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opensecura / 3p / lowrisc / opentitan / 8278abd644594117d64579f28ebe29b9c76a2758 / . / sw / device / tests
tree: 0a4eefcfc2614c533c714d8324d26522109b8fd7 [path history] [tgz]
  1. autogen/
  2. closed_source/
  3. crypto/
  4. otbn_data/
  5. sim_dv/
  6. aes_entropy_test.c
  7. aes_idle_test.c
  8. aes_masking_off_test.c
  9. aes_smoketest.c
  10. alert_handler_lpg_clkoff_test.c
  11. alert_handler_lpg_reset_toggle.c
  12. alert_handler_lpg_sleep_mode_alerts.c
  13. alert_handler_lpg_sleep_mode_pings.c
  14. alert_handler_ping_timeout_test.c
  15. alert_handler_reverse_ping_in_deep_sleep_test.c
  16. aon_timer_irq_test.c
  17. aon_timer_sleep_wdog_sleep_pause_test.c
  18. aon_timer_smoketest.c
  19. aon_timer_wdog_bite_reset_test.c
  20. aon_timer_wdog_lc_escalate_test.c
  21. ast_clk_outs_test.c
  22. BUILD
  23. chip_power_idle_load.c
  24. chip_power_sleep_load.c
  25. clkmgr_external_clk_src_for_sw_fast_test.c
  26. clkmgr_external_clk_src_for_sw_impl.c
  27. clkmgr_external_clk_src_for_sw_impl.h
  28. clkmgr_external_clk_src_for_sw_slow_test.c
  29. clkmgr_jitter_test.c
  30. clkmgr_off_aes_trans_test.c
  31. clkmgr_off_hmac_trans_test.c
  32. clkmgr_off_kmac_trans_test.c
  33. clkmgr_off_otbn_trans_test.c
  34. clkmgr_off_peri_test.c
  35. clkmgr_off_trans_impl.c
  36. clkmgr_off_trans_impl.h
  37. clkmgr_reset_frequency_test.c
  38. clkmgr_sleep_frequency_test.c
  39. clkmgr_smoketest.c
  40. coverage_test.c
  41. crt_test.c
  42. csrng_edn_concurrency_test.c
  43. csrng_kat_test.c
  44. csrng_smoketest.c
  45. entropy_src_ast_rng_req_test.c
  46. entropy_src_csrng_test.c
  47. entropy_src_edn_reqs_test.c
  48. entropy_src_fw_ovr_test.c
  49. entropy_src_kat_impl.c
  50. entropy_src_kat_impl.h
  51. entropy_src_kat_test.c
  52. entropy_src_smoketest.c
  53. example_concurrency_test.c
  54. example_test_from_flash.c
  55. example_test_from_rom.c
  56. flash_ctrl_clock_freqs_test.c
  57. flash_ctrl_idle_low_power_test.c
  58. flash_ctrl_ops_test.c
  59. flash_ctrl_test.c
  60. gpio_pinmux_test.c
  61. gpio_smoketest.c
  62. hmac_enc_idle_test.c
  63. hmac_enc_test.c
  64. hmac_smoketest.c
  65. keymgr_key_derivation_test.c
  66. keymgr_sideload_aes_test.c
  67. keymgr_sideload_kmac_test.c
  68. keymgr_sideload_otbn_test.c
  69. kmac_app_rom_test.c
  70. kmac_entropy_test.c
  71. kmac_idle_test.c
  72. kmac_mode_cshake_test.c
  73. kmac_mode_kmac_test.c
  74. kmac_smoketest.c
  75. lc_ctrl_otp_hw_cfg_test.c
  76. otbn_ecdsa_op_irq_test.c
  77. otbn_irq_test.c
  78. otbn_mem_scramble_test.c
  79. otbn_randomness_impl.c
  80. otbn_randomness_impl.h
  81. otbn_randomness_test.c
  82. otbn_rsa_test.c
  83. otbn_smoketest.c
  84. otp_ctrl_smoketest.c
  85. plic_sw_irq_test.c
  86. pmp_smoketest_napot.c
  87. pmp_smoketest_tor.c
  88. power_virus_systemtest.c
  89. pwrmgr_sleep_disabled_test.c
  90. pwrmgr_smoketest.c
  91. pwrmgr_wdog_reset_reqs_test.c
  92. README.md
  93. rstmgr_alert_info_test.c
  94. rstmgr_cpu_info_test.c
  95. rstmgr_smoketest.c
  96. rstmgr_sw_req_test.c
  97. rstmgr_sw_rst_ctrl_test.c
  98. rv_core_ibex_address_translation_test.c
  99. rv_core_ibex_address_translation_test.S
  100. rv_core_ibex_icache_invalidate_test.c
  101. rv_core_ibex_nmi_irq_test.c
  102. rv_core_ibex_rnd_test.c
  103. rv_core_ibex_rnd_test.S
  104. rv_plic_smoketest.c
  105. rv_timer_smoketest.c
  106. sensor_ctrl_alerts.c
  107. sensor_ctrl_wakeup.c
  108. sleep_pwm_pulses_test.c
  109. spi_host_smoketest.c
  110. spi_passthru_test.c
  111. sram_ctrl_execution_test.c
  112. sram_ctrl_sleep_sram_ret_contents_test.c
  113. sram_ctrl_smoketest.c
  114. uart_smoketest.c
  115. usbdev_stream_test.c
  116. usbdev_test.c
sw/device/tests/README.md

Chip-Level Tests

Overview

This subtree contains three types of chip-level tests that are capable of running across all OpenTitan verification targets, using the on-device test framework. These targets include: DV simulation, Verilator simulation, FPGA, and eventually silicon.

Test Types

  • Chip-level Tests - A collection of software level tests that run on OpenTitan hardware, whose main purpose is pre-silicon verification and post-silicon bringup. These tests consist of: smoke, IP integration, and system-level tests. While most of these tests are top-level agnostic, some are not.
    • Smoke Tests - A software level test, written in C using DIFs, that performs a minimal set of operations on a given IP block to verify that it is alive and functioning.
    • IP Integration Tests - A software level test, written in C, that exercises some specific functionality specific to a given IP and toplevel.
    • System-level Scenario Test - A software level test, written in C, that mimics complex system level use case scenarios. Such a test is designed to encompass multiple pieces of functionality tested by the IP integration tests.

Organization and Style Guide

File Naming Conventions

  • Smoke tests: {IP name}_smoketest.c
  • IP Integration tests: {IP name}[_{feature}]_test.c
  • System-level tests: {use case}_systemtest.c

Subfoldering Rules

  • Smoke tests will be placed in (one per IP):
    • (generic) sw/device/tests/
    • (earlgrey-specific) sw/device/tests/earlgrey/
    • ({toplevel}-specific) sw/device/tests/{toplevel}/
  • IP Integration tests will be placed in the same folders as above.
  • System-level tests will be placed in the same folders as above.
  • IP Integration Test data (some tests, e.g. OTBN, load data files): sw/device/tests/{IP}_data/
  • Target-specific tests will be subfoldered by target (see below).

Subfoldering Target-Specific Tests

Ideally all smoke, IP integration, and system-level tests should be target agnostic. However, some tests require emulation of host capabilities, such as an external SPI or I2C host, an external host to encrypt/decrypt data, or an external host that toggles GPIO pins. Eventually, host-side test initiation tools and the on-device test framework will make host emulation opaque to each chip-level test. However, until then, host emulation depends on the target (e.g., DV vs. Verilator simulation). Therefore, chip-level tests that require external stimulation from the host, will be subfoldered by target, under the appropriate toplevel folder above. One example of such a test is the sw/device/tests/sim_dv/gpio_test.c, which is subfoldered under ../sim_dv/ to indicate it is a target-specific test.

Writing a Chip-Level Test

For instructions on how to write a chip-level test, refer to the on-device test framework page.

List of Tests

Smoke

TBD

IP Integration

{{< incGenFromIpDesc “/hw/top_earlgrey/data/chip_testplan.hjson” “testplan” >}}

System-Level (Use Case)

TBD