commit 81dcffceaf88273e58543988c7012d52dc7ff190
author Steve Nelson <steve.nelson@wdc.com> Wed Nov 18 06:16:06 2020 -0800
committer rasmus-madsen <53917183+rasmus-madsen@users.noreply.github.com> Thu Nov 19 19:02:36 2020 +0100
tree 9a5a71ba6b268648b8a7f97d463dcb7e97387d8b
parent 02f9c5089966dfc1e3e5a3f009caef3e17eb070f

[csrng/dv] Removed ack register to match latest rtl

Signed-off-by: Steve Nelson <steve.nelson@wdc.com>

hw/ip/csrng/dv/env/csrng_scoreboard.sv

diff --git a/hw/ip/csrng/dv/env/csrng_scoreboard.sv b/hw/ip/csrng/dv/env/csrng_scoreboard.sv
index dae1f90..9e62805 100644
--- a/hw/ip/csrng/dv/env/csrng_scoreboard.sv
+++ b/hw/ip/csrng/dv/env/csrng_scoreboard.sv
@@ -47,7 +47,7 @@
     uvm_reg csr;
     bit     do_read_check   = 1'b1;
     bit     write           = item.is_write();
-    uvm_reg_addr_t csr_addr = ral.align_to_word_addr(item.a_addr);
+    uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
 
     bit addr_phase_read   = (!write && channel == AddrChannel);
     bit addr_phase_write  = (write && channel == AddrChannel);
@@ -94,9 +94,6 @@
       "sw_cmd_sts": begin
         do_read_check = 1'b0;
       end
-      "sw_cmd_ack": begin
-        do_read_check = 1'b0;
-      end
       "genbits_vld": begin
         do_read_check = 1'b0;
       end

hw/ip/csrng/dv/env/seq_lib/csrng_sanity_vseq.sv

diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_sanity_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_sanity_vseq.sv
index df29e8f..af295f0 100644
--- a/hw/ip/csrng/dv/env/seq_lib/csrng_sanity_vseq.sv
+++ b/hw/ip/csrng/dv/env/seq_lib/csrng_sanity_vseq.sv
@@ -27,9 +27,6 @@
     // Write CSRNG Cmd_Req Register - Generate Command
     wr_cmd_req(.acmd(Generate), .clen(0), .flags(0), .glen(1));
 
-    // Wait for CSRNG Cmd_Ack
-    csr_spinwait(.ptr(ral.sw_cmd_ack.cmd_ack), .exp_data(1'b1));
-
     // Wait for CSRNG genbits_vld
     csr_spinwait(.ptr(ral.genbits_vld.genbits_vld), .exp_data(1'b1));