Update riscv_compliance to riscv/riscv-compliance@5a978cf
Update code from upstream repository https://github.com/riscv/riscv-
compliance.git to revision 5a978cfd444d5e640150d46703deda99057b2bbb
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
diff --git a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
index 594d16f..4810715 100644
--- a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
+++ b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
@@ -1,7 +1,7 @@
From 5fb77a9e75207f4a35d0b1c4ad9f0ce7faba3814 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 15 Apr 2020 15:45:31 +0100
-Subject: [PATCH 1/4] Add configurable trap alignment and entry point to p
+Subject: [PATCH 1/5] Add configurable trap alignment and entry point to p
test-env
---
diff --git a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
index 25c4bb8..7ba5629 100644
--- a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
+++ b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
@@ -1,18 +1,18 @@
-From cc071b648ed45ddf86295baad7636ead4a71c8c3 Mon Sep 17 00:00:00 2001
+From 75061e3a20f7c4e1a4768ea3f455e106efec7b19 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 15 Apr 2020 15:44:54 +0100
-Subject: [PATCH 2/4] Add OpenTitan target
+Subject: [PATCH 2/5] Add OpenTitan target
---
- riscv-target/opentitan/README.md | 134 ++++++++++++++++++
+ riscv-target/opentitan/README.md | 144 ++++++++++++++++++
riscv-target/opentitan/compliance_io.h | 22 +++
riscv-target/opentitan/compliance_test.h | 35 +++++
- .../opentitan/device/rv32imc/Makefile.include | 74 ++++++++++
- .../opentitan/device/rv32imc/isa.yaml | 49 +++++++
+ .../opentitan/device/rv32imc/Makefile.include | 79 ++++++++++
+ .../opentitan/device/rv32imc/isa.yaml | 49 ++++++
riscv-target/opentitan/device/rv32imc/main.c | 39 +++++
.../opentitan/device/rv32imc/platform.yaml | 10 ++
.../opentitan/device/rv32imc/run_rvc_test.S | 85 +++++++++++
- 8 files changed, 448 insertions(+)
+ 8 files changed, 463 insertions(+)
create mode 100644 riscv-target/opentitan/README.md
create mode 100644 riscv-target/opentitan/compliance_io.h
create mode 100644 riscv-target/opentitan/compliance_test.h
@@ -24,15 +24,16 @@
diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md
new file mode 100644
-index 0000000..f75c384
+index 0000000..6823fe2
--- /dev/null
+++ b/riscv-target/opentitan/README.md
-@@ -0,0 +1,134 @@
+@@ -0,0 +1,144 @@
+
+# Overview
+The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator.
-+OpenTitan is an open source project to build transparent, high-quality reference designs for silicon root of trust chips.
-+Please see the [OpenTitan website](https://opentitan.org) for more details.
++OpenTitan is an open source project to build transparent, high-quality reference
++designs for silicon root of trust chips. Please see the [OpenTitan
++website](https://opentitan.org) for more details.
+
+To run on Verilator, set the variables below
+
@@ -42,8 +43,8 @@
+$ export OT_TARGET=verilator
+```
+
-+To run on FPGA, set the variables below.
-+The `FPGA_UART` variable must be set to wherever a valid device is connected.
++To run on FPGA, set the variables below. The `FPGA_UART` variable must be set
++to wherever a valid device is connected.
+
+```console
+$ export RISCV_TARGET=opentitan
@@ -58,17 +59,23 @@
+$ stty -F $OT_FPGA_UART 230400 raw
+```
+
-+By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
-+If your Verilator build is at a different location, please set that as well when running with Verilator.
++By default, the test assumes there exists a valid Verilator build at
++`${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
++If your Verilator build is at a different location, please set that as well when
++running with Verilator.
+
+```console
+$ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD}
+```
+
-+When running against FPGA, the test assumes the FPGA is already programmed and ready to go with spiflash available at `${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export`
-+To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/).
++When running against FPGA, the test assumes the FPGA is already programmed and
++ready to go with spiflash available at
++`${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export` To quickly get started
++with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start
++guide](https://docs.opentitan.org/doc/ug/quickstart/).
+
-+Finally the support software must be built, including the boot_rom when using the verilator target.
++Finally the support software must be built, including the boot_rom when using
++the verilator target.
+
+```console
+$ cd $REPO_TOP
@@ -76,9 +83,9 @@
+$ ninja -C ./build-out all
+```
+
-+Now, run the tests from the riscv_compliance directory.
-+The following output will be seen (software build steps are truncated).
-+The example below uses Verilator as an example, but the FPGA output is nearly identical.
++Now, run the tests from the riscv_compliance directory. The following output
++will be seen (software build steps are truncated). The example below uses
++Verilator as an example, but the FPGA output is nearly identical.
+
+```console
+$ cd $RISCV_COMPLIANCE_REPO_BASE
@@ -140,11 +147,14 @@
+OK: 48/48
+```
+
-+There are several test suites that can be run `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr`.
-+Change the `RISCV_ISA` argument passed to `make` to choose between them.
++There are several test suites that can be run `rv32i`, `rv32im`, `rv32imc` and
++`rv32Zicsr`. Change the `RISCV_ISA` argument passed to `make` to choose between
++them.
+
+## Changing targets
-+When switching between targets (i.e. between FPGA and verilator) the `work` directory in the `riscv_compliance` tree must be remove to force a software rebuild.
++When switching between targets (i.e. between FPGA and verilator) the `work`
++directory in the `riscv_compliance` tree must be remove to force a software
++rebuild.
+
+```console
+$ cd $RISCV_COMPLIANCE_REPO_BASE
@@ -233,10 +243,10 @@
+#endif
diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include
new file mode 100644
-index 0000000..a20c279
+index 0000000..5ba548a
--- /dev/null
+++ b/riscv-target/opentitan/device/rv32imc/Makefile.include
-@@ -0,0 +1,74 @@
+@@ -0,0 +1,79 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
@@ -262,8 +272,13 @@
+else
+ CARG = -DSIMULATION=1
+ MAKEARG = SIM=1
++ # Verilator can be run in parallel mode so alter log output to prepend with
++ # test name, also increase uart_timeout as with parallel runs on CI individual
++ # test execution can take greater than 60 seconds.
+ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \
-+ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem
++ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem \
++ --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \
++ --uart_timeout 240
+ OT_SW_TARGET = sim_verilator
+endif
+
diff --git a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
index 9a05bf5..017774c 100644
--- a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
+++ b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
@@ -1,7 +1,7 @@
-From 7dc77a7b973028b96bb31deb7cb5d6d8fdc967f7 Mon Sep 17 00:00:00 2001
+From c59d607e9c0b3d362882d7560b6e48ae9dc31740 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 15 Apr 2020 18:39:08 +0100
-Subject: [PATCH 3/4] Remove tests that do not pass on OpenTitan
+Subject: [PATCH 3/5] Remove tests that do not pass on OpenTitan
---
riscv-test-suite/rv32i/Makefrag | 15 +++++++++------
diff --git a/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch b/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch
index 43cc8fd..f91bf48 100644
--- a/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch
+++ b/sw/vendor/patches/riscv_compliance/0004-Enable-parallel-runs.patch
@@ -1,15 +1,15 @@
-From 00a12c1448157003e4926f0e9df105589816ef63 Mon Sep 17 00:00:00 2001
+From 5ddb5a17cb8f61955cb6103682d6190abe61e181 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Fri, 17 Apr 2020 15:02:48 +0100
-Subject: [PATCH 4/4] Enable parallel runs
+Subject: [PATCH 4/5] Enable parallel runs
---
Makefile | 5 +++++
- riscv-target/opentitan/README.md | 14 ++++++++++++++
- 2 files changed, 19 insertions(+)
+ riscv-target/opentitan/README.md | 16 ++++++++++++++++
+ 2 files changed, 21 insertions(+)
diff --git a/Makefile b/Makefile
-index 25557c1..8f7b04a 100644
+index 25557c1..02c524a 100644
--- a/Makefile
+++ b/Makefile
@@ -50,6 +50,11 @@ else
@@ -17,7 +17,7 @@
JOBS ?= -j8 --max-load=4
endif
+ ifeq ($(RISCV_TARGET),opentitan)
-+ ifeq ($(OT_TARGET), verilator)
++ ifeq ($(OT_TARGET),verilator)
+ JOBS ?= -j4
+ endif
+ endif
@@ -25,16 +25,18 @@
default: $(DEFAULT_TARGET)
diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md
-index f75c384..b1756cd 100644
+index 6823fe2..71baa3c 100644
--- a/riscv-target/opentitan/README.md
+++ b/riscv-target/opentitan/README.md
-@@ -121,6 +121,20 @@ $ cd $RISCV_COMPLIANCE_REPO_BASE
+@@ -131,6 +131,22 @@ $ cd $RISCV_COMPLIANCE_REPO_BASE
$ rm -rf ./work
```
+## Parallel runs
-+When running against the `verilator` target parallel make jobs are used (via passing `-j4` to make internally).
-+Parallel runs can be disabled by passing `PARALLEL=0` to the `make` command or the `-j` used can be altered with the `JOBS` argument.
++When running against the `verilator` target parallel make jobs are used (via
++passing `-j4` to make internally). Parallel runs can be disabled by passing
++`PARALLEL=0` to the `make` command or the `-j` used can be altered with the
++`JOBS` argument.
+
+Disable parallel runs:
+```console
diff --git a/sw/vendor/patches/riscv_compliance/0005-Update-.vmem-paths-with-new-naming.patch b/sw/vendor/patches/riscv_compliance/0005-Update-.vmem-paths-with-new-naming.patch
new file mode 100644
index 0000000..cbafdf5
--- /dev/null
+++ b/sw/vendor/patches/riscv_compliance/0005-Update-.vmem-paths-with-new-naming.patch
@@ -0,0 +1,33 @@
+From 00161b024ca6169e0750750da136a8c1e4b0c3a5 Mon Sep 17 00:00:00 2001
+From: Greg Chadwick <gac@lowrisc.org>
+Date: Mon, 20 Apr 2020 13:41:51 +0100
+Subject: [PATCH 5/5] Update .vmem paths with new naming
+
+---
+ riscv-target/opentitan/device/rv32imc/Makefile.include | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include
+index 5ba548a..e1be9d8 100644
+--- a/riscv-target/opentitan/device/rv32imc/Makefile.include
++++ b/riscv-target/opentitan/device/rv32imc/Makefile.include
+@@ -26,8 +26,8 @@ else
+ # Verilator can be run in parallel mode so alter log output to prepend with
+ # test name, also increase uart_timeout as with parallel runs on CI individual
+ # test execution can take greater than 60 seconds.
+- PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \
+- --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem \
++ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).32.vmem \
++ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.32.vmem \
+ --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \
+ --uart_timeout 240
+ OT_SW_TARGET = sim_verilator
+@@ -76,4 +76,4 @@ COMPILE_TARGET += \
+ $$(RISCV_READELF) -a $$(@) > $$(@).readelf; \
+ $$(RISCV_NM) $$(@) > $$(@).nm; \
+ $$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \
+- srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem
++ srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).32.vmem -vmem
+--
+2.17.1
+
diff --git a/sw/vendor/riscv_compliance/Makefile b/sw/vendor/riscv_compliance/Makefile
index 8f7b04a..02c524a 100644
--- a/sw/vendor/riscv_compliance/Makefile
+++ b/sw/vendor/riscv_compliance/Makefile
@@ -51,7 +51,7 @@
JOBS ?= -j8 --max-load=4
endif
ifeq ($(RISCV_TARGET),opentitan)
- ifeq ($(OT_TARGET), verilator)
+ ifeq ($(OT_TARGET),verilator)
JOBS ?= -j4
endif
endif
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
index b1756cd..71baa3c 100644
--- a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
+++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
@@ -1,8 +1,9 @@
# Overview
The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator.
-OpenTitan is an open source project to build transparent, high-quality reference designs for silicon root of trust chips.
-Please see the [OpenTitan website](https://opentitan.org) for more details.
+OpenTitan is an open source project to build transparent, high-quality reference
+designs for silicon root of trust chips. Please see the [OpenTitan
+website](https://opentitan.org) for more details.
To run on Verilator, set the variables below
@@ -12,8 +13,8 @@
$ export OT_TARGET=verilator
```
-To run on FPGA, set the variables below.
-The `FPGA_UART` variable must be set to wherever a valid device is connected.
+To run on FPGA, set the variables below. The `FPGA_UART` variable must be set
+to wherever a valid device is connected.
```console
$ export RISCV_TARGET=opentitan
@@ -28,17 +29,23 @@
$ stty -F $OT_FPGA_UART 230400 raw
```
-By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
-If your Verilator build is at a different location, please set that as well when running with Verilator.
+By default, the test assumes there exists a valid Verilator build at
+`${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
+If your Verilator build is at a different location, please set that as well when
+running with Verilator.
```console
$ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD}
```
-When running against FPGA, the test assumes the FPGA is already programmed and ready to go with spiflash available at `${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export`
-To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/).
+When running against FPGA, the test assumes the FPGA is already programmed and
+ready to go with spiflash available at
+`${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export` To quickly get started
+with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start
+guide](https://docs.opentitan.org/doc/ug/quickstart/).
-Finally the support software must be built, including the boot_rom when using the verilator target.
+Finally the support software must be built, including the boot_rom when using
+the verilator target.
```console
$ cd $REPO_TOP
@@ -46,9 +53,9 @@
$ ninja -C ./build-out all
```
-Now, run the tests from the riscv_compliance directory.
-The following output will be seen (software build steps are truncated).
-The example below uses Verilator as an example, but the FPGA output is nearly identical.
+Now, run the tests from the riscv_compliance directory. The following output
+will be seen (software build steps are truncated). The example below uses
+Verilator as an example, but the FPGA output is nearly identical.
```console
$ cd $RISCV_COMPLIANCE_REPO_BASE
@@ -110,11 +117,14 @@
OK: 48/48
```
-There are several test suites that can be run `rv32i`, `rv32im`, `rv32imc` and `rv32Zicsr`.
-Change the `RISCV_ISA` argument passed to `make` to choose between them.
+There are several test suites that can be run `rv32i`, `rv32im`, `rv32imc` and
+`rv32Zicsr`. Change the `RISCV_ISA` argument passed to `make` to choose between
+them.
## Changing targets
-When switching between targets (i.e. between FPGA and verilator) the `work` directory in the `riscv_compliance` tree must be remove to force a software rebuild.
+When switching between targets (i.e. between FPGA and verilator) the `work`
+directory in the `riscv_compliance` tree must be remove to force a software
+rebuild.
```console
$ cd $RISCV_COMPLIANCE_REPO_BASE
@@ -122,8 +132,10 @@
```
## Parallel runs
-When running against the `verilator` target parallel make jobs are used (via passing `-j4` to make internally).
-Parallel runs can be disabled by passing `PARALLEL=0` to the `make` command or the `-j` used can be altered with the `JOBS` argument.
+When running against the `verilator` target parallel make jobs are used (via
+passing `-j4` to make internally). Parallel runs can be disabled by passing
+`PARALLEL=0` to the `make` command or the `-j` used can be altered with the
+`JOBS` argument.
Disable parallel runs:
```console
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
index a20c279..e1be9d8 100644
--- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
+++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -23,8 +23,13 @@
else
CARG = -DSIMULATION=1
MAKEARG = SIM=1
- PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).vmem \
- --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.vmem
+ # Verilator can be run in parallel mode so alter log output to prepend with
+ # test name, also increase uart_timeout as with parallel runs on CI individual
+ # test execution can take greater than 60 seconds.
+ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<).32.vmem \
+ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.32.vmem \
+ --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \
+ --uart_timeout 240
OT_SW_TARGET = sim_verilator
endif
@@ -71,4 +76,4 @@
$$(RISCV_READELF) -a $$(@) > $$(@).readelf; \
$$(RISCV_NM) $$(@) > $$(@).nm; \
$$(RISCV_OBJCOPY) -O binary $$(@) $$(@).bin; \
- srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).vmem -vmem
+ srec_cat $$(@).bin -binary -offset 0x0000 -byte-swap 4 -o $$(@).32.vmem -vmem
