| commit | 0a447e50511aa1d18f015a13d45aa480dd25c3eb | [log] [tgz] |
|---|---|---|
| author | Silvestrs Timofejevs <silvestrst@lowrisc.org> | Wed Dec 18 08:26:46 2019 +0000 |
| committer | Garret Kelly <Garret.Kelly@gmail.com> | Fri Jan 24 10:33:01 2020 -0500 |
| tree | 930d67aac16b1b139cc8ce48dd6c8926a40b872d | |
| parent | 5703b90eb2fc9ee5c35628696ca876e9e37ebf0f [diff] |
[dif_plic] Introduce DIF PLIC library
PLIC (Platform Level Interrupt Controller) multiplexes various device
interrupts onto the external interrupt lines. Single PLIC can facilitate
interrupt delivery to 1 or more targets.
This change introduces the PLIC DIF (Device Interface Functions) for
programming PLIC.
There is a number of important details that derive from the PLIC integration with
the Earl Grey, and the PLIC implementation itself:
1) The sequence of interrupt sources as passed to the PLIC gateway,
dictates the register layouts and the interrupt bit indexes in these
registers. It also determines interrupt source IDs.
2) Same peripheral interrupts are always packed together in the
registers, and their IDs are consecutive.
3) There is a set of per target registers that control the interrupt
delivery to these targets (Interrupt Enable, Threshold and
Claim/Complete).
4) Any interrupt source can interrupt any of the PLIC supported targets
providing the target specific registers are configured appropriately.
Note:
Presently, PLIC documentation is generated with a default parameterisation,
which does not match the Earl Grey PLIC implementation.
Relevant verilog source files to understand the Earl Grey PLIC
implementation:
hw/top_earlgrey/rtl/autogen/rv_plic_reg_top.sv:
registers implementation inside PLIC
hw/top_earlgrey/rtl/autogen/rv_plic.sv:
PLIC implementation
hw/top_earlgrey/rtl/autogen/top_earlgrey.sv:
IP blocks connected together, in particular "intr_vector" (size, how it is
assigned, and how it is passed to PLIC).
Signed-off-by: Silvestrs Timofejevs <silvestrst@lowrisc.org>
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