| commit | 2405f7feec9fa9859fa81f0004e21fd23c1d6810 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Jan 26 10:36:01 2021 +0000 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Tue Jan 26 16:59:07 2021 +0000 |
| tree | c310f74b1b7447cde3f3baed766546f65be91e20 | |
| parent | d6a2ed1a7360fa85e96dc7529dcfebca5caca604 [diff] |
[prim] Properly fix widths in tlul_adapter_sram In commit 51ea6b8, I tried to sort out widths properly when SramDw != TL_DW but didn't quite get it right. In this module, we have two FIFOs (u_reqfifo and u_rspfifo) for bus accesses. These should be sized for the bus width, rather than the SRAM width. Doing so gets rid of some nasty casts (and an out-of-date waiver), which is nice, and should fix a remaining AscentLint width mismatch error. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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