[top] Latest ast integration - ast alert interface change - flash / ast alert connection Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 431d31f..c899403 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -1303,6 +1303,19 @@ index: -1 } { + name: otp_alert + struct: ast_dif + package: ast_pkg + type: uni + act: req + width: 1 + inst_name: otp_ctrl + default: "" + external: true + top_signame: otp_alert + index: -1 + } + { name: edn struct: edn package: edn_pkg @@ -3268,6 +3281,19 @@ index: -1 } { + name: ast_init_done + struct: logic + type: uni + act: rcv + width: 1 + inst_name: sensor_ctrl_aon + default: "" + package: "" + external: true + top_signame: ast_init_done + index: -1 + } + { name: ast2pinmux struct: logic type: uni @@ -5606,6 +5632,19 @@ inst_name: eflash index: -1 } + { + struct: ast_dif + package: ast_pkg + type: uni + act: req + name: flash_alert + inst_name: eflash + width: 1 + default: "" + external: true + top_signame: flash_alert + index: -1 + } ] clock_connections: { @@ -6240,6 +6279,7 @@ clkmgr_aon.jitter_en: clk_main_jitter_en clkmgr_aon.ast_clk_byp_req: ast_clk_byp_req clkmgr_aon.ast_clk_byp_ack: ast_clk_byp_ack + eflash.flash_alert: flash_alert eflash.flash_bist_enable: flash_bist_enable eflash.flash_power_down_h: flash_power_down_h eflash.flash_power_ready_h: flash_power_ready_h @@ -6251,9 +6291,11 @@ pwrmgr_aon.pwr_ast: pwrmgr_ast otp_ctrl.otp_ast_pwr_seq: "" otp_ctrl.otp_ast_pwr_seq_h: "" + otp_ctrl.otp_alert: otp_alert sensor_ctrl_aon.ast_alert: sensor_ctrl_ast_alert sensor_ctrl_aon.ast_status: sensor_ctrl_ast_status sensor_ctrl_aon.ast2pinmux: ast2pinmux + sensor_ctrl_aon.ast_init_done: ast_init_done usbdev.usb_ref_val: "" usbdev.usb_ref_pulse: "" clkmgr_aon.clocks_ast: clks_ast @@ -11348,14 +11390,42 @@ module_name: sensor_ctrl_aon } { - name: sensor_ctrl_aon_recov_ls + name: sensor_ctrl_aon_recov_fla width: 1 type: alert async: "0" module_name: sensor_ctrl_aon } { - name: sensor_ctrl_aon_recov_ot + name: sensor_ctrl_aon_recov_otp + width: 1 + type: alert + async: "0" + module_name: sensor_ctrl_aon + } + { + name: sensor_ctrl_aon_recov_ot0 + width: 1 + type: alert + async: "0" + module_name: sensor_ctrl_aon + } + { + name: sensor_ctrl_aon_recov_ot1 + width: 1 + type: alert + async: "0" + module_name: sensor_ctrl_aon + } + { + name: sensor_ctrl_aon_recov_ot2 + width: 1 + type: alert + async: "0" + module_name: sensor_ctrl_aon + } + { + name: sensor_ctrl_aon_recov_ot3 width: 1 type: alert async: "0" @@ -11923,6 +11993,19 @@ index: -1 } { + name: otp_alert + struct: ast_dif + package: ast_pkg + type: uni + act: req + width: 1 + inst_name: otp_ctrl + default: "" + external: true + top_signame: otp_alert + index: -1 + } + { name: edn struct: edn package: edn_pkg @@ -13448,6 +13531,19 @@ index: -1 } { + name: ast_init_done + struct: logic + type: uni + act: rcv + width: 1 + inst_name: sensor_ctrl_aon + default: "" + package: "" + external: true + top_signame: ast_init_done + index: -1 + } + { name: ast2pinmux struct: logic type: uni @@ -14811,6 +14907,19 @@ index: -1 } { + struct: ast_dif + package: ast_pkg + type: uni + act: req + name: flash_alert + inst_name: eflash + width: 1 + default: "" + external: true + top_signame: flash_alert + index: -1 + } + { name: tl_corei struct: tl package: tlul_pkg @@ -15765,6 +15874,18 @@ netname: ast_clk_byp_ack } { + package: ast_pkg + struct: ast_dif + signame: flash_alert_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: flash_alert + } + { package: lc_ctrl_pkg struct: lc_tx signame: flash_bist_enable_i @@ -15934,6 +16055,18 @@ } { package: ast_pkg + struct: ast_dif + signame: otp_alert_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: otp_alert + } + { + package: ast_pkg struct: ast_alert_req signame: sensor_ctrl_ast_alert_req_i width: 1 @@ -15983,6 +16116,18 @@ { package: "" struct: logic + signame: ast_init_done_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: ast_init_done + } + { + package: "" + struct: logic signame: usbdev_usb_ref_val_o width: 1 type: uni
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index b4c4d02..d1aa234 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -766,6 +766,13 @@ act: "rcv" name: "flash_test_voltage_h" }, + + { struct: "ast_dif", + package: "ast_pkg", + type: "uni" + act: "req" + name: "flash_alert" + }, ], }, ], @@ -980,6 +987,7 @@ 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', 'clkmgr_aon.ast_clk_byp_req' : 'ast_clk_byp_req', 'clkmgr_aon.ast_clk_byp_ack' : 'ast_clk_byp_ack', + 'eflash.flash_alert' : 'flash_alert', 'eflash.flash_bist_enable' : 'flash_bist_enable', 'eflash.flash_power_down_h' : 'flash_power_down_h', 'eflash.flash_power_ready_h' : 'flash_power_ready_h', @@ -991,9 +999,11 @@ 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast', 'otp_ctrl.otp_ast_pwr_seq' : '', 'otp_ctrl.otp_ast_pwr_seq_h' : '', + 'otp_ctrl.otp_alert' : 'otp_alert', 'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert', 'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status', 'sensor_ctrl_aon.ast2pinmux' : 'ast2pinmux', + 'sensor_ctrl_aon.ast_init_done': 'ast_init_done', 'usbdev.usb_ref_val' : '', 'usbdev.usb_ref_pulse' : '', },
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv index 3e51530..5376384 100644 --- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -15,23 +15,27 @@ assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4]; assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5]; assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6]; -assign alert_if[11].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; -assign alert_if[12].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1]; -assign alert_if[13].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; -assign alert_if[14].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; -assign alert_if[15].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; -assign alert_if[16].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; -assign alert_if[17].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; -assign alert_if[18].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; -assign alert_if[19].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; -assign alert_if[20].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; -assign alert_if[21].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; -assign alert_if[22].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; -assign alert_if[23].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; -assign alert_if[24].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; -assign alert_if[25].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; -assign alert_if[26].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; -assign alert_if[27].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1]; -assign alert_if[28].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; -assign alert_if[29].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; -assign alert_if[30].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0]; +assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7]; +assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8]; +assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9]; +assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10]; +assign alert_if[15].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; +assign alert_if[16].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1]; +assign alert_if[17].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0]; +assign alert_if[18].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1]; +assign alert_if[19].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2]; +assign alert_if[20].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3]; +assign alert_if[21].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[22].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[23].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0]; +assign alert_if[24].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1]; +assign alert_if[25].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[26].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[27].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[28].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[29].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[30].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[31].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1]; +assign alert_if[32].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[33].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[34].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv index 63196b7..98071fe 100644 --- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -14,8 +14,12 @@ "sensor_ctrl_aon_recov_gd", "sensor_ctrl_aon_recov_ts_hi", "sensor_ctrl_aon_recov_ts_lo", - "sensor_ctrl_aon_recov_ls", - "sensor_ctrl_aon_recov_ot", + "sensor_ctrl_aon_recov_fla", + "sensor_ctrl_aon_recov_otp", + "sensor_ctrl_aon_recov_ot0", + "sensor_ctrl_aon_recov_ot1", + "sensor_ctrl_aon_recov_ot2", + "sensor_ctrl_aon_recov_ot3", "sram_ctrl_ret_aon_fatal_intg_error", "sram_ctrl_ret_aon_fatal_parity_error", "flash_ctrl_recov_err", @@ -38,4 +42,4 @@ "rom_ctrl_fatal" }; -parameter uint NUM_ALERTS = 31; +parameter uint NUM_ALERTS = 35;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson index 6cd3aa7..7ab2a67 100644 --- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson +++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@ { name: "NAlerts", desc: "Number of peripheral inputs", type: "int", - default: "31", + default: "35", local: "true" }, { name: "EscCntDw", @@ -66,7 +66,7 @@ { name: "AsyncOn", desc: "Number of peripheral outputs", type: "logic [NAlerts-1:0]", - default: "31'b1111111111111111110000000000000", + default: "35'b11111111111111111100000000000000000", local: "true" }, { name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv index 159b9c4..ba2545e 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@ package alert_handler_reg_pkg; // Param list - parameter int NAlerts = 31; + parameter int NAlerts = 35; parameter int EscCntDw = 32; parameter int AccuCntDw = 16; - parameter logic [NAlerts-1:0] AsyncOn = 31'b1111111111111111110000000000000; + parameter logic [NAlerts-1:0] AsyncOn = 35'b11111111111111111100000000000000000; parameter int N_CLASSES = 4; parameter int N_ESC_SEV = 4; parameter int N_PHASES = 4; @@ -458,15 +458,15 @@ // Register -> HW type typedef struct packed { - alert_handler_reg2hw_intr_state_reg_t intr_state; // [979:976] - alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [975:972] - alert_handler_reg2hw_intr_test_reg_t intr_test; // [971:964] - alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [963:940] - alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [939:939] - alert_handler_reg2hw_alert_regwen_mreg_t [30:0] alert_regwen; // [938:908] - alert_handler_reg2hw_alert_en_mreg_t [30:0] alert_en; // [907:877] - alert_handler_reg2hw_alert_class_mreg_t [30:0] alert_class; // [876:815] - alert_handler_reg2hw_alert_cause_mreg_t [30:0] alert_cause; // [814:784] + alert_handler_reg2hw_intr_state_reg_t intr_state; // [999:996] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [995:992] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [991:984] + alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [983:960] + alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [959:959] + alert_handler_reg2hw_alert_regwen_mreg_t [34:0] alert_regwen; // [958:924] + alert_handler_reg2hw_alert_en_mreg_t [34:0] alert_en; // [923:889] + alert_handler_reg2hw_alert_class_mreg_t [34:0] alert_class; // [888:819] + alert_handler_reg2hw_alert_cause_mreg_t [34:0] alert_cause; // [818:784] alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780] alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772] alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768] @@ -506,8 +506,8 @@ // HW -> register type typedef struct packed { - alert_handler_hw2reg_intr_state_reg_t intr_state; // [289:282] - alert_handler_hw2reg_alert_cause_mreg_t [30:0] alert_cause; // [281:220] + alert_handler_hw2reg_intr_state_reg_t intr_state; // [297:290] + alert_handler_hw2reg_alert_cause_mreg_t [34:0] alert_cause; // [289:220] alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [219:212] alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] @@ -565,194 +565,214 @@ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 10'h 88; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 10'h 8c; parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 10'h 90; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h 94; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h 98; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h 9c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 100; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 104; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 108; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 10c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 110; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 114; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 118; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 11c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 120; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 124; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 128; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 12c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 130; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 134; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 138; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 13c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 140; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 144; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 148; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 14c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 150; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 154; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 158; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 15c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 160; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 164; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 168; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 16c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 170; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 174; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 178; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 17c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 180; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 184; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 188; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 18c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 190; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 194; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 198; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 19c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 1a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 1a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 1a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 1ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 1b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 1b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 1b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 1bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 1c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 1c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 1c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 1cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 1d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 1d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 1d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 1dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 1e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 1e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 1e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 1ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 1f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 1f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 1f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 1fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 200; - parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 204; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 208; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 20c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 210; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 214; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 218; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 10'h 21c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 10'h 220; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET = 10'h 224; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET = 10'h 228; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET = 10'h 22c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET = 10'h 230; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET = 10'h 234; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET = 10'h 238; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET = 10'h 23c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET = 10'h 240; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET = 10'h 244; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET = 10'h 248; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET = 10'h 24c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET = 10'h 250; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET = 10'h 254; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET = 10'h 258; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET = 10'h 25c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET = 10'h 260; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET = 10'h 264; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET = 10'h 268; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET = 10'h 26c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET = 10'h 270; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET = 10'h 274; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET = 10'h 278; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET = 10'h 27c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET = 10'h 280; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 284; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 288; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 28c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 290; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 294; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 298; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 29c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 2a0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 2a4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 2a8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 2ac; - parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 2b0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 2b4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 2b8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 2bc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 2c0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 2c4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 2c8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 2cc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 2d0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 2d4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 2d8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 2dc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 2e0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 2e4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 2e8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 2ec; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 2f0; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 2f4; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 2f8; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 2fc; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 300; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 304; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 308; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 30c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 310; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 314; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 318; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 31c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 320; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 324; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 328; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 32c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 330; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 334; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 338; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 33c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 340; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 344; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 348; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 34c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 350; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 354; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 358; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 35c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 360; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 364; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 368; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 36c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 370; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 374; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 378; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 37c; - parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 10'h 94; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 10'h 98; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 10'h 9c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 10'h a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 100; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 104; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 108; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 10c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 110; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 114; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 10'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 10'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET = 10'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET = 10'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET = 10'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET = 10'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET = 10'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET = 10'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET = 10'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET = 10'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET = 10'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET = 10'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET = 10'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET = 10'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET = 10'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET = 10'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET = 10'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET = 10'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET = 10'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET = 10'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET = 10'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET = 10'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET = 10'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET = 10'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET = 10'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET = 10'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_31_OFFSET = 10'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_32_OFFSET = 10'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_33_OFFSET = 10'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_34_OFFSET = 10'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3d0; // Reset values for hwext registers and their fields parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; @@ -812,6 +832,10 @@ ALERT_HANDLER_ALERT_REGWEN_28, ALERT_HANDLER_ALERT_REGWEN_29, ALERT_HANDLER_ALERT_REGWEN_30, + ALERT_HANDLER_ALERT_REGWEN_31, + ALERT_HANDLER_ALERT_REGWEN_32, + ALERT_HANDLER_ALERT_REGWEN_33, + ALERT_HANDLER_ALERT_REGWEN_34, ALERT_HANDLER_ALERT_EN_0, ALERT_HANDLER_ALERT_EN_1, ALERT_HANDLER_ALERT_EN_2, @@ -843,6 +867,10 @@ ALERT_HANDLER_ALERT_EN_28, ALERT_HANDLER_ALERT_EN_29, ALERT_HANDLER_ALERT_EN_30, + ALERT_HANDLER_ALERT_EN_31, + ALERT_HANDLER_ALERT_EN_32, + ALERT_HANDLER_ALERT_EN_33, + ALERT_HANDLER_ALERT_EN_34, ALERT_HANDLER_ALERT_CLASS_0, ALERT_HANDLER_ALERT_CLASS_1, ALERT_HANDLER_ALERT_CLASS_2, @@ -874,6 +902,10 @@ ALERT_HANDLER_ALERT_CLASS_28, ALERT_HANDLER_ALERT_CLASS_29, ALERT_HANDLER_ALERT_CLASS_30, + ALERT_HANDLER_ALERT_CLASS_31, + ALERT_HANDLER_ALERT_CLASS_32, + ALERT_HANDLER_ALERT_CLASS_33, + ALERT_HANDLER_ALERT_CLASS_34, ALERT_HANDLER_ALERT_CAUSE_0, ALERT_HANDLER_ALERT_CAUSE_1, ALERT_HANDLER_ALERT_CAUSE_2, @@ -905,6 +937,10 @@ ALERT_HANDLER_ALERT_CAUSE_28, ALERT_HANDLER_ALERT_CAUSE_29, ALERT_HANDLER_ALERT_CAUSE_30, + ALERT_HANDLER_ALERT_CAUSE_31, + ALERT_HANDLER_ALERT_CAUSE_32, + ALERT_HANDLER_ALERT_CAUSE_33, + ALERT_HANDLER_ALERT_CAUSE_34, ALERT_HANDLER_LOC_ALERT_REGWEN_0, ALERT_HANDLER_LOC_ALERT_REGWEN_1, ALERT_HANDLER_LOC_ALERT_REGWEN_2, @@ -936,6 +972,10 @@ ALERT_HANDLER_LOC_ALERT_REGWEN_28, ALERT_HANDLER_LOC_ALERT_REGWEN_29, ALERT_HANDLER_LOC_ALERT_REGWEN_30, + ALERT_HANDLER_LOC_ALERT_REGWEN_31, + ALERT_HANDLER_LOC_ALERT_REGWEN_32, + ALERT_HANDLER_LOC_ALERT_REGWEN_33, + ALERT_HANDLER_LOC_ALERT_REGWEN_34, ALERT_HANDLER_LOC_ALERT_EN_0, ALERT_HANDLER_LOC_ALERT_EN_1, ALERT_HANDLER_LOC_ALERT_EN_2, @@ -1003,7 +1043,7 @@ } alert_handler_id_e; // Register width information to check illegal writes - parameter logic [3:0] ALERT_HANDLER_PERMIT [225] = '{ + parameter logic [3:0] ALERT_HANDLER_PERMIT [245] = '{ 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST @@ -1041,194 +1081,214 @@ 4'b 0001, // index[ 34] ALERT_HANDLER_ALERT_REGWEN_28 4'b 0001, // index[ 35] ALERT_HANDLER_ALERT_REGWEN_29 4'b 0001, // index[ 36] ALERT_HANDLER_ALERT_REGWEN_30 - 4'b 0001, // index[ 37] ALERT_HANDLER_ALERT_EN_0 - 4'b 0001, // index[ 38] ALERT_HANDLER_ALERT_EN_1 - 4'b 0001, // index[ 39] ALERT_HANDLER_ALERT_EN_2 - 4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_EN_3 - 4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_EN_4 - 4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_EN_5 - 4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_EN_6 - 4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_EN_7 - 4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_EN_8 - 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_EN_9 - 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_EN_10 - 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_EN_11 - 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_12 - 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_13 - 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_14 - 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_15 - 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_16 - 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_17 - 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_18 - 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_19 - 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_20 - 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_21 - 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_22 - 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_23 - 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_24 - 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_25 - 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_26 - 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_27 - 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_28 - 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_29 - 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_30 - 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_CLASS_0 - 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_CLASS_1 - 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_CLASS_2 - 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_CLASS_3 - 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_CLASS_4 - 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_CLASS_5 - 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_CLASS_6 - 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_CLASS_7 - 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_CLASS_8 - 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_CLASS_9 - 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_CLASS_10 - 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_CLASS_11 - 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_CLASS_12 - 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_CLASS_13 - 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_CLASS_14 - 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_CLASS_15 - 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_CLASS_16 - 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_CLASS_17 - 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_CLASS_18 - 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_CLASS_19 - 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_CLASS_20 - 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_CLASS_21 - 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_CLASS_22 - 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_CLASS_23 - 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_24 - 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_25 - 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_26 - 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_27 - 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_28 - 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_29 - 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_30 - 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CAUSE_0 - 4'b 0001, // index[100] ALERT_HANDLER_ALERT_CAUSE_1 - 4'b 0001, // index[101] ALERT_HANDLER_ALERT_CAUSE_2 - 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CAUSE_3 - 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CAUSE_4 - 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CAUSE_5 - 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CAUSE_6 - 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CAUSE_7 - 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CAUSE_8 - 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CAUSE_9 - 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CAUSE_10 - 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CAUSE_11 - 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CAUSE_12 - 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CAUSE_13 - 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CAUSE_14 - 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CAUSE_15 - 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CAUSE_16 - 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CAUSE_17 - 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CAUSE_18 - 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CAUSE_19 - 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CAUSE_20 - 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CAUSE_21 - 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CAUSE_22 - 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CAUSE_23 - 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CAUSE_24 - 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CAUSE_25 - 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CAUSE_26 - 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CAUSE_27 - 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CAUSE_28 - 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CAUSE_29 - 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CAUSE_30 - 4'b 0001, // index[130] ALERT_HANDLER_LOC_ALERT_REGWEN_0 - 4'b 0001, // index[131] ALERT_HANDLER_LOC_ALERT_REGWEN_1 - 4'b 0001, // index[132] ALERT_HANDLER_LOC_ALERT_REGWEN_2 - 4'b 0001, // index[133] ALERT_HANDLER_LOC_ALERT_REGWEN_3 - 4'b 0001, // index[134] ALERT_HANDLER_LOC_ALERT_REGWEN_4 - 4'b 0001, // index[135] ALERT_HANDLER_LOC_ALERT_REGWEN_5 - 4'b 0001, // index[136] ALERT_HANDLER_LOC_ALERT_REGWEN_6 - 4'b 0001, // index[137] ALERT_HANDLER_LOC_ALERT_REGWEN_7 - 4'b 0001, // index[138] ALERT_HANDLER_LOC_ALERT_REGWEN_8 - 4'b 0001, // index[139] ALERT_HANDLER_LOC_ALERT_REGWEN_9 - 4'b 0001, // index[140] ALERT_HANDLER_LOC_ALERT_REGWEN_10 - 4'b 0001, // index[141] ALERT_HANDLER_LOC_ALERT_REGWEN_11 - 4'b 0001, // index[142] ALERT_HANDLER_LOC_ALERT_REGWEN_12 - 4'b 0001, // index[143] ALERT_HANDLER_LOC_ALERT_REGWEN_13 - 4'b 0001, // index[144] ALERT_HANDLER_LOC_ALERT_REGWEN_14 - 4'b 0001, // index[145] ALERT_HANDLER_LOC_ALERT_REGWEN_15 - 4'b 0001, // index[146] ALERT_HANDLER_LOC_ALERT_REGWEN_16 - 4'b 0001, // index[147] ALERT_HANDLER_LOC_ALERT_REGWEN_17 - 4'b 0001, // index[148] ALERT_HANDLER_LOC_ALERT_REGWEN_18 - 4'b 0001, // index[149] ALERT_HANDLER_LOC_ALERT_REGWEN_19 - 4'b 0001, // index[150] ALERT_HANDLER_LOC_ALERT_REGWEN_20 - 4'b 0001, // index[151] ALERT_HANDLER_LOC_ALERT_REGWEN_21 - 4'b 0001, // index[152] ALERT_HANDLER_LOC_ALERT_REGWEN_22 - 4'b 0001, // index[153] ALERT_HANDLER_LOC_ALERT_REGWEN_23 - 4'b 0001, // index[154] ALERT_HANDLER_LOC_ALERT_REGWEN_24 - 4'b 0001, // index[155] ALERT_HANDLER_LOC_ALERT_REGWEN_25 - 4'b 0001, // index[156] ALERT_HANDLER_LOC_ALERT_REGWEN_26 - 4'b 0001, // index[157] ALERT_HANDLER_LOC_ALERT_REGWEN_27 - 4'b 0001, // index[158] ALERT_HANDLER_LOC_ALERT_REGWEN_28 - 4'b 0001, // index[159] ALERT_HANDLER_LOC_ALERT_REGWEN_29 - 4'b 0001, // index[160] ALERT_HANDLER_LOC_ALERT_REGWEN_30 - 4'b 0001, // index[161] ALERT_HANDLER_LOC_ALERT_EN_0 - 4'b 0001, // index[162] ALERT_HANDLER_LOC_ALERT_EN_1 - 4'b 0001, // index[163] ALERT_HANDLER_LOC_ALERT_EN_2 - 4'b 0001, // index[164] ALERT_HANDLER_LOC_ALERT_EN_3 - 4'b 0001, // index[165] ALERT_HANDLER_LOC_ALERT_CLASS_0 - 4'b 0001, // index[166] ALERT_HANDLER_LOC_ALERT_CLASS_1 - 4'b 0001, // index[167] ALERT_HANDLER_LOC_ALERT_CLASS_2 - 4'b 0001, // index[168] ALERT_HANDLER_LOC_ALERT_CLASS_3 - 4'b 0001, // index[169] ALERT_HANDLER_LOC_ALERT_CAUSE_0 - 4'b 0001, // index[170] ALERT_HANDLER_LOC_ALERT_CAUSE_1 - 4'b 0001, // index[171] ALERT_HANDLER_LOC_ALERT_CAUSE_2 - 4'b 0001, // index[172] ALERT_HANDLER_LOC_ALERT_CAUSE_3 - 4'b 0001, // index[173] ALERT_HANDLER_CLASSA_REGWEN - 4'b 0011, // index[174] ALERT_HANDLER_CLASSA_CTRL - 4'b 0001, // index[175] ALERT_HANDLER_CLASSA_CLR_REGWEN - 4'b 0001, // index[176] ALERT_HANDLER_CLASSA_CLR - 4'b 0011, // index[177] ALERT_HANDLER_CLASSA_ACCUM_CNT - 4'b 0011, // index[178] ALERT_HANDLER_CLASSA_ACCUM_THRESH - 4'b 1111, // index[179] ALERT_HANDLER_CLASSA_TIMEOUT_CYC - 4'b 1111, // index[180] ALERT_HANDLER_CLASSA_PHASE0_CYC - 4'b 1111, // index[181] ALERT_HANDLER_CLASSA_PHASE1_CYC - 4'b 1111, // index[182] ALERT_HANDLER_CLASSA_PHASE2_CYC - 4'b 1111, // index[183] ALERT_HANDLER_CLASSA_PHASE3_CYC - 4'b 1111, // index[184] ALERT_HANDLER_CLASSA_ESC_CNT - 4'b 0001, // index[185] ALERT_HANDLER_CLASSA_STATE - 4'b 0001, // index[186] ALERT_HANDLER_CLASSB_REGWEN - 4'b 0011, // index[187] ALERT_HANDLER_CLASSB_CTRL - 4'b 0001, // index[188] ALERT_HANDLER_CLASSB_CLR_REGWEN - 4'b 0001, // index[189] ALERT_HANDLER_CLASSB_CLR - 4'b 0011, // index[190] ALERT_HANDLER_CLASSB_ACCUM_CNT - 4'b 0011, // index[191] ALERT_HANDLER_CLASSB_ACCUM_THRESH - 4'b 1111, // index[192] ALERT_HANDLER_CLASSB_TIMEOUT_CYC - 4'b 1111, // index[193] ALERT_HANDLER_CLASSB_PHASE0_CYC - 4'b 1111, // index[194] ALERT_HANDLER_CLASSB_PHASE1_CYC - 4'b 1111, // index[195] ALERT_HANDLER_CLASSB_PHASE2_CYC - 4'b 1111, // index[196] ALERT_HANDLER_CLASSB_PHASE3_CYC - 4'b 1111, // index[197] ALERT_HANDLER_CLASSB_ESC_CNT - 4'b 0001, // index[198] ALERT_HANDLER_CLASSB_STATE - 4'b 0001, // index[199] ALERT_HANDLER_CLASSC_REGWEN - 4'b 0011, // index[200] ALERT_HANDLER_CLASSC_CTRL - 4'b 0001, // index[201] ALERT_HANDLER_CLASSC_CLR_REGWEN - 4'b 0001, // index[202] ALERT_HANDLER_CLASSC_CLR - 4'b 0011, // index[203] ALERT_HANDLER_CLASSC_ACCUM_CNT - 4'b 0011, // index[204] ALERT_HANDLER_CLASSC_ACCUM_THRESH - 4'b 1111, // index[205] ALERT_HANDLER_CLASSC_TIMEOUT_CYC - 4'b 1111, // index[206] ALERT_HANDLER_CLASSC_PHASE0_CYC - 4'b 1111, // index[207] ALERT_HANDLER_CLASSC_PHASE1_CYC - 4'b 1111, // index[208] ALERT_HANDLER_CLASSC_PHASE2_CYC - 4'b 1111, // index[209] ALERT_HANDLER_CLASSC_PHASE3_CYC - 4'b 1111, // index[210] ALERT_HANDLER_CLASSC_ESC_CNT - 4'b 0001, // index[211] ALERT_HANDLER_CLASSC_STATE - 4'b 0001, // index[212] ALERT_HANDLER_CLASSD_REGWEN - 4'b 0011, // index[213] ALERT_HANDLER_CLASSD_CTRL - 4'b 0001, // index[214] ALERT_HANDLER_CLASSD_CLR_REGWEN - 4'b 0001, // index[215] ALERT_HANDLER_CLASSD_CLR - 4'b 0011, // index[216] ALERT_HANDLER_CLASSD_ACCUM_CNT - 4'b 0011, // index[217] ALERT_HANDLER_CLASSD_ACCUM_THRESH - 4'b 1111, // index[218] ALERT_HANDLER_CLASSD_TIMEOUT_CYC - 4'b 1111, // index[219] ALERT_HANDLER_CLASSD_PHASE0_CYC - 4'b 1111, // index[220] ALERT_HANDLER_CLASSD_PHASE1_CYC - 4'b 1111, // index[221] ALERT_HANDLER_CLASSD_PHASE2_CYC - 4'b 1111, // index[222] ALERT_HANDLER_CLASSD_PHASE3_CYC - 4'b 1111, // index[223] ALERT_HANDLER_CLASSD_ESC_CNT - 4'b 0001 // index[224] ALERT_HANDLER_CLASSD_STATE + 4'b 0001, // index[ 37] ALERT_HANDLER_ALERT_REGWEN_31 + 4'b 0001, // index[ 38] ALERT_HANDLER_ALERT_REGWEN_32 + 4'b 0001, // index[ 39] ALERT_HANDLER_ALERT_REGWEN_33 + 4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_REGWEN_34 + 4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_EN_0 + 4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_EN_1 + 4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_EN_2 + 4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_EN_3 + 4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_EN_4 + 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_EN_5 + 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_EN_6 + 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_EN_7 + 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_8 + 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_9 + 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_10 + 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_11 + 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_12 + 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_13 + 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_14 + 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_15 + 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_16 + 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_17 + 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_18 + 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_19 + 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_20 + 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_21 + 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_22 + 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_23 + 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_24 + 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_25 + 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_26 + 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_27 + 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_28 + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_29 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_30 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_31 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_32 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_33 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_34 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_CLASS_0 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_CLASS_1 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_CLASS_2 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_CLASS_3 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_CLASS_4 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_CLASS_5 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_CLASS_6 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_CLASS_7 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_CLASS_8 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_CLASS_9 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_CLASS_10 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_CLASS_11 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_CLASS_12 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_CLASS_13 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_CLASS_14 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_CLASS_15 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_16 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_17 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_18 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_19 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_20 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_21 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_22 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_23 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_24 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_25 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_26 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_27 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_28 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_29 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_30 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_31 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_32 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_33 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_34 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[146] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[147] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[148] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[149] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[150] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[151] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[152] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[153] ALERT_HANDLER_LOC_ALERT_REGWEN_7 + 4'b 0001, // index[154] ALERT_HANDLER_LOC_ALERT_REGWEN_8 + 4'b 0001, // index[155] ALERT_HANDLER_LOC_ALERT_REGWEN_9 + 4'b 0001, // index[156] ALERT_HANDLER_LOC_ALERT_REGWEN_10 + 4'b 0001, // index[157] ALERT_HANDLER_LOC_ALERT_REGWEN_11 + 4'b 0001, // index[158] ALERT_HANDLER_LOC_ALERT_REGWEN_12 + 4'b 0001, // index[159] ALERT_HANDLER_LOC_ALERT_REGWEN_13 + 4'b 0001, // index[160] ALERT_HANDLER_LOC_ALERT_REGWEN_14 + 4'b 0001, // index[161] ALERT_HANDLER_LOC_ALERT_REGWEN_15 + 4'b 0001, // index[162] ALERT_HANDLER_LOC_ALERT_REGWEN_16 + 4'b 0001, // index[163] ALERT_HANDLER_LOC_ALERT_REGWEN_17 + 4'b 0001, // index[164] ALERT_HANDLER_LOC_ALERT_REGWEN_18 + 4'b 0001, // index[165] ALERT_HANDLER_LOC_ALERT_REGWEN_19 + 4'b 0001, // index[166] ALERT_HANDLER_LOC_ALERT_REGWEN_20 + 4'b 0001, // index[167] ALERT_HANDLER_LOC_ALERT_REGWEN_21 + 4'b 0001, // index[168] ALERT_HANDLER_LOC_ALERT_REGWEN_22 + 4'b 0001, // index[169] ALERT_HANDLER_LOC_ALERT_REGWEN_23 + 4'b 0001, // index[170] ALERT_HANDLER_LOC_ALERT_REGWEN_24 + 4'b 0001, // index[171] ALERT_HANDLER_LOC_ALERT_REGWEN_25 + 4'b 0001, // index[172] ALERT_HANDLER_LOC_ALERT_REGWEN_26 + 4'b 0001, // index[173] ALERT_HANDLER_LOC_ALERT_REGWEN_27 + 4'b 0001, // index[174] ALERT_HANDLER_LOC_ALERT_REGWEN_28 + 4'b 0001, // index[175] ALERT_HANDLER_LOC_ALERT_REGWEN_29 + 4'b 0001, // index[176] ALERT_HANDLER_LOC_ALERT_REGWEN_30 + 4'b 0001, // index[177] ALERT_HANDLER_LOC_ALERT_REGWEN_31 + 4'b 0001, // index[178] ALERT_HANDLER_LOC_ALERT_REGWEN_32 + 4'b 0001, // index[179] ALERT_HANDLER_LOC_ALERT_REGWEN_33 + 4'b 0001, // index[180] ALERT_HANDLER_LOC_ALERT_REGWEN_34 + 4'b 0001, // index[181] ALERT_HANDLER_LOC_ALERT_EN_0 + 4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_EN_1 + 4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_EN_2 + 4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_EN_3 + 4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_CLASS_0 + 4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_CLASS_1 + 4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_CLASS_2 + 4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_CLASS_3 + 4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[190] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[191] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[192] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[193] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[194] ALERT_HANDLER_CLASSA_CTRL + 4'b 0001, // index[195] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[196] ALERT_HANDLER_CLASSA_CLR + 4'b 0011, // index[197] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[198] ALERT_HANDLER_CLASSA_ACCUM_THRESH + 4'b 1111, // index[199] ALERT_HANDLER_CLASSA_TIMEOUT_CYC + 4'b 1111, // index[200] ALERT_HANDLER_CLASSA_PHASE0_CYC + 4'b 1111, // index[201] ALERT_HANDLER_CLASSA_PHASE1_CYC + 4'b 1111, // index[202] ALERT_HANDLER_CLASSA_PHASE2_CYC + 4'b 1111, // index[203] ALERT_HANDLER_CLASSA_PHASE3_CYC + 4'b 1111, // index[204] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[205] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[206] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[207] ALERT_HANDLER_CLASSB_CTRL + 4'b 0001, // index[208] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[209] ALERT_HANDLER_CLASSB_CLR + 4'b 0011, // index[210] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[211] ALERT_HANDLER_CLASSB_ACCUM_THRESH + 4'b 1111, // index[212] ALERT_HANDLER_CLASSB_TIMEOUT_CYC + 4'b 1111, // index[213] ALERT_HANDLER_CLASSB_PHASE0_CYC + 4'b 1111, // index[214] ALERT_HANDLER_CLASSB_PHASE1_CYC + 4'b 1111, // index[215] ALERT_HANDLER_CLASSB_PHASE2_CYC + 4'b 1111, // index[216] ALERT_HANDLER_CLASSB_PHASE3_CYC + 4'b 1111, // index[217] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[218] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[219] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[220] ALERT_HANDLER_CLASSC_CTRL + 4'b 0001, // index[221] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[222] ALERT_HANDLER_CLASSC_CLR + 4'b 0011, // index[223] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[224] ALERT_HANDLER_CLASSC_ACCUM_THRESH + 4'b 1111, // index[225] ALERT_HANDLER_CLASSC_TIMEOUT_CYC + 4'b 1111, // index[226] ALERT_HANDLER_CLASSC_PHASE0_CYC + 4'b 1111, // index[227] ALERT_HANDLER_CLASSC_PHASE1_CYC + 4'b 1111, // index[228] ALERT_HANDLER_CLASSC_PHASE2_CYC + 4'b 1111, // index[229] ALERT_HANDLER_CLASSC_PHASE3_CYC + 4'b 1111, // index[230] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[231] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[232] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[233] ALERT_HANDLER_CLASSD_CTRL + 4'b 0001, // index[234] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[235] ALERT_HANDLER_CLASSD_CLR + 4'b 0011, // index[236] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[237] ALERT_HANDLER_CLASSD_ACCUM_THRESH + 4'b 1111, // index[238] ALERT_HANDLER_CLASSD_TIMEOUT_CYC + 4'b 1111, // index[239] ALERT_HANDLER_CLASSD_PHASE0_CYC + 4'b 1111, // index[240] ALERT_HANDLER_CLASSD_PHASE1_CYC + 4'b 1111, // index[241] ALERT_HANDLER_CLASSD_PHASE2_CYC + 4'b 1111, // index[242] ALERT_HANDLER_CLASSD_PHASE3_CYC + 4'b 1111, // index[243] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[244] ALERT_HANDLER_CLASSD_STATE }; endpackage
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv index 05e40d0..6a3e544 100644 --- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv +++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -238,6 +238,18 @@ logic alert_regwen_30_qs; logic alert_regwen_30_wd; logic alert_regwen_30_we; + logic alert_regwen_31_qs; + logic alert_regwen_31_wd; + logic alert_regwen_31_we; + logic alert_regwen_32_qs; + logic alert_regwen_32_wd; + logic alert_regwen_32_we; + logic alert_regwen_33_qs; + logic alert_regwen_33_wd; + logic alert_regwen_33_we; + logic alert_regwen_34_qs; + logic alert_regwen_34_wd; + logic alert_regwen_34_we; logic alert_en_0_qs; logic alert_en_0_wd; logic alert_en_0_we; @@ -331,6 +343,18 @@ logic alert_en_30_qs; logic alert_en_30_wd; logic alert_en_30_we; + logic alert_en_31_qs; + logic alert_en_31_wd; + logic alert_en_31_we; + logic alert_en_32_qs; + logic alert_en_32_wd; + logic alert_en_32_we; + logic alert_en_33_qs; + logic alert_en_33_wd; + logic alert_en_33_we; + logic alert_en_34_qs; + logic alert_en_34_wd; + logic alert_en_34_we; logic [1:0] alert_class_0_qs; logic [1:0] alert_class_0_wd; logic alert_class_0_we; @@ -424,6 +448,18 @@ logic [1:0] alert_class_30_qs; logic [1:0] alert_class_30_wd; logic alert_class_30_we; + logic [1:0] alert_class_31_qs; + logic [1:0] alert_class_31_wd; + logic alert_class_31_we; + logic [1:0] alert_class_32_qs; + logic [1:0] alert_class_32_wd; + logic alert_class_32_we; + logic [1:0] alert_class_33_qs; + logic [1:0] alert_class_33_wd; + logic alert_class_33_we; + logic [1:0] alert_class_34_qs; + logic [1:0] alert_class_34_wd; + logic alert_class_34_we; logic alert_cause_0_qs; logic alert_cause_0_wd; logic alert_cause_0_we; @@ -517,6 +553,18 @@ logic alert_cause_30_qs; logic alert_cause_30_wd; logic alert_cause_30_we; + logic alert_cause_31_qs; + logic alert_cause_31_wd; + logic alert_cause_31_we; + logic alert_cause_32_qs; + logic alert_cause_32_wd; + logic alert_cause_32_we; + logic alert_cause_33_qs; + logic alert_cause_33_wd; + logic alert_cause_33_we; + logic alert_cause_34_qs; + logic alert_cause_34_wd; + logic alert_cause_34_we; logic loc_alert_regwen_0_qs; logic loc_alert_regwen_0_wd; logic loc_alert_regwen_0_we; @@ -610,6 +658,18 @@ logic loc_alert_regwen_30_qs; logic loc_alert_regwen_30_wd; logic loc_alert_regwen_30_we; + logic loc_alert_regwen_31_qs; + logic loc_alert_regwen_31_wd; + logic loc_alert_regwen_31_we; + logic loc_alert_regwen_32_qs; + logic loc_alert_regwen_32_wd; + logic loc_alert_regwen_32_we; + logic loc_alert_regwen_33_qs; + logic loc_alert_regwen_33_wd; + logic loc_alert_regwen_33_we; + logic loc_alert_regwen_34_qs; + logic loc_alert_regwen_34_wd; + logic loc_alert_regwen_34_we; logic loc_alert_en_0_qs; logic loc_alert_en_0_wd; logic loc_alert_en_0_we; @@ -2089,6 +2149,114 @@ .qs (alert_regwen_30_qs) ); + // Subregister 31 of Multireg alert_regwen + // R[alert_regwen_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_alert_regwen_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_regwen_31_we), + .wd (alert_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[31].q ), + + // to register interface (read) + .qs (alert_regwen_31_qs) + ); + + // Subregister 32 of Multireg alert_regwen + // R[alert_regwen_32]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_alert_regwen_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_regwen_32_we), + .wd (alert_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[32].q ), + + // to register interface (read) + .qs (alert_regwen_32_qs) + ); + + // Subregister 33 of Multireg alert_regwen + // R[alert_regwen_33]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_alert_regwen_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_regwen_33_we), + .wd (alert_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[33].q ), + + // to register interface (read) + .qs (alert_regwen_33_qs) + ); + + // Subregister 34 of Multireg alert_regwen + // R[alert_regwen_34]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_alert_regwen_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_regwen_34_we), + .wd (alert_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[34].q ), + + // to register interface (read) + .qs (alert_regwen_34_qs) + ); + // Subregister 0 of Multireg alert_en @@ -2928,6 +3096,114 @@ .qs (alert_en_30_qs) ); + // Subregister 31 of Multireg alert_en + // R[alert_en_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_en_31_we & alert_regwen_31_qs), + .wd (alert_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[31].q ), + + // to register interface (read) + .qs (alert_en_31_qs) + ); + + // Subregister 32 of Multireg alert_en + // R[alert_en_32]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_en_32_we & alert_regwen_32_qs), + .wd (alert_en_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[32].q ), + + // to register interface (read) + .qs (alert_en_32_qs) + ); + + // Subregister 33 of Multireg alert_en + // R[alert_en_33]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_en_33_we & alert_regwen_33_qs), + .wd (alert_en_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[33].q ), + + // to register interface (read) + .qs (alert_en_33_qs) + ); + + // Subregister 34 of Multireg alert_en + // R[alert_en_34]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_en_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_en_34_we & alert_regwen_34_qs), + .wd (alert_en_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en[34].q ), + + // to register interface (read) + .qs (alert_en_34_qs) + ); + // Subregister 0 of Multireg alert_class @@ -3767,6 +4043,114 @@ .qs (alert_class_30_qs) ); + // Subregister 31 of Multireg alert_class + // R[alert_class_31]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_class_31_we & alert_regwen_31_qs), + .wd (alert_class_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[31].q ), + + // to register interface (read) + .qs (alert_class_31_qs) + ); + + // Subregister 32 of Multireg alert_class + // R[alert_class_32]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_class_32_we & alert_regwen_32_qs), + .wd (alert_class_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[32].q ), + + // to register interface (read) + .qs (alert_class_32_qs) + ); + + // Subregister 33 of Multireg alert_class + // R[alert_class_33]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_class_33_we & alert_regwen_33_qs), + .wd (alert_class_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[33].q ), + + // to register interface (read) + .qs (alert_class_33_qs) + ); + + // Subregister 34 of Multireg alert_class + // R[alert_class_34]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_alert_class_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (alert_class_34_we & alert_regwen_34_qs), + .wd (alert_class_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class[34].q ), + + // to register interface (read) + .qs (alert_class_34_qs) + ); + // Subregister 0 of Multireg alert_cause @@ -4606,6 +4990,114 @@ .qs (alert_cause_30_qs) ); + // Subregister 31 of Multireg alert_cause + // R[alert_cause_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_cause_31_we), + .wd (alert_cause_31_wd), + + // from internal hardware + .de (hw2reg.alert_cause[31].de), + .d (hw2reg.alert_cause[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[31].q ), + + // to register interface (read) + .qs (alert_cause_31_qs) + ); + + // Subregister 32 of Multireg alert_cause + // R[alert_cause_32]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_cause_32_we), + .wd (alert_cause_32_wd), + + // from internal hardware + .de (hw2reg.alert_cause[32].de), + .d (hw2reg.alert_cause[32].d ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[32].q ), + + // to register interface (read) + .qs (alert_cause_32_qs) + ); + + // Subregister 33 of Multireg alert_cause + // R[alert_cause_33]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_cause_33_we), + .wd (alert_cause_33_wd), + + // from internal hardware + .de (hw2reg.alert_cause[33].de), + .d (hw2reg.alert_cause[33].d ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[33].q ), + + // to register interface (read) + .qs (alert_cause_33_qs) + ); + + // Subregister 34 of Multireg alert_cause + // R[alert_cause_34]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_cause_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_cause_34_we), + .wd (alert_cause_34_wd), + + // from internal hardware + .de (hw2reg.alert_cause[34].de), + .d (hw2reg.alert_cause[34].d ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[34].q ), + + // to register interface (read) + .qs (alert_cause_34_qs) + ); + // Subregister 0 of Multireg loc_alert_regwen @@ -5445,6 +5937,114 @@ .qs (loc_alert_regwen_30_qs) ); + // Subregister 31 of Multireg loc_alert_regwen + // R[loc_alert_regwen_31]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_loc_alert_regwen_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (loc_alert_regwen_31_we), + .wd (loc_alert_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (loc_alert_regwen_31_qs) + ); + + // Subregister 32 of Multireg loc_alert_regwen + // R[loc_alert_regwen_32]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_loc_alert_regwen_32 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (loc_alert_regwen_32_we), + .wd (loc_alert_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (loc_alert_regwen_32_qs) + ); + + // Subregister 33 of Multireg loc_alert_regwen + // R[loc_alert_regwen_33]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_loc_alert_regwen_33 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (loc_alert_regwen_33_we), + .wd (loc_alert_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (loc_alert_regwen_33_qs) + ); + + // Subregister 34 of Multireg loc_alert_regwen + // R[loc_alert_regwen_34]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("W0C"), + .RESVAL (1'h1) + ) u_loc_alert_regwen_34 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (loc_alert_regwen_34_we), + .wd (loc_alert_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (loc_alert_regwen_34_qs) + ); + // Subregister 0 of Multireg loc_alert_en @@ -7986,7 +8586,7 @@ - logic [224:0] addr_hit; + logic [244:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); @@ -8026,194 +8626,214 @@ addr_hit[ 34] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_28_OFFSET); addr_hit[ 35] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_29_OFFSET); addr_hit[ 36] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_30_OFFSET); - addr_hit[ 37] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET); - addr_hit[ 38] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET); - addr_hit[ 39] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET); - addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET); - addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET); - addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET); - addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET); - addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET); - addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET); - addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET); - addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET); - addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET); - addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET); - addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET); - addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET); - addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET); - addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET); - addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET); - addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET); - addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET); - addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET); - addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET); - addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET); - addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET); - addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET); - addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET); - addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET); - addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET); - addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET); - addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET); - addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET); - addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET); - addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET); - addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET); - addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET); - addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET); - addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET); - addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET); - addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET); - addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET); - addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET); - addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET); - addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET); - addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET); - addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET); - addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET); - addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET); - addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET); - addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET); - addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET); - addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET); - addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET); - addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET); - addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET); - addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET); - addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET); - addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET); - addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET); - addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET); - addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET); - addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET); - addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET); - addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); - addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); - addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); - addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); - addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); - addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); - addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); - addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); - addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); - addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); - addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); - addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); - addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); - addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); - addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); - addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); - addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); - addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); - addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); - addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); - addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); - addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); - addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); - addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); - addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); - addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); - addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); - addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); - addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); - addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); - addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); - addr_hit[130] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); - addr_hit[131] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); - addr_hit[132] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); - addr_hit[133] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); - addr_hit[134] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); - addr_hit[135] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); - addr_hit[136] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); - addr_hit[137] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET); - addr_hit[138] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET); - addr_hit[139] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET); - addr_hit[140] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET); - addr_hit[141] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET); - addr_hit[142] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET); - addr_hit[143] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET); - addr_hit[144] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET); - addr_hit[145] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET); - addr_hit[146] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET); - addr_hit[147] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET); - addr_hit[148] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET); - addr_hit[149] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET); - addr_hit[150] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET); - addr_hit[151] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET); - addr_hit[152] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET); - addr_hit[153] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET); - addr_hit[154] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET); - addr_hit[155] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET); - addr_hit[156] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET); - addr_hit[157] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET); - addr_hit[158] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET); - addr_hit[159] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET); - addr_hit[160] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET); - addr_hit[161] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET); - addr_hit[162] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET); - addr_hit[163] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET); - addr_hit[164] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET); - addr_hit[165] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET); - addr_hit[166] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET); - addr_hit[167] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET); - addr_hit[168] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET); - addr_hit[169] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); - addr_hit[170] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); - addr_hit[171] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); - addr_hit[172] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); - addr_hit[173] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); - addr_hit[174] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET); - addr_hit[175] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); - addr_hit[176] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET); - addr_hit[177] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); - addr_hit[178] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET); - addr_hit[179] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET); - addr_hit[180] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET); - addr_hit[181] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET); - addr_hit[182] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET); - addr_hit[183] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET); - addr_hit[184] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); - addr_hit[185] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); - addr_hit[186] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); - addr_hit[187] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET); - addr_hit[188] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); - addr_hit[189] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET); - addr_hit[190] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); - addr_hit[191] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET); - addr_hit[192] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET); - addr_hit[193] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET); - addr_hit[194] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET); - addr_hit[195] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET); - addr_hit[196] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET); - addr_hit[197] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); - addr_hit[198] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); - addr_hit[199] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); - addr_hit[200] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET); - addr_hit[201] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); - addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET); - addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); - addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET); - addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET); - addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET); - addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET); - addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET); - addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET); - addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); - addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); - addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); - addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET); - addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); - addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET); - addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); - addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET); - addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET); - addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET); - addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET); - addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET); - addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET); - addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); - addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + addr_hit[ 37] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_31_OFFSET); + addr_hit[ 38] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_32_OFFSET); + addr_hit[ 39] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_33_OFFSET); + addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_34_OFFSET); + addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET); + addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET); + addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET); + addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET); + addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET); + addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET); + addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET); + addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET); + addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET); + addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET); + addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET); + addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET); + addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET); + addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET); + addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET); + addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET); + addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET); + addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET); + addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET); + addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET); + addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET); + addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET); + addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET); + addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET); + addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET); + addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET); + addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET); + addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET); + addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET); + addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_7_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_8_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_9_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_10_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_11_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_12_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_13_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_14_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_15_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_16_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_17_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_18_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_19_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_20_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_21_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_22_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_23_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_24_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_25_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_26_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_27_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_28_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_29_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_30_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_31_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_32_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_33_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_34_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -8445,7 +9065,27 @@ (addr_hit[221] & (|(ALERT_HANDLER_PERMIT[221] & ~reg_be))) | (addr_hit[222] & (|(ALERT_HANDLER_PERMIT[222] & ~reg_be))) | (addr_hit[223] & (|(ALERT_HANDLER_PERMIT[223] & ~reg_be))) | - (addr_hit[224] & (|(ALERT_HANDLER_PERMIT[224] & ~reg_be))))); + (addr_hit[224] & (|(ALERT_HANDLER_PERMIT[224] & ~reg_be))) | + (addr_hit[225] & (|(ALERT_HANDLER_PERMIT[225] & ~reg_be))) | + (addr_hit[226] & (|(ALERT_HANDLER_PERMIT[226] & ~reg_be))) | + (addr_hit[227] & (|(ALERT_HANDLER_PERMIT[227] & ~reg_be))) | + (addr_hit[228] & (|(ALERT_HANDLER_PERMIT[228] & ~reg_be))) | + (addr_hit[229] & (|(ALERT_HANDLER_PERMIT[229] & ~reg_be))) | + (addr_hit[230] & (|(ALERT_HANDLER_PERMIT[230] & ~reg_be))) | + (addr_hit[231] & (|(ALERT_HANDLER_PERMIT[231] & ~reg_be))) | + (addr_hit[232] & (|(ALERT_HANDLER_PERMIT[232] & ~reg_be))) | + (addr_hit[233] & (|(ALERT_HANDLER_PERMIT[233] & ~reg_be))) | + (addr_hit[234] & (|(ALERT_HANDLER_PERMIT[234] & ~reg_be))) | + (addr_hit[235] & (|(ALERT_HANDLER_PERMIT[235] & ~reg_be))) | + (addr_hit[236] & (|(ALERT_HANDLER_PERMIT[236] & ~reg_be))) | + (addr_hit[237] & (|(ALERT_HANDLER_PERMIT[237] & ~reg_be))) | + (addr_hit[238] & (|(ALERT_HANDLER_PERMIT[238] & ~reg_be))) | + (addr_hit[239] & (|(ALERT_HANDLER_PERMIT[239] & ~reg_be))) | + (addr_hit[240] & (|(ALERT_HANDLER_PERMIT[240] & ~reg_be))) | + (addr_hit[241] & (|(ALERT_HANDLER_PERMIT[241] & ~reg_be))) | + (addr_hit[242] & (|(ALERT_HANDLER_PERMIT[242] & ~reg_be))) | + (addr_hit[243] & (|(ALERT_HANDLER_PERMIT[243] & ~reg_be))) | + (addr_hit[244] & (|(ALERT_HANDLER_PERMIT[244] & ~reg_be))))); end assign intr_state_classa_we = addr_hit[0] & reg_we & !reg_error; @@ -8586,665 +9226,725 @@ assign alert_regwen_30_we = addr_hit[36] & reg_we & !reg_error; assign alert_regwen_30_wd = reg_wdata[0]; - assign alert_en_0_we = addr_hit[37] & reg_we & !reg_error; + assign alert_regwen_31_we = addr_hit[37] & reg_we & !reg_error; + assign alert_regwen_31_wd = reg_wdata[0]; + + assign alert_regwen_32_we = addr_hit[38] & reg_we & !reg_error; + assign alert_regwen_32_wd = reg_wdata[0]; + + assign alert_regwen_33_we = addr_hit[39] & reg_we & !reg_error; + assign alert_regwen_33_wd = reg_wdata[0]; + + assign alert_regwen_34_we = addr_hit[40] & reg_we & !reg_error; + assign alert_regwen_34_wd = reg_wdata[0]; + + assign alert_en_0_we = addr_hit[41] & reg_we & !reg_error; assign alert_en_0_wd = reg_wdata[0]; - assign alert_en_1_we = addr_hit[38] & reg_we & !reg_error; + assign alert_en_1_we = addr_hit[42] & reg_we & !reg_error; assign alert_en_1_wd = reg_wdata[0]; - assign alert_en_2_we = addr_hit[39] & reg_we & !reg_error; + assign alert_en_2_we = addr_hit[43] & reg_we & !reg_error; assign alert_en_2_wd = reg_wdata[0]; - assign alert_en_3_we = addr_hit[40] & reg_we & !reg_error; + assign alert_en_3_we = addr_hit[44] & reg_we & !reg_error; assign alert_en_3_wd = reg_wdata[0]; - assign alert_en_4_we = addr_hit[41] & reg_we & !reg_error; + assign alert_en_4_we = addr_hit[45] & reg_we & !reg_error; assign alert_en_4_wd = reg_wdata[0]; - assign alert_en_5_we = addr_hit[42] & reg_we & !reg_error; + assign alert_en_5_we = addr_hit[46] & reg_we & !reg_error; assign alert_en_5_wd = reg_wdata[0]; - assign alert_en_6_we = addr_hit[43] & reg_we & !reg_error; + assign alert_en_6_we = addr_hit[47] & reg_we & !reg_error; assign alert_en_6_wd = reg_wdata[0]; - assign alert_en_7_we = addr_hit[44] & reg_we & !reg_error; + assign alert_en_7_we = addr_hit[48] & reg_we & !reg_error; assign alert_en_7_wd = reg_wdata[0]; - assign alert_en_8_we = addr_hit[45] & reg_we & !reg_error; + assign alert_en_8_we = addr_hit[49] & reg_we & !reg_error; assign alert_en_8_wd = reg_wdata[0]; - assign alert_en_9_we = addr_hit[46] & reg_we & !reg_error; + assign alert_en_9_we = addr_hit[50] & reg_we & !reg_error; assign alert_en_9_wd = reg_wdata[0]; - assign alert_en_10_we = addr_hit[47] & reg_we & !reg_error; + assign alert_en_10_we = addr_hit[51] & reg_we & !reg_error; assign alert_en_10_wd = reg_wdata[0]; - assign alert_en_11_we = addr_hit[48] & reg_we & !reg_error; + assign alert_en_11_we = addr_hit[52] & reg_we & !reg_error; assign alert_en_11_wd = reg_wdata[0]; - assign alert_en_12_we = addr_hit[49] & reg_we & !reg_error; + assign alert_en_12_we = addr_hit[53] & reg_we & !reg_error; assign alert_en_12_wd = reg_wdata[0]; - assign alert_en_13_we = addr_hit[50] & reg_we & !reg_error; + assign alert_en_13_we = addr_hit[54] & reg_we & !reg_error; assign alert_en_13_wd = reg_wdata[0]; - assign alert_en_14_we = addr_hit[51] & reg_we & !reg_error; + assign alert_en_14_we = addr_hit[55] & reg_we & !reg_error; assign alert_en_14_wd = reg_wdata[0]; - assign alert_en_15_we = addr_hit[52] & reg_we & !reg_error; + assign alert_en_15_we = addr_hit[56] & reg_we & !reg_error; assign alert_en_15_wd = reg_wdata[0]; - assign alert_en_16_we = addr_hit[53] & reg_we & !reg_error; + assign alert_en_16_we = addr_hit[57] & reg_we & !reg_error; assign alert_en_16_wd = reg_wdata[0]; - assign alert_en_17_we = addr_hit[54] & reg_we & !reg_error; + assign alert_en_17_we = addr_hit[58] & reg_we & !reg_error; assign alert_en_17_wd = reg_wdata[0]; - assign alert_en_18_we = addr_hit[55] & reg_we & !reg_error; + assign alert_en_18_we = addr_hit[59] & reg_we & !reg_error; assign alert_en_18_wd = reg_wdata[0]; - assign alert_en_19_we = addr_hit[56] & reg_we & !reg_error; + assign alert_en_19_we = addr_hit[60] & reg_we & !reg_error; assign alert_en_19_wd = reg_wdata[0]; - assign alert_en_20_we = addr_hit[57] & reg_we & !reg_error; + assign alert_en_20_we = addr_hit[61] & reg_we & !reg_error; assign alert_en_20_wd = reg_wdata[0]; - assign alert_en_21_we = addr_hit[58] & reg_we & !reg_error; + assign alert_en_21_we = addr_hit[62] & reg_we & !reg_error; assign alert_en_21_wd = reg_wdata[0]; - assign alert_en_22_we = addr_hit[59] & reg_we & !reg_error; + assign alert_en_22_we = addr_hit[63] & reg_we & !reg_error; assign alert_en_22_wd = reg_wdata[0]; - assign alert_en_23_we = addr_hit[60] & reg_we & !reg_error; + assign alert_en_23_we = addr_hit[64] & reg_we & !reg_error; assign alert_en_23_wd = reg_wdata[0]; - assign alert_en_24_we = addr_hit[61] & reg_we & !reg_error; + assign alert_en_24_we = addr_hit[65] & reg_we & !reg_error; assign alert_en_24_wd = reg_wdata[0]; - assign alert_en_25_we = addr_hit[62] & reg_we & !reg_error; + assign alert_en_25_we = addr_hit[66] & reg_we & !reg_error; assign alert_en_25_wd = reg_wdata[0]; - assign alert_en_26_we = addr_hit[63] & reg_we & !reg_error; + assign alert_en_26_we = addr_hit[67] & reg_we & !reg_error; assign alert_en_26_wd = reg_wdata[0]; - assign alert_en_27_we = addr_hit[64] & reg_we & !reg_error; + assign alert_en_27_we = addr_hit[68] & reg_we & !reg_error; assign alert_en_27_wd = reg_wdata[0]; - assign alert_en_28_we = addr_hit[65] & reg_we & !reg_error; + assign alert_en_28_we = addr_hit[69] & reg_we & !reg_error; assign alert_en_28_wd = reg_wdata[0]; - assign alert_en_29_we = addr_hit[66] & reg_we & !reg_error; + assign alert_en_29_we = addr_hit[70] & reg_we & !reg_error; assign alert_en_29_wd = reg_wdata[0]; - assign alert_en_30_we = addr_hit[67] & reg_we & !reg_error; + assign alert_en_30_we = addr_hit[71] & reg_we & !reg_error; assign alert_en_30_wd = reg_wdata[0]; - assign alert_class_0_we = addr_hit[68] & reg_we & !reg_error; + assign alert_en_31_we = addr_hit[72] & reg_we & !reg_error; + assign alert_en_31_wd = reg_wdata[0]; + + assign alert_en_32_we = addr_hit[73] & reg_we & !reg_error; + assign alert_en_32_wd = reg_wdata[0]; + + assign alert_en_33_we = addr_hit[74] & reg_we & !reg_error; + assign alert_en_33_wd = reg_wdata[0]; + + assign alert_en_34_we = addr_hit[75] & reg_we & !reg_error; + assign alert_en_34_wd = reg_wdata[0]; + + assign alert_class_0_we = addr_hit[76] & reg_we & !reg_error; assign alert_class_0_wd = reg_wdata[1:0]; - assign alert_class_1_we = addr_hit[69] & reg_we & !reg_error; + assign alert_class_1_we = addr_hit[77] & reg_we & !reg_error; assign alert_class_1_wd = reg_wdata[1:0]; - assign alert_class_2_we = addr_hit[70] & reg_we & !reg_error; + assign alert_class_2_we = addr_hit[78] & reg_we & !reg_error; assign alert_class_2_wd = reg_wdata[1:0]; - assign alert_class_3_we = addr_hit[71] & reg_we & !reg_error; + assign alert_class_3_we = addr_hit[79] & reg_we & !reg_error; assign alert_class_3_wd = reg_wdata[1:0]; - assign alert_class_4_we = addr_hit[72] & reg_we & !reg_error; + assign alert_class_4_we = addr_hit[80] & reg_we & !reg_error; assign alert_class_4_wd = reg_wdata[1:0]; - assign alert_class_5_we = addr_hit[73] & reg_we & !reg_error; + assign alert_class_5_we = addr_hit[81] & reg_we & !reg_error; assign alert_class_5_wd = reg_wdata[1:0]; - assign alert_class_6_we = addr_hit[74] & reg_we & !reg_error; + assign alert_class_6_we = addr_hit[82] & reg_we & !reg_error; assign alert_class_6_wd = reg_wdata[1:0]; - assign alert_class_7_we = addr_hit[75] & reg_we & !reg_error; + assign alert_class_7_we = addr_hit[83] & reg_we & !reg_error; assign alert_class_7_wd = reg_wdata[1:0]; - assign alert_class_8_we = addr_hit[76] & reg_we & !reg_error; + assign alert_class_8_we = addr_hit[84] & reg_we & !reg_error; assign alert_class_8_wd = reg_wdata[1:0]; - assign alert_class_9_we = addr_hit[77] & reg_we & !reg_error; + assign alert_class_9_we = addr_hit[85] & reg_we & !reg_error; assign alert_class_9_wd = reg_wdata[1:0]; - assign alert_class_10_we = addr_hit[78] & reg_we & !reg_error; + assign alert_class_10_we = addr_hit[86] & reg_we & !reg_error; assign alert_class_10_wd = reg_wdata[1:0]; - assign alert_class_11_we = addr_hit[79] & reg_we & !reg_error; + assign alert_class_11_we = addr_hit[87] & reg_we & !reg_error; assign alert_class_11_wd = reg_wdata[1:0]; - assign alert_class_12_we = addr_hit[80] & reg_we & !reg_error; + assign alert_class_12_we = addr_hit[88] & reg_we & !reg_error; assign alert_class_12_wd = reg_wdata[1:0]; - assign alert_class_13_we = addr_hit[81] & reg_we & !reg_error; + assign alert_class_13_we = addr_hit[89] & reg_we & !reg_error; assign alert_class_13_wd = reg_wdata[1:0]; - assign alert_class_14_we = addr_hit[82] & reg_we & !reg_error; + assign alert_class_14_we = addr_hit[90] & reg_we & !reg_error; assign alert_class_14_wd = reg_wdata[1:0]; - assign alert_class_15_we = addr_hit[83] & reg_we & !reg_error; + assign alert_class_15_we = addr_hit[91] & reg_we & !reg_error; assign alert_class_15_wd = reg_wdata[1:0]; - assign alert_class_16_we = addr_hit[84] & reg_we & !reg_error; + assign alert_class_16_we = addr_hit[92] & reg_we & !reg_error; assign alert_class_16_wd = reg_wdata[1:0]; - assign alert_class_17_we = addr_hit[85] & reg_we & !reg_error; + assign alert_class_17_we = addr_hit[93] & reg_we & !reg_error; assign alert_class_17_wd = reg_wdata[1:0]; - assign alert_class_18_we = addr_hit[86] & reg_we & !reg_error; + assign alert_class_18_we = addr_hit[94] & reg_we & !reg_error; assign alert_class_18_wd = reg_wdata[1:0]; - assign alert_class_19_we = addr_hit[87] & reg_we & !reg_error; + assign alert_class_19_we = addr_hit[95] & reg_we & !reg_error; assign alert_class_19_wd = reg_wdata[1:0]; - assign alert_class_20_we = addr_hit[88] & reg_we & !reg_error; + assign alert_class_20_we = addr_hit[96] & reg_we & !reg_error; assign alert_class_20_wd = reg_wdata[1:0]; - assign alert_class_21_we = addr_hit[89] & reg_we & !reg_error; + assign alert_class_21_we = addr_hit[97] & reg_we & !reg_error; assign alert_class_21_wd = reg_wdata[1:0]; - assign alert_class_22_we = addr_hit[90] & reg_we & !reg_error; + assign alert_class_22_we = addr_hit[98] & reg_we & !reg_error; assign alert_class_22_wd = reg_wdata[1:0]; - assign alert_class_23_we = addr_hit[91] & reg_we & !reg_error; + assign alert_class_23_we = addr_hit[99] & reg_we & !reg_error; assign alert_class_23_wd = reg_wdata[1:0]; - assign alert_class_24_we = addr_hit[92] & reg_we & !reg_error; + assign alert_class_24_we = addr_hit[100] & reg_we & !reg_error; assign alert_class_24_wd = reg_wdata[1:0]; - assign alert_class_25_we = addr_hit[93] & reg_we & !reg_error; + assign alert_class_25_we = addr_hit[101] & reg_we & !reg_error; assign alert_class_25_wd = reg_wdata[1:0]; - assign alert_class_26_we = addr_hit[94] & reg_we & !reg_error; + assign alert_class_26_we = addr_hit[102] & reg_we & !reg_error; assign alert_class_26_wd = reg_wdata[1:0]; - assign alert_class_27_we = addr_hit[95] & reg_we & !reg_error; + assign alert_class_27_we = addr_hit[103] & reg_we & !reg_error; assign alert_class_27_wd = reg_wdata[1:0]; - assign alert_class_28_we = addr_hit[96] & reg_we & !reg_error; + assign alert_class_28_we = addr_hit[104] & reg_we & !reg_error; assign alert_class_28_wd = reg_wdata[1:0]; - assign alert_class_29_we = addr_hit[97] & reg_we & !reg_error; + assign alert_class_29_we = addr_hit[105] & reg_we & !reg_error; assign alert_class_29_wd = reg_wdata[1:0]; - assign alert_class_30_we = addr_hit[98] & reg_we & !reg_error; + assign alert_class_30_we = addr_hit[106] & reg_we & !reg_error; assign alert_class_30_wd = reg_wdata[1:0]; - assign alert_cause_0_we = addr_hit[99] & reg_we & !reg_error; + assign alert_class_31_we = addr_hit[107] & reg_we & !reg_error; + assign alert_class_31_wd = reg_wdata[1:0]; + + assign alert_class_32_we = addr_hit[108] & reg_we & !reg_error; + assign alert_class_32_wd = reg_wdata[1:0]; + + assign alert_class_33_we = addr_hit[109] & reg_we & !reg_error; + assign alert_class_33_wd = reg_wdata[1:0]; + + assign alert_class_34_we = addr_hit[110] & reg_we & !reg_error; + assign alert_class_34_wd = reg_wdata[1:0]; + + assign alert_cause_0_we = addr_hit[111] & reg_we & !reg_error; assign alert_cause_0_wd = reg_wdata[0]; - assign alert_cause_1_we = addr_hit[100] & reg_we & !reg_error; + assign alert_cause_1_we = addr_hit[112] & reg_we & !reg_error; assign alert_cause_1_wd = reg_wdata[0]; - assign alert_cause_2_we = addr_hit[101] & reg_we & !reg_error; + assign alert_cause_2_we = addr_hit[113] & reg_we & !reg_error; assign alert_cause_2_wd = reg_wdata[0]; - assign alert_cause_3_we = addr_hit[102] & reg_we & !reg_error; + assign alert_cause_3_we = addr_hit[114] & reg_we & !reg_error; assign alert_cause_3_wd = reg_wdata[0]; - assign alert_cause_4_we = addr_hit[103] & reg_we & !reg_error; + assign alert_cause_4_we = addr_hit[115] & reg_we & !reg_error; assign alert_cause_4_wd = reg_wdata[0]; - assign alert_cause_5_we = addr_hit[104] & reg_we & !reg_error; + assign alert_cause_5_we = addr_hit[116] & reg_we & !reg_error; assign alert_cause_5_wd = reg_wdata[0]; - assign alert_cause_6_we = addr_hit[105] & reg_we & !reg_error; + assign alert_cause_6_we = addr_hit[117] & reg_we & !reg_error; assign alert_cause_6_wd = reg_wdata[0]; - assign alert_cause_7_we = addr_hit[106] & reg_we & !reg_error; + assign alert_cause_7_we = addr_hit[118] & reg_we & !reg_error; assign alert_cause_7_wd = reg_wdata[0]; - assign alert_cause_8_we = addr_hit[107] & reg_we & !reg_error; + assign alert_cause_8_we = addr_hit[119] & reg_we & !reg_error; assign alert_cause_8_wd = reg_wdata[0]; - assign alert_cause_9_we = addr_hit[108] & reg_we & !reg_error; + assign alert_cause_9_we = addr_hit[120] & reg_we & !reg_error; assign alert_cause_9_wd = reg_wdata[0]; - assign alert_cause_10_we = addr_hit[109] & reg_we & !reg_error; + assign alert_cause_10_we = addr_hit[121] & reg_we & !reg_error; assign alert_cause_10_wd = reg_wdata[0]; - assign alert_cause_11_we = addr_hit[110] & reg_we & !reg_error; + assign alert_cause_11_we = addr_hit[122] & reg_we & !reg_error; assign alert_cause_11_wd = reg_wdata[0]; - assign alert_cause_12_we = addr_hit[111] & reg_we & !reg_error; + assign alert_cause_12_we = addr_hit[123] & reg_we & !reg_error; assign alert_cause_12_wd = reg_wdata[0]; - assign alert_cause_13_we = addr_hit[112] & reg_we & !reg_error; + assign alert_cause_13_we = addr_hit[124] & reg_we & !reg_error; assign alert_cause_13_wd = reg_wdata[0]; - assign alert_cause_14_we = addr_hit[113] & reg_we & !reg_error; + assign alert_cause_14_we = addr_hit[125] & reg_we & !reg_error; assign alert_cause_14_wd = reg_wdata[0]; - assign alert_cause_15_we = addr_hit[114] & reg_we & !reg_error; + assign alert_cause_15_we = addr_hit[126] & reg_we & !reg_error; assign alert_cause_15_wd = reg_wdata[0]; - assign alert_cause_16_we = addr_hit[115] & reg_we & !reg_error; + assign alert_cause_16_we = addr_hit[127] & reg_we & !reg_error; assign alert_cause_16_wd = reg_wdata[0]; - assign alert_cause_17_we = addr_hit[116] & reg_we & !reg_error; + assign alert_cause_17_we = addr_hit[128] & reg_we & !reg_error; assign alert_cause_17_wd = reg_wdata[0]; - assign alert_cause_18_we = addr_hit[117] & reg_we & !reg_error; + assign alert_cause_18_we = addr_hit[129] & reg_we & !reg_error; assign alert_cause_18_wd = reg_wdata[0]; - assign alert_cause_19_we = addr_hit[118] & reg_we & !reg_error; + assign alert_cause_19_we = addr_hit[130] & reg_we & !reg_error; assign alert_cause_19_wd = reg_wdata[0]; - assign alert_cause_20_we = addr_hit[119] & reg_we & !reg_error; + assign alert_cause_20_we = addr_hit[131] & reg_we & !reg_error; assign alert_cause_20_wd = reg_wdata[0]; - assign alert_cause_21_we = addr_hit[120] & reg_we & !reg_error; + assign alert_cause_21_we = addr_hit[132] & reg_we & !reg_error; assign alert_cause_21_wd = reg_wdata[0]; - assign alert_cause_22_we = addr_hit[121] & reg_we & !reg_error; + assign alert_cause_22_we = addr_hit[133] & reg_we & !reg_error; assign alert_cause_22_wd = reg_wdata[0]; - assign alert_cause_23_we = addr_hit[122] & reg_we & !reg_error; + assign alert_cause_23_we = addr_hit[134] & reg_we & !reg_error; assign alert_cause_23_wd = reg_wdata[0]; - assign alert_cause_24_we = addr_hit[123] & reg_we & !reg_error; + assign alert_cause_24_we = addr_hit[135] & reg_we & !reg_error; assign alert_cause_24_wd = reg_wdata[0]; - assign alert_cause_25_we = addr_hit[124] & reg_we & !reg_error; + assign alert_cause_25_we = addr_hit[136] & reg_we & !reg_error; assign alert_cause_25_wd = reg_wdata[0]; - assign alert_cause_26_we = addr_hit[125] & reg_we & !reg_error; + assign alert_cause_26_we = addr_hit[137] & reg_we & !reg_error; assign alert_cause_26_wd = reg_wdata[0]; - assign alert_cause_27_we = addr_hit[126] & reg_we & !reg_error; + assign alert_cause_27_we = addr_hit[138] & reg_we & !reg_error; assign alert_cause_27_wd = reg_wdata[0]; - assign alert_cause_28_we = addr_hit[127] & reg_we & !reg_error; + assign alert_cause_28_we = addr_hit[139] & reg_we & !reg_error; assign alert_cause_28_wd = reg_wdata[0]; - assign alert_cause_29_we = addr_hit[128] & reg_we & !reg_error; + assign alert_cause_29_we = addr_hit[140] & reg_we & !reg_error; assign alert_cause_29_wd = reg_wdata[0]; - assign alert_cause_30_we = addr_hit[129] & reg_we & !reg_error; + assign alert_cause_30_we = addr_hit[141] & reg_we & !reg_error; assign alert_cause_30_wd = reg_wdata[0]; - assign loc_alert_regwen_0_we = addr_hit[130] & reg_we & !reg_error; + assign alert_cause_31_we = addr_hit[142] & reg_we & !reg_error; + assign alert_cause_31_wd = reg_wdata[0]; + + assign alert_cause_32_we = addr_hit[143] & reg_we & !reg_error; + assign alert_cause_32_wd = reg_wdata[0]; + + assign alert_cause_33_we = addr_hit[144] & reg_we & !reg_error; + assign alert_cause_33_wd = reg_wdata[0]; + + assign alert_cause_34_we = addr_hit[145] & reg_we & !reg_error; + assign alert_cause_34_wd = reg_wdata[0]; + + assign loc_alert_regwen_0_we = addr_hit[146] & reg_we & !reg_error; assign loc_alert_regwen_0_wd = reg_wdata[0]; - assign loc_alert_regwen_1_we = addr_hit[131] & reg_we & !reg_error; + assign loc_alert_regwen_1_we = addr_hit[147] & reg_we & !reg_error; assign loc_alert_regwen_1_wd = reg_wdata[0]; - assign loc_alert_regwen_2_we = addr_hit[132] & reg_we & !reg_error; + assign loc_alert_regwen_2_we = addr_hit[148] & reg_we & !reg_error; assign loc_alert_regwen_2_wd = reg_wdata[0]; - assign loc_alert_regwen_3_we = addr_hit[133] & reg_we & !reg_error; + assign loc_alert_regwen_3_we = addr_hit[149] & reg_we & !reg_error; assign loc_alert_regwen_3_wd = reg_wdata[0]; - assign loc_alert_regwen_4_we = addr_hit[134] & reg_we & !reg_error; + assign loc_alert_regwen_4_we = addr_hit[150] & reg_we & !reg_error; assign loc_alert_regwen_4_wd = reg_wdata[0]; - assign loc_alert_regwen_5_we = addr_hit[135] & reg_we & !reg_error; + assign loc_alert_regwen_5_we = addr_hit[151] & reg_we & !reg_error; assign loc_alert_regwen_5_wd = reg_wdata[0]; - assign loc_alert_regwen_6_we = addr_hit[136] & reg_we & !reg_error; + assign loc_alert_regwen_6_we = addr_hit[152] & reg_we & !reg_error; assign loc_alert_regwen_6_wd = reg_wdata[0]; - assign loc_alert_regwen_7_we = addr_hit[137] & reg_we & !reg_error; + assign loc_alert_regwen_7_we = addr_hit[153] & reg_we & !reg_error; assign loc_alert_regwen_7_wd = reg_wdata[0]; - assign loc_alert_regwen_8_we = addr_hit[138] & reg_we & !reg_error; + assign loc_alert_regwen_8_we = addr_hit[154] & reg_we & !reg_error; assign loc_alert_regwen_8_wd = reg_wdata[0]; - assign loc_alert_regwen_9_we = addr_hit[139] & reg_we & !reg_error; + assign loc_alert_regwen_9_we = addr_hit[155] & reg_we & !reg_error; assign loc_alert_regwen_9_wd = reg_wdata[0]; - assign loc_alert_regwen_10_we = addr_hit[140] & reg_we & !reg_error; + assign loc_alert_regwen_10_we = addr_hit[156] & reg_we & !reg_error; assign loc_alert_regwen_10_wd = reg_wdata[0]; - assign loc_alert_regwen_11_we = addr_hit[141] & reg_we & !reg_error; + assign loc_alert_regwen_11_we = addr_hit[157] & reg_we & !reg_error; assign loc_alert_regwen_11_wd = reg_wdata[0]; - assign loc_alert_regwen_12_we = addr_hit[142] & reg_we & !reg_error; + assign loc_alert_regwen_12_we = addr_hit[158] & reg_we & !reg_error; assign loc_alert_regwen_12_wd = reg_wdata[0]; - assign loc_alert_regwen_13_we = addr_hit[143] & reg_we & !reg_error; + assign loc_alert_regwen_13_we = addr_hit[159] & reg_we & !reg_error; assign loc_alert_regwen_13_wd = reg_wdata[0]; - assign loc_alert_regwen_14_we = addr_hit[144] & reg_we & !reg_error; + assign loc_alert_regwen_14_we = addr_hit[160] & reg_we & !reg_error; assign loc_alert_regwen_14_wd = reg_wdata[0]; - assign loc_alert_regwen_15_we = addr_hit[145] & reg_we & !reg_error; + assign loc_alert_regwen_15_we = addr_hit[161] & reg_we & !reg_error; assign loc_alert_regwen_15_wd = reg_wdata[0]; - assign loc_alert_regwen_16_we = addr_hit[146] & reg_we & !reg_error; + assign loc_alert_regwen_16_we = addr_hit[162] & reg_we & !reg_error; assign loc_alert_regwen_16_wd = reg_wdata[0]; - assign loc_alert_regwen_17_we = addr_hit[147] & reg_we & !reg_error; + assign loc_alert_regwen_17_we = addr_hit[163] & reg_we & !reg_error; assign loc_alert_regwen_17_wd = reg_wdata[0]; - assign loc_alert_regwen_18_we = addr_hit[148] & reg_we & !reg_error; + assign loc_alert_regwen_18_we = addr_hit[164] & reg_we & !reg_error; assign loc_alert_regwen_18_wd = reg_wdata[0]; - assign loc_alert_regwen_19_we = addr_hit[149] & reg_we & !reg_error; + assign loc_alert_regwen_19_we = addr_hit[165] & reg_we & !reg_error; assign loc_alert_regwen_19_wd = reg_wdata[0]; - assign loc_alert_regwen_20_we = addr_hit[150] & reg_we & !reg_error; + assign loc_alert_regwen_20_we = addr_hit[166] & reg_we & !reg_error; assign loc_alert_regwen_20_wd = reg_wdata[0]; - assign loc_alert_regwen_21_we = addr_hit[151] & reg_we & !reg_error; + assign loc_alert_regwen_21_we = addr_hit[167] & reg_we & !reg_error; assign loc_alert_regwen_21_wd = reg_wdata[0]; - assign loc_alert_regwen_22_we = addr_hit[152] & reg_we & !reg_error; + assign loc_alert_regwen_22_we = addr_hit[168] & reg_we & !reg_error; assign loc_alert_regwen_22_wd = reg_wdata[0]; - assign loc_alert_regwen_23_we = addr_hit[153] & reg_we & !reg_error; + assign loc_alert_regwen_23_we = addr_hit[169] & reg_we & !reg_error; assign loc_alert_regwen_23_wd = reg_wdata[0]; - assign loc_alert_regwen_24_we = addr_hit[154] & reg_we & !reg_error; + assign loc_alert_regwen_24_we = addr_hit[170] & reg_we & !reg_error; assign loc_alert_regwen_24_wd = reg_wdata[0]; - assign loc_alert_regwen_25_we = addr_hit[155] & reg_we & !reg_error; + assign loc_alert_regwen_25_we = addr_hit[171] & reg_we & !reg_error; assign loc_alert_regwen_25_wd = reg_wdata[0]; - assign loc_alert_regwen_26_we = addr_hit[156] & reg_we & !reg_error; + assign loc_alert_regwen_26_we = addr_hit[172] & reg_we & !reg_error; assign loc_alert_regwen_26_wd = reg_wdata[0]; - assign loc_alert_regwen_27_we = addr_hit[157] & reg_we & !reg_error; + assign loc_alert_regwen_27_we = addr_hit[173] & reg_we & !reg_error; assign loc_alert_regwen_27_wd = reg_wdata[0]; - assign loc_alert_regwen_28_we = addr_hit[158] & reg_we & !reg_error; + assign loc_alert_regwen_28_we = addr_hit[174] & reg_we & !reg_error; assign loc_alert_regwen_28_wd = reg_wdata[0]; - assign loc_alert_regwen_29_we = addr_hit[159] & reg_we & !reg_error; + assign loc_alert_regwen_29_we = addr_hit[175] & reg_we & !reg_error; assign loc_alert_regwen_29_wd = reg_wdata[0]; - assign loc_alert_regwen_30_we = addr_hit[160] & reg_we & !reg_error; + assign loc_alert_regwen_30_we = addr_hit[176] & reg_we & !reg_error; assign loc_alert_regwen_30_wd = reg_wdata[0]; - assign loc_alert_en_0_we = addr_hit[161] & reg_we & !reg_error; + assign loc_alert_regwen_31_we = addr_hit[177] & reg_we & !reg_error; + assign loc_alert_regwen_31_wd = reg_wdata[0]; + + assign loc_alert_regwen_32_we = addr_hit[178] & reg_we & !reg_error; + assign loc_alert_regwen_32_wd = reg_wdata[0]; + + assign loc_alert_regwen_33_we = addr_hit[179] & reg_we & !reg_error; + assign loc_alert_regwen_33_wd = reg_wdata[0]; + + assign loc_alert_regwen_34_we = addr_hit[180] & reg_we & !reg_error; + assign loc_alert_regwen_34_wd = reg_wdata[0]; + + assign loc_alert_en_0_we = addr_hit[181] & reg_we & !reg_error; assign loc_alert_en_0_wd = reg_wdata[0]; - assign loc_alert_en_1_we = addr_hit[162] & reg_we & !reg_error; + assign loc_alert_en_1_we = addr_hit[182] & reg_we & !reg_error; assign loc_alert_en_1_wd = reg_wdata[0]; - assign loc_alert_en_2_we = addr_hit[163] & reg_we & !reg_error; + assign loc_alert_en_2_we = addr_hit[183] & reg_we & !reg_error; assign loc_alert_en_2_wd = reg_wdata[0]; - assign loc_alert_en_3_we = addr_hit[164] & reg_we & !reg_error; + assign loc_alert_en_3_we = addr_hit[184] & reg_we & !reg_error; assign loc_alert_en_3_wd = reg_wdata[0]; - assign loc_alert_class_0_we = addr_hit[165] & reg_we & !reg_error; + assign loc_alert_class_0_we = addr_hit[185] & reg_we & !reg_error; assign loc_alert_class_0_wd = reg_wdata[1:0]; - assign loc_alert_class_1_we = addr_hit[166] & reg_we & !reg_error; + assign loc_alert_class_1_we = addr_hit[186] & reg_we & !reg_error; assign loc_alert_class_1_wd = reg_wdata[1:0]; - assign loc_alert_class_2_we = addr_hit[167] & reg_we & !reg_error; + assign loc_alert_class_2_we = addr_hit[187] & reg_we & !reg_error; assign loc_alert_class_2_wd = reg_wdata[1:0]; - assign loc_alert_class_3_we = addr_hit[168] & reg_we & !reg_error; + assign loc_alert_class_3_we = addr_hit[188] & reg_we & !reg_error; assign loc_alert_class_3_wd = reg_wdata[1:0]; - assign loc_alert_cause_0_we = addr_hit[169] & reg_we & !reg_error; + assign loc_alert_cause_0_we = addr_hit[189] & reg_we & !reg_error; assign loc_alert_cause_0_wd = reg_wdata[0]; - assign loc_alert_cause_1_we = addr_hit[170] & reg_we & !reg_error; + assign loc_alert_cause_1_we = addr_hit[190] & reg_we & !reg_error; assign loc_alert_cause_1_wd = reg_wdata[0]; - assign loc_alert_cause_2_we = addr_hit[171] & reg_we & !reg_error; + assign loc_alert_cause_2_we = addr_hit[191] & reg_we & !reg_error; assign loc_alert_cause_2_wd = reg_wdata[0]; - assign loc_alert_cause_3_we = addr_hit[172] & reg_we & !reg_error; + assign loc_alert_cause_3_we = addr_hit[192] & reg_we & !reg_error; assign loc_alert_cause_3_wd = reg_wdata[0]; - assign classa_regwen_we = addr_hit[173] & reg_we & !reg_error; + assign classa_regwen_we = addr_hit[193] & reg_we & !reg_error; assign classa_regwen_wd = reg_wdata[0]; - assign classa_ctrl_en_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_en_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_en_wd = reg_wdata[0]; - assign classa_ctrl_lock_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_lock_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_lock_wd = reg_wdata[1]; - assign classa_ctrl_en_e0_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_en_e0_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_en_e0_wd = reg_wdata[2]; - assign classa_ctrl_en_e1_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_en_e1_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_en_e1_wd = reg_wdata[3]; - assign classa_ctrl_en_e2_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_en_e2_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_en_e2_wd = reg_wdata[4]; - assign classa_ctrl_en_e3_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_en_e3_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_en_e3_wd = reg_wdata[5]; - assign classa_ctrl_map_e0_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_map_e0_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_map_e0_wd = reg_wdata[7:6]; - assign classa_ctrl_map_e1_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_map_e1_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_map_e1_wd = reg_wdata[9:8]; - assign classa_ctrl_map_e2_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_map_e2_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_map_e2_wd = reg_wdata[11:10]; - assign classa_ctrl_map_e3_we = addr_hit[174] & reg_we & !reg_error; + assign classa_ctrl_map_e3_we = addr_hit[194] & reg_we & !reg_error; assign classa_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classa_clr_regwen_we = addr_hit[175] & reg_we & !reg_error; + assign classa_clr_regwen_we = addr_hit[195] & reg_we & !reg_error; assign classa_clr_regwen_wd = reg_wdata[0]; - assign classa_clr_we = addr_hit[176] & reg_we & !reg_error; + assign classa_clr_we = addr_hit[196] & reg_we & !reg_error; assign classa_clr_wd = reg_wdata[0]; - assign classa_accum_cnt_re = addr_hit[177] & reg_re & !reg_error; + assign classa_accum_cnt_re = addr_hit[197] & reg_re & !reg_error; - assign classa_accum_thresh_we = addr_hit[178] & reg_we & !reg_error; + assign classa_accum_thresh_we = addr_hit[198] & reg_we & !reg_error; assign classa_accum_thresh_wd = reg_wdata[15:0]; - assign classa_timeout_cyc_we = addr_hit[179] & reg_we & !reg_error; + assign classa_timeout_cyc_we = addr_hit[199] & reg_we & !reg_error; assign classa_timeout_cyc_wd = reg_wdata[31:0]; - assign classa_phase0_cyc_we = addr_hit[180] & reg_we & !reg_error; + assign classa_phase0_cyc_we = addr_hit[200] & reg_we & !reg_error; assign classa_phase0_cyc_wd = reg_wdata[31:0]; - assign classa_phase1_cyc_we = addr_hit[181] & reg_we & !reg_error; + assign classa_phase1_cyc_we = addr_hit[201] & reg_we & !reg_error; assign classa_phase1_cyc_wd = reg_wdata[31:0]; - assign classa_phase2_cyc_we = addr_hit[182] & reg_we & !reg_error; + assign classa_phase2_cyc_we = addr_hit[202] & reg_we & !reg_error; assign classa_phase2_cyc_wd = reg_wdata[31:0]; - assign classa_phase3_cyc_we = addr_hit[183] & reg_we & !reg_error; + assign classa_phase3_cyc_we = addr_hit[203] & reg_we & !reg_error; assign classa_phase3_cyc_wd = reg_wdata[31:0]; - assign classa_esc_cnt_re = addr_hit[184] & reg_re & !reg_error; + assign classa_esc_cnt_re = addr_hit[204] & reg_re & !reg_error; - assign classa_state_re = addr_hit[185] & reg_re & !reg_error; + assign classa_state_re = addr_hit[205] & reg_re & !reg_error; - assign classb_regwen_we = addr_hit[186] & reg_we & !reg_error; + assign classb_regwen_we = addr_hit[206] & reg_we & !reg_error; assign classb_regwen_wd = reg_wdata[0]; - assign classb_ctrl_en_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_en_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_en_wd = reg_wdata[0]; - assign classb_ctrl_lock_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_lock_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_lock_wd = reg_wdata[1]; - assign classb_ctrl_en_e0_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_en_e0_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_en_e0_wd = reg_wdata[2]; - assign classb_ctrl_en_e1_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_en_e1_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_en_e1_wd = reg_wdata[3]; - assign classb_ctrl_en_e2_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_en_e2_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_en_e2_wd = reg_wdata[4]; - assign classb_ctrl_en_e3_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_en_e3_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_en_e3_wd = reg_wdata[5]; - assign classb_ctrl_map_e0_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_map_e0_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_map_e0_wd = reg_wdata[7:6]; - assign classb_ctrl_map_e1_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_map_e1_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_map_e1_wd = reg_wdata[9:8]; - assign classb_ctrl_map_e2_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_map_e2_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_map_e2_wd = reg_wdata[11:10]; - assign classb_ctrl_map_e3_we = addr_hit[187] & reg_we & !reg_error; + assign classb_ctrl_map_e3_we = addr_hit[207] & reg_we & !reg_error; assign classb_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classb_clr_regwen_we = addr_hit[188] & reg_we & !reg_error; + assign classb_clr_regwen_we = addr_hit[208] & reg_we & !reg_error; assign classb_clr_regwen_wd = reg_wdata[0]; - assign classb_clr_we = addr_hit[189] & reg_we & !reg_error; + assign classb_clr_we = addr_hit[209] & reg_we & !reg_error; assign classb_clr_wd = reg_wdata[0]; - assign classb_accum_cnt_re = addr_hit[190] & reg_re & !reg_error; + assign classb_accum_cnt_re = addr_hit[210] & reg_re & !reg_error; - assign classb_accum_thresh_we = addr_hit[191] & reg_we & !reg_error; + assign classb_accum_thresh_we = addr_hit[211] & reg_we & !reg_error; assign classb_accum_thresh_wd = reg_wdata[15:0]; - assign classb_timeout_cyc_we = addr_hit[192] & reg_we & !reg_error; + assign classb_timeout_cyc_we = addr_hit[212] & reg_we & !reg_error; assign classb_timeout_cyc_wd = reg_wdata[31:0]; - assign classb_phase0_cyc_we = addr_hit[193] & reg_we & !reg_error; + assign classb_phase0_cyc_we = addr_hit[213] & reg_we & !reg_error; assign classb_phase0_cyc_wd = reg_wdata[31:0]; - assign classb_phase1_cyc_we = addr_hit[194] & reg_we & !reg_error; + assign classb_phase1_cyc_we = addr_hit[214] & reg_we & !reg_error; assign classb_phase1_cyc_wd = reg_wdata[31:0]; - assign classb_phase2_cyc_we = addr_hit[195] & reg_we & !reg_error; + assign classb_phase2_cyc_we = addr_hit[215] & reg_we & !reg_error; assign classb_phase2_cyc_wd = reg_wdata[31:0]; - assign classb_phase3_cyc_we = addr_hit[196] & reg_we & !reg_error; + assign classb_phase3_cyc_we = addr_hit[216] & reg_we & !reg_error; assign classb_phase3_cyc_wd = reg_wdata[31:0]; - assign classb_esc_cnt_re = addr_hit[197] & reg_re & !reg_error; + assign classb_esc_cnt_re = addr_hit[217] & reg_re & !reg_error; - assign classb_state_re = addr_hit[198] & reg_re & !reg_error; + assign classb_state_re = addr_hit[218] & reg_re & !reg_error; - assign classc_regwen_we = addr_hit[199] & reg_we & !reg_error; + assign classc_regwen_we = addr_hit[219] & reg_we & !reg_error; assign classc_regwen_wd = reg_wdata[0]; - assign classc_ctrl_en_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_en_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_en_wd = reg_wdata[0]; - assign classc_ctrl_lock_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_lock_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_lock_wd = reg_wdata[1]; - assign classc_ctrl_en_e0_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_en_e0_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_en_e0_wd = reg_wdata[2]; - assign classc_ctrl_en_e1_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_en_e1_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_en_e1_wd = reg_wdata[3]; - assign classc_ctrl_en_e2_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_en_e2_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_en_e2_wd = reg_wdata[4]; - assign classc_ctrl_en_e3_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_en_e3_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_en_e3_wd = reg_wdata[5]; - assign classc_ctrl_map_e0_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_map_e0_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_map_e0_wd = reg_wdata[7:6]; - assign classc_ctrl_map_e1_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_map_e1_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_map_e1_wd = reg_wdata[9:8]; - assign classc_ctrl_map_e2_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_map_e2_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_map_e2_wd = reg_wdata[11:10]; - assign classc_ctrl_map_e3_we = addr_hit[200] & reg_we & !reg_error; + assign classc_ctrl_map_e3_we = addr_hit[220] & reg_we & !reg_error; assign classc_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classc_clr_regwen_we = addr_hit[201] & reg_we & !reg_error; + assign classc_clr_regwen_we = addr_hit[221] & reg_we & !reg_error; assign classc_clr_regwen_wd = reg_wdata[0]; - assign classc_clr_we = addr_hit[202] & reg_we & !reg_error; + assign classc_clr_we = addr_hit[222] & reg_we & !reg_error; assign classc_clr_wd = reg_wdata[0]; - assign classc_accum_cnt_re = addr_hit[203] & reg_re & !reg_error; + assign classc_accum_cnt_re = addr_hit[223] & reg_re & !reg_error; - assign classc_accum_thresh_we = addr_hit[204] & reg_we & !reg_error; + assign classc_accum_thresh_we = addr_hit[224] & reg_we & !reg_error; assign classc_accum_thresh_wd = reg_wdata[15:0]; - assign classc_timeout_cyc_we = addr_hit[205] & reg_we & !reg_error; + assign classc_timeout_cyc_we = addr_hit[225] & reg_we & !reg_error; assign classc_timeout_cyc_wd = reg_wdata[31:0]; - assign classc_phase0_cyc_we = addr_hit[206] & reg_we & !reg_error; + assign classc_phase0_cyc_we = addr_hit[226] & reg_we & !reg_error; assign classc_phase0_cyc_wd = reg_wdata[31:0]; - assign classc_phase1_cyc_we = addr_hit[207] & reg_we & !reg_error; + assign classc_phase1_cyc_we = addr_hit[227] & reg_we & !reg_error; assign classc_phase1_cyc_wd = reg_wdata[31:0]; - assign classc_phase2_cyc_we = addr_hit[208] & reg_we & !reg_error; + assign classc_phase2_cyc_we = addr_hit[228] & reg_we & !reg_error; assign classc_phase2_cyc_wd = reg_wdata[31:0]; - assign classc_phase3_cyc_we = addr_hit[209] & reg_we & !reg_error; + assign classc_phase3_cyc_we = addr_hit[229] & reg_we & !reg_error; assign classc_phase3_cyc_wd = reg_wdata[31:0]; - assign classc_esc_cnt_re = addr_hit[210] & reg_re & !reg_error; + assign classc_esc_cnt_re = addr_hit[230] & reg_re & !reg_error; - assign classc_state_re = addr_hit[211] & reg_re & !reg_error; + assign classc_state_re = addr_hit[231] & reg_re & !reg_error; - assign classd_regwen_we = addr_hit[212] & reg_we & !reg_error; + assign classd_regwen_we = addr_hit[232] & reg_we & !reg_error; assign classd_regwen_wd = reg_wdata[0]; - assign classd_ctrl_en_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_en_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_en_wd = reg_wdata[0]; - assign classd_ctrl_lock_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_lock_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_lock_wd = reg_wdata[1]; - assign classd_ctrl_en_e0_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_en_e0_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_en_e0_wd = reg_wdata[2]; - assign classd_ctrl_en_e1_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_en_e1_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_en_e1_wd = reg_wdata[3]; - assign classd_ctrl_en_e2_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_en_e2_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_en_e2_wd = reg_wdata[4]; - assign classd_ctrl_en_e3_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_en_e3_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_en_e3_wd = reg_wdata[5]; - assign classd_ctrl_map_e0_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_map_e0_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_map_e0_wd = reg_wdata[7:6]; - assign classd_ctrl_map_e1_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_map_e1_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_map_e1_wd = reg_wdata[9:8]; - assign classd_ctrl_map_e2_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_map_e2_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_map_e2_wd = reg_wdata[11:10]; - assign classd_ctrl_map_e3_we = addr_hit[213] & reg_we & !reg_error; + assign classd_ctrl_map_e3_we = addr_hit[233] & reg_we & !reg_error; assign classd_ctrl_map_e3_wd = reg_wdata[13:12]; - assign classd_clr_regwen_we = addr_hit[214] & reg_we & !reg_error; + assign classd_clr_regwen_we = addr_hit[234] & reg_we & !reg_error; assign classd_clr_regwen_wd = reg_wdata[0]; - assign classd_clr_we = addr_hit[215] & reg_we & !reg_error; + assign classd_clr_we = addr_hit[235] & reg_we & !reg_error; assign classd_clr_wd = reg_wdata[0]; - assign classd_accum_cnt_re = addr_hit[216] & reg_re & !reg_error; + assign classd_accum_cnt_re = addr_hit[236] & reg_re & !reg_error; - assign classd_accum_thresh_we = addr_hit[217] & reg_we & !reg_error; + assign classd_accum_thresh_we = addr_hit[237] & reg_we & !reg_error; assign classd_accum_thresh_wd = reg_wdata[15:0]; - assign classd_timeout_cyc_we = addr_hit[218] & reg_we & !reg_error; + assign classd_timeout_cyc_we = addr_hit[238] & reg_we & !reg_error; assign classd_timeout_cyc_wd = reg_wdata[31:0]; - assign classd_phase0_cyc_we = addr_hit[219] & reg_we & !reg_error; + assign classd_phase0_cyc_we = addr_hit[239] & reg_we & !reg_error; assign classd_phase0_cyc_wd = reg_wdata[31:0]; - assign classd_phase1_cyc_we = addr_hit[220] & reg_we & !reg_error; + assign classd_phase1_cyc_we = addr_hit[240] & reg_we & !reg_error; assign classd_phase1_cyc_wd = reg_wdata[31:0]; - assign classd_phase2_cyc_we = addr_hit[221] & reg_we & !reg_error; + assign classd_phase2_cyc_we = addr_hit[241] & reg_we & !reg_error; assign classd_phase2_cyc_wd = reg_wdata[31:0]; - assign classd_phase3_cyc_we = addr_hit[222] & reg_we & !reg_error; + assign classd_phase3_cyc_we = addr_hit[242] & reg_we & !reg_error; assign classd_phase3_cyc_wd = reg_wdata[31:0]; - assign classd_esc_cnt_re = addr_hit[223] & reg_re & !reg_error; + assign classd_esc_cnt_re = addr_hit[243] & reg_re & !reg_error; - assign classd_state_re = addr_hit[224] & reg_re & !reg_error; + assign classd_state_re = addr_hit[244] & reg_re & !reg_error; // Read data return always_comb begin @@ -9408,554 +10108,634 @@ end addr_hit[37]: begin - reg_rdata_next[0] = alert_en_0_qs; + reg_rdata_next[0] = alert_regwen_31_qs; end addr_hit[38]: begin - reg_rdata_next[0] = alert_en_1_qs; + reg_rdata_next[0] = alert_regwen_32_qs; end addr_hit[39]: begin - reg_rdata_next[0] = alert_en_2_qs; + reg_rdata_next[0] = alert_regwen_33_qs; end addr_hit[40]: begin - reg_rdata_next[0] = alert_en_3_qs; + reg_rdata_next[0] = alert_regwen_34_qs; end addr_hit[41]: begin - reg_rdata_next[0] = alert_en_4_qs; + reg_rdata_next[0] = alert_en_0_qs; end addr_hit[42]: begin - reg_rdata_next[0] = alert_en_5_qs; + reg_rdata_next[0] = alert_en_1_qs; end addr_hit[43]: begin - reg_rdata_next[0] = alert_en_6_qs; + reg_rdata_next[0] = alert_en_2_qs; end addr_hit[44]: begin - reg_rdata_next[0] = alert_en_7_qs; + reg_rdata_next[0] = alert_en_3_qs; end addr_hit[45]: begin - reg_rdata_next[0] = alert_en_8_qs; + reg_rdata_next[0] = alert_en_4_qs; end addr_hit[46]: begin - reg_rdata_next[0] = alert_en_9_qs; + reg_rdata_next[0] = alert_en_5_qs; end addr_hit[47]: begin - reg_rdata_next[0] = alert_en_10_qs; + reg_rdata_next[0] = alert_en_6_qs; end addr_hit[48]: begin - reg_rdata_next[0] = alert_en_11_qs; + reg_rdata_next[0] = alert_en_7_qs; end addr_hit[49]: begin - reg_rdata_next[0] = alert_en_12_qs; + reg_rdata_next[0] = alert_en_8_qs; end addr_hit[50]: begin - reg_rdata_next[0] = alert_en_13_qs; + reg_rdata_next[0] = alert_en_9_qs; end addr_hit[51]: begin - reg_rdata_next[0] = alert_en_14_qs; + reg_rdata_next[0] = alert_en_10_qs; end addr_hit[52]: begin - reg_rdata_next[0] = alert_en_15_qs; + reg_rdata_next[0] = alert_en_11_qs; end addr_hit[53]: begin - reg_rdata_next[0] = alert_en_16_qs; + reg_rdata_next[0] = alert_en_12_qs; end addr_hit[54]: begin - reg_rdata_next[0] = alert_en_17_qs; + reg_rdata_next[0] = alert_en_13_qs; end addr_hit[55]: begin - reg_rdata_next[0] = alert_en_18_qs; + reg_rdata_next[0] = alert_en_14_qs; end addr_hit[56]: begin - reg_rdata_next[0] = alert_en_19_qs; + reg_rdata_next[0] = alert_en_15_qs; end addr_hit[57]: begin - reg_rdata_next[0] = alert_en_20_qs; + reg_rdata_next[0] = alert_en_16_qs; end addr_hit[58]: begin - reg_rdata_next[0] = alert_en_21_qs; + reg_rdata_next[0] = alert_en_17_qs; end addr_hit[59]: begin - reg_rdata_next[0] = alert_en_22_qs; + reg_rdata_next[0] = alert_en_18_qs; end addr_hit[60]: begin - reg_rdata_next[0] = alert_en_23_qs; + reg_rdata_next[0] = alert_en_19_qs; end addr_hit[61]: begin - reg_rdata_next[0] = alert_en_24_qs; + reg_rdata_next[0] = alert_en_20_qs; end addr_hit[62]: begin - reg_rdata_next[0] = alert_en_25_qs; + reg_rdata_next[0] = alert_en_21_qs; end addr_hit[63]: begin - reg_rdata_next[0] = alert_en_26_qs; + reg_rdata_next[0] = alert_en_22_qs; end addr_hit[64]: begin - reg_rdata_next[0] = alert_en_27_qs; + reg_rdata_next[0] = alert_en_23_qs; end addr_hit[65]: begin - reg_rdata_next[0] = alert_en_28_qs; + reg_rdata_next[0] = alert_en_24_qs; end addr_hit[66]: begin - reg_rdata_next[0] = alert_en_29_qs; + reg_rdata_next[0] = alert_en_25_qs; end addr_hit[67]: begin - reg_rdata_next[0] = alert_en_30_qs; + reg_rdata_next[0] = alert_en_26_qs; end addr_hit[68]: begin - reg_rdata_next[1:0] = alert_class_0_qs; + reg_rdata_next[0] = alert_en_27_qs; end addr_hit[69]: begin - reg_rdata_next[1:0] = alert_class_1_qs; + reg_rdata_next[0] = alert_en_28_qs; end addr_hit[70]: begin - reg_rdata_next[1:0] = alert_class_2_qs; + reg_rdata_next[0] = alert_en_29_qs; end addr_hit[71]: begin - reg_rdata_next[1:0] = alert_class_3_qs; + reg_rdata_next[0] = alert_en_30_qs; end addr_hit[72]: begin - reg_rdata_next[1:0] = alert_class_4_qs; + reg_rdata_next[0] = alert_en_31_qs; end addr_hit[73]: begin - reg_rdata_next[1:0] = alert_class_5_qs; + reg_rdata_next[0] = alert_en_32_qs; end addr_hit[74]: begin - reg_rdata_next[1:0] = alert_class_6_qs; + reg_rdata_next[0] = alert_en_33_qs; end addr_hit[75]: begin - reg_rdata_next[1:0] = alert_class_7_qs; + reg_rdata_next[0] = alert_en_34_qs; end addr_hit[76]: begin - reg_rdata_next[1:0] = alert_class_8_qs; + reg_rdata_next[1:0] = alert_class_0_qs; end addr_hit[77]: begin - reg_rdata_next[1:0] = alert_class_9_qs; + reg_rdata_next[1:0] = alert_class_1_qs; end addr_hit[78]: begin - reg_rdata_next[1:0] = alert_class_10_qs; + reg_rdata_next[1:0] = alert_class_2_qs; end addr_hit[79]: begin - reg_rdata_next[1:0] = alert_class_11_qs; + reg_rdata_next[1:0] = alert_class_3_qs; end addr_hit[80]: begin - reg_rdata_next[1:0] = alert_class_12_qs; + reg_rdata_next[1:0] = alert_class_4_qs; end addr_hit[81]: begin - reg_rdata_next[1:0] = alert_class_13_qs; + reg_rdata_next[1:0] = alert_class_5_qs; end addr_hit[82]: begin - reg_rdata_next[1:0] = alert_class_14_qs; + reg_rdata_next[1:0] = alert_class_6_qs; end addr_hit[83]: begin - reg_rdata_next[1:0] = alert_class_15_qs; + reg_rdata_next[1:0] = alert_class_7_qs; end addr_hit[84]: begin - reg_rdata_next[1:0] = alert_class_16_qs; + reg_rdata_next[1:0] = alert_class_8_qs; end addr_hit[85]: begin - reg_rdata_next[1:0] = alert_class_17_qs; + reg_rdata_next[1:0] = alert_class_9_qs; end addr_hit[86]: begin - reg_rdata_next[1:0] = alert_class_18_qs; + reg_rdata_next[1:0] = alert_class_10_qs; end addr_hit[87]: begin - reg_rdata_next[1:0] = alert_class_19_qs; + reg_rdata_next[1:0] = alert_class_11_qs; end addr_hit[88]: begin - reg_rdata_next[1:0] = alert_class_20_qs; + reg_rdata_next[1:0] = alert_class_12_qs; end addr_hit[89]: begin - reg_rdata_next[1:0] = alert_class_21_qs; + reg_rdata_next[1:0] = alert_class_13_qs; end addr_hit[90]: begin - reg_rdata_next[1:0] = alert_class_22_qs; + reg_rdata_next[1:0] = alert_class_14_qs; end addr_hit[91]: begin - reg_rdata_next[1:0] = alert_class_23_qs; + reg_rdata_next[1:0] = alert_class_15_qs; end addr_hit[92]: begin - reg_rdata_next[1:0] = alert_class_24_qs; + reg_rdata_next[1:0] = alert_class_16_qs; end addr_hit[93]: begin - reg_rdata_next[1:0] = alert_class_25_qs; + reg_rdata_next[1:0] = alert_class_17_qs; end addr_hit[94]: begin - reg_rdata_next[1:0] = alert_class_26_qs; + reg_rdata_next[1:0] = alert_class_18_qs; end addr_hit[95]: begin - reg_rdata_next[1:0] = alert_class_27_qs; + reg_rdata_next[1:0] = alert_class_19_qs; end addr_hit[96]: begin - reg_rdata_next[1:0] = alert_class_28_qs; + reg_rdata_next[1:0] = alert_class_20_qs; end addr_hit[97]: begin - reg_rdata_next[1:0] = alert_class_29_qs; + reg_rdata_next[1:0] = alert_class_21_qs; end addr_hit[98]: begin - reg_rdata_next[1:0] = alert_class_30_qs; + reg_rdata_next[1:0] = alert_class_22_qs; end addr_hit[99]: begin - reg_rdata_next[0] = alert_cause_0_qs; + reg_rdata_next[1:0] = alert_class_23_qs; end addr_hit[100]: begin - reg_rdata_next[0] = alert_cause_1_qs; + reg_rdata_next[1:0] = alert_class_24_qs; end addr_hit[101]: begin - reg_rdata_next[0] = alert_cause_2_qs; + reg_rdata_next[1:0] = alert_class_25_qs; end addr_hit[102]: begin - reg_rdata_next[0] = alert_cause_3_qs; + reg_rdata_next[1:0] = alert_class_26_qs; end addr_hit[103]: begin - reg_rdata_next[0] = alert_cause_4_qs; + reg_rdata_next[1:0] = alert_class_27_qs; end addr_hit[104]: begin - reg_rdata_next[0] = alert_cause_5_qs; + reg_rdata_next[1:0] = alert_class_28_qs; end addr_hit[105]: begin - reg_rdata_next[0] = alert_cause_6_qs; + reg_rdata_next[1:0] = alert_class_29_qs; end addr_hit[106]: begin - reg_rdata_next[0] = alert_cause_7_qs; + reg_rdata_next[1:0] = alert_class_30_qs; end addr_hit[107]: begin - reg_rdata_next[0] = alert_cause_8_qs; + reg_rdata_next[1:0] = alert_class_31_qs; end addr_hit[108]: begin - reg_rdata_next[0] = alert_cause_9_qs; + reg_rdata_next[1:0] = alert_class_32_qs; end addr_hit[109]: begin - reg_rdata_next[0] = alert_cause_10_qs; + reg_rdata_next[1:0] = alert_class_33_qs; end addr_hit[110]: begin - reg_rdata_next[0] = alert_cause_11_qs; + reg_rdata_next[1:0] = alert_class_34_qs; end addr_hit[111]: begin - reg_rdata_next[0] = alert_cause_12_qs; + reg_rdata_next[0] = alert_cause_0_qs; end addr_hit[112]: begin - reg_rdata_next[0] = alert_cause_13_qs; + reg_rdata_next[0] = alert_cause_1_qs; end addr_hit[113]: begin - reg_rdata_next[0] = alert_cause_14_qs; + reg_rdata_next[0] = alert_cause_2_qs; end addr_hit[114]: begin - reg_rdata_next[0] = alert_cause_15_qs; + reg_rdata_next[0] = alert_cause_3_qs; end addr_hit[115]: begin - reg_rdata_next[0] = alert_cause_16_qs; + reg_rdata_next[0] = alert_cause_4_qs; end addr_hit[116]: begin - reg_rdata_next[0] = alert_cause_17_qs; + reg_rdata_next[0] = alert_cause_5_qs; end addr_hit[117]: begin - reg_rdata_next[0] = alert_cause_18_qs; + reg_rdata_next[0] = alert_cause_6_qs; end addr_hit[118]: begin - reg_rdata_next[0] = alert_cause_19_qs; + reg_rdata_next[0] = alert_cause_7_qs; end addr_hit[119]: begin - reg_rdata_next[0] = alert_cause_20_qs; + reg_rdata_next[0] = alert_cause_8_qs; end addr_hit[120]: begin - reg_rdata_next[0] = alert_cause_21_qs; + reg_rdata_next[0] = alert_cause_9_qs; end addr_hit[121]: begin - reg_rdata_next[0] = alert_cause_22_qs; + reg_rdata_next[0] = alert_cause_10_qs; end addr_hit[122]: begin - reg_rdata_next[0] = alert_cause_23_qs; + reg_rdata_next[0] = alert_cause_11_qs; end addr_hit[123]: begin - reg_rdata_next[0] = alert_cause_24_qs; + reg_rdata_next[0] = alert_cause_12_qs; end addr_hit[124]: begin - reg_rdata_next[0] = alert_cause_25_qs; + reg_rdata_next[0] = alert_cause_13_qs; end addr_hit[125]: begin - reg_rdata_next[0] = alert_cause_26_qs; + reg_rdata_next[0] = alert_cause_14_qs; end addr_hit[126]: begin - reg_rdata_next[0] = alert_cause_27_qs; + reg_rdata_next[0] = alert_cause_15_qs; end addr_hit[127]: begin - reg_rdata_next[0] = alert_cause_28_qs; + reg_rdata_next[0] = alert_cause_16_qs; end addr_hit[128]: begin - reg_rdata_next[0] = alert_cause_29_qs; + reg_rdata_next[0] = alert_cause_17_qs; end addr_hit[129]: begin - reg_rdata_next[0] = alert_cause_30_qs; + reg_rdata_next[0] = alert_cause_18_qs; end addr_hit[130]: begin - reg_rdata_next[0] = loc_alert_regwen_0_qs; + reg_rdata_next[0] = alert_cause_19_qs; end addr_hit[131]: begin - reg_rdata_next[0] = loc_alert_regwen_1_qs; + reg_rdata_next[0] = alert_cause_20_qs; end addr_hit[132]: begin - reg_rdata_next[0] = loc_alert_regwen_2_qs; + reg_rdata_next[0] = alert_cause_21_qs; end addr_hit[133]: begin - reg_rdata_next[0] = loc_alert_regwen_3_qs; + reg_rdata_next[0] = alert_cause_22_qs; end addr_hit[134]: begin - reg_rdata_next[0] = loc_alert_regwen_4_qs; + reg_rdata_next[0] = alert_cause_23_qs; end addr_hit[135]: begin - reg_rdata_next[0] = loc_alert_regwen_5_qs; + reg_rdata_next[0] = alert_cause_24_qs; end addr_hit[136]: begin - reg_rdata_next[0] = loc_alert_regwen_6_qs; + reg_rdata_next[0] = alert_cause_25_qs; end addr_hit[137]: begin - reg_rdata_next[0] = loc_alert_regwen_7_qs; + reg_rdata_next[0] = alert_cause_26_qs; end addr_hit[138]: begin - reg_rdata_next[0] = loc_alert_regwen_8_qs; + reg_rdata_next[0] = alert_cause_27_qs; end addr_hit[139]: begin - reg_rdata_next[0] = loc_alert_regwen_9_qs; + reg_rdata_next[0] = alert_cause_28_qs; end addr_hit[140]: begin - reg_rdata_next[0] = loc_alert_regwen_10_qs; + reg_rdata_next[0] = alert_cause_29_qs; end addr_hit[141]: begin - reg_rdata_next[0] = loc_alert_regwen_11_qs; + reg_rdata_next[0] = alert_cause_30_qs; end addr_hit[142]: begin - reg_rdata_next[0] = loc_alert_regwen_12_qs; + reg_rdata_next[0] = alert_cause_31_qs; end addr_hit[143]: begin - reg_rdata_next[0] = loc_alert_regwen_13_qs; + reg_rdata_next[0] = alert_cause_32_qs; end addr_hit[144]: begin - reg_rdata_next[0] = loc_alert_regwen_14_qs; + reg_rdata_next[0] = alert_cause_33_qs; end addr_hit[145]: begin - reg_rdata_next[0] = loc_alert_regwen_15_qs; + reg_rdata_next[0] = alert_cause_34_qs; end addr_hit[146]: begin - reg_rdata_next[0] = loc_alert_regwen_16_qs; + reg_rdata_next[0] = loc_alert_regwen_0_qs; end addr_hit[147]: begin - reg_rdata_next[0] = loc_alert_regwen_17_qs; + reg_rdata_next[0] = loc_alert_regwen_1_qs; end addr_hit[148]: begin - reg_rdata_next[0] = loc_alert_regwen_18_qs; + reg_rdata_next[0] = loc_alert_regwen_2_qs; end addr_hit[149]: begin - reg_rdata_next[0] = loc_alert_regwen_19_qs; + reg_rdata_next[0] = loc_alert_regwen_3_qs; end addr_hit[150]: begin - reg_rdata_next[0] = loc_alert_regwen_20_qs; + reg_rdata_next[0] = loc_alert_regwen_4_qs; end addr_hit[151]: begin - reg_rdata_next[0] = loc_alert_regwen_21_qs; + reg_rdata_next[0] = loc_alert_regwen_5_qs; end addr_hit[152]: begin - reg_rdata_next[0] = loc_alert_regwen_22_qs; + reg_rdata_next[0] = loc_alert_regwen_6_qs; end addr_hit[153]: begin - reg_rdata_next[0] = loc_alert_regwen_23_qs; + reg_rdata_next[0] = loc_alert_regwen_7_qs; end addr_hit[154]: begin - reg_rdata_next[0] = loc_alert_regwen_24_qs; + reg_rdata_next[0] = loc_alert_regwen_8_qs; end addr_hit[155]: begin - reg_rdata_next[0] = loc_alert_regwen_25_qs; + reg_rdata_next[0] = loc_alert_regwen_9_qs; end addr_hit[156]: begin - reg_rdata_next[0] = loc_alert_regwen_26_qs; + reg_rdata_next[0] = loc_alert_regwen_10_qs; end addr_hit[157]: begin - reg_rdata_next[0] = loc_alert_regwen_27_qs; + reg_rdata_next[0] = loc_alert_regwen_11_qs; end addr_hit[158]: begin - reg_rdata_next[0] = loc_alert_regwen_28_qs; + reg_rdata_next[0] = loc_alert_regwen_12_qs; end addr_hit[159]: begin - reg_rdata_next[0] = loc_alert_regwen_29_qs; + reg_rdata_next[0] = loc_alert_regwen_13_qs; end addr_hit[160]: begin - reg_rdata_next[0] = loc_alert_regwen_30_qs; + reg_rdata_next[0] = loc_alert_regwen_14_qs; end addr_hit[161]: begin - reg_rdata_next[0] = loc_alert_en_0_qs; + reg_rdata_next[0] = loc_alert_regwen_15_qs; end addr_hit[162]: begin - reg_rdata_next[0] = loc_alert_en_1_qs; + reg_rdata_next[0] = loc_alert_regwen_16_qs; end addr_hit[163]: begin - reg_rdata_next[0] = loc_alert_en_2_qs; + reg_rdata_next[0] = loc_alert_regwen_17_qs; end addr_hit[164]: begin - reg_rdata_next[0] = loc_alert_en_3_qs; + reg_rdata_next[0] = loc_alert_regwen_18_qs; end addr_hit[165]: begin - reg_rdata_next[1:0] = loc_alert_class_0_qs; + reg_rdata_next[0] = loc_alert_regwen_19_qs; end addr_hit[166]: begin - reg_rdata_next[1:0] = loc_alert_class_1_qs; + reg_rdata_next[0] = loc_alert_regwen_20_qs; end addr_hit[167]: begin - reg_rdata_next[1:0] = loc_alert_class_2_qs; + reg_rdata_next[0] = loc_alert_regwen_21_qs; end addr_hit[168]: begin - reg_rdata_next[1:0] = loc_alert_class_3_qs; + reg_rdata_next[0] = loc_alert_regwen_22_qs; end addr_hit[169]: begin - reg_rdata_next[0] = loc_alert_cause_0_qs; + reg_rdata_next[0] = loc_alert_regwen_23_qs; end addr_hit[170]: begin - reg_rdata_next[0] = loc_alert_cause_1_qs; + reg_rdata_next[0] = loc_alert_regwen_24_qs; end addr_hit[171]: begin - reg_rdata_next[0] = loc_alert_cause_2_qs; + reg_rdata_next[0] = loc_alert_regwen_25_qs; end addr_hit[172]: begin - reg_rdata_next[0] = loc_alert_cause_3_qs; + reg_rdata_next[0] = loc_alert_regwen_26_qs; end addr_hit[173]: begin - reg_rdata_next[0] = classa_regwen_qs; + reg_rdata_next[0] = loc_alert_regwen_27_qs; end addr_hit[174]: begin + reg_rdata_next[0] = loc_alert_regwen_28_qs; + end + + addr_hit[175]: begin + reg_rdata_next[0] = loc_alert_regwen_29_qs; + end + + addr_hit[176]: begin + reg_rdata_next[0] = loc_alert_regwen_30_qs; + end + + addr_hit[177]: begin + reg_rdata_next[0] = loc_alert_regwen_31_qs; + end + + addr_hit[178]: begin + reg_rdata_next[0] = loc_alert_regwen_32_qs; + end + + addr_hit[179]: begin + reg_rdata_next[0] = loc_alert_regwen_33_qs; + end + + addr_hit[180]: begin + reg_rdata_next[0] = loc_alert_regwen_34_qs; + end + + addr_hit[181]: begin + reg_rdata_next[0] = loc_alert_en_0_qs; + end + + addr_hit[182]: begin + reg_rdata_next[0] = loc_alert_en_1_qs; + end + + addr_hit[183]: begin + reg_rdata_next[0] = loc_alert_en_2_qs; + end + + addr_hit[184]: begin + reg_rdata_next[0] = loc_alert_en_3_qs; + end + + addr_hit[185]: begin + reg_rdata_next[1:0] = loc_alert_class_0_qs; + end + + addr_hit[186]: begin + reg_rdata_next[1:0] = loc_alert_class_1_qs; + end + + addr_hit[187]: begin + reg_rdata_next[1:0] = loc_alert_class_2_qs; + end + + addr_hit[188]: begin + reg_rdata_next[1:0] = loc_alert_class_3_qs; + end + + addr_hit[189]: begin + reg_rdata_next[0] = loc_alert_cause_0_qs; + end + + addr_hit[190]: begin + reg_rdata_next[0] = loc_alert_cause_1_qs; + end + + addr_hit[191]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[192]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[193]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[194]: begin reg_rdata_next[0] = classa_ctrl_en_qs; reg_rdata_next[1] = classa_ctrl_lock_qs; reg_rdata_next[2] = classa_ctrl_en_e0_qs; @@ -9968,55 +10748,55 @@ reg_rdata_next[13:12] = classa_ctrl_map_e3_qs; end - addr_hit[175]: begin + addr_hit[195]: begin reg_rdata_next[0] = classa_clr_regwen_qs; end - addr_hit[176]: begin + addr_hit[196]: begin reg_rdata_next[0] = '0; end - addr_hit[177]: begin + addr_hit[197]: begin reg_rdata_next[15:0] = classa_accum_cnt_qs; end - addr_hit[178]: begin + addr_hit[198]: begin reg_rdata_next[15:0] = classa_accum_thresh_qs; end - addr_hit[179]: begin + addr_hit[199]: begin reg_rdata_next[31:0] = classa_timeout_cyc_qs; end - addr_hit[180]: begin + addr_hit[200]: begin reg_rdata_next[31:0] = classa_phase0_cyc_qs; end - addr_hit[181]: begin + addr_hit[201]: begin reg_rdata_next[31:0] = classa_phase1_cyc_qs; end - addr_hit[182]: begin + addr_hit[202]: begin reg_rdata_next[31:0] = classa_phase2_cyc_qs; end - addr_hit[183]: begin + addr_hit[203]: begin reg_rdata_next[31:0] = classa_phase3_cyc_qs; end - addr_hit[184]: begin + addr_hit[204]: begin reg_rdata_next[31:0] = classa_esc_cnt_qs; end - addr_hit[185]: begin + addr_hit[205]: begin reg_rdata_next[2:0] = classa_state_qs; end - addr_hit[186]: begin + addr_hit[206]: begin reg_rdata_next[0] = classb_regwen_qs; end - addr_hit[187]: begin + addr_hit[207]: begin reg_rdata_next[0] = classb_ctrl_en_qs; reg_rdata_next[1] = classb_ctrl_lock_qs; reg_rdata_next[2] = classb_ctrl_en_e0_qs; @@ -10029,55 +10809,55 @@ reg_rdata_next[13:12] = classb_ctrl_map_e3_qs; end - addr_hit[188]: begin + addr_hit[208]: begin reg_rdata_next[0] = classb_clr_regwen_qs; end - addr_hit[189]: begin + addr_hit[209]: begin reg_rdata_next[0] = '0; end - addr_hit[190]: begin + addr_hit[210]: begin reg_rdata_next[15:0] = classb_accum_cnt_qs; end - addr_hit[191]: begin + addr_hit[211]: begin reg_rdata_next[15:0] = classb_accum_thresh_qs; end - addr_hit[192]: begin + addr_hit[212]: begin reg_rdata_next[31:0] = classb_timeout_cyc_qs; end - addr_hit[193]: begin + addr_hit[213]: begin reg_rdata_next[31:0] = classb_phase0_cyc_qs; end - addr_hit[194]: begin + addr_hit[214]: begin reg_rdata_next[31:0] = classb_phase1_cyc_qs; end - addr_hit[195]: begin + addr_hit[215]: begin reg_rdata_next[31:0] = classb_phase2_cyc_qs; end - addr_hit[196]: begin + addr_hit[216]: begin reg_rdata_next[31:0] = classb_phase3_cyc_qs; end - addr_hit[197]: begin + addr_hit[217]: begin reg_rdata_next[31:0] = classb_esc_cnt_qs; end - addr_hit[198]: begin + addr_hit[218]: begin reg_rdata_next[2:0] = classb_state_qs; end - addr_hit[199]: begin + addr_hit[219]: begin reg_rdata_next[0] = classc_regwen_qs; end - addr_hit[200]: begin + addr_hit[220]: begin reg_rdata_next[0] = classc_ctrl_en_qs; reg_rdata_next[1] = classc_ctrl_lock_qs; reg_rdata_next[2] = classc_ctrl_en_e0_qs; @@ -10090,55 +10870,55 @@ reg_rdata_next[13:12] = classc_ctrl_map_e3_qs; end - addr_hit[201]: begin + addr_hit[221]: begin reg_rdata_next[0] = classc_clr_regwen_qs; end - addr_hit[202]: begin + addr_hit[222]: begin reg_rdata_next[0] = '0; end - addr_hit[203]: begin + addr_hit[223]: begin reg_rdata_next[15:0] = classc_accum_cnt_qs; end - addr_hit[204]: begin + addr_hit[224]: begin reg_rdata_next[15:0] = classc_accum_thresh_qs; end - addr_hit[205]: begin + addr_hit[225]: begin reg_rdata_next[31:0] = classc_timeout_cyc_qs; end - addr_hit[206]: begin + addr_hit[226]: begin reg_rdata_next[31:0] = classc_phase0_cyc_qs; end - addr_hit[207]: begin + addr_hit[227]: begin reg_rdata_next[31:0] = classc_phase1_cyc_qs; end - addr_hit[208]: begin + addr_hit[228]: begin reg_rdata_next[31:0] = classc_phase2_cyc_qs; end - addr_hit[209]: begin + addr_hit[229]: begin reg_rdata_next[31:0] = classc_phase3_cyc_qs; end - addr_hit[210]: begin + addr_hit[230]: begin reg_rdata_next[31:0] = classc_esc_cnt_qs; end - addr_hit[211]: begin + addr_hit[231]: begin reg_rdata_next[2:0] = classc_state_qs; end - addr_hit[212]: begin + addr_hit[232]: begin reg_rdata_next[0] = classd_regwen_qs; end - addr_hit[213]: begin + addr_hit[233]: begin reg_rdata_next[0] = classd_ctrl_en_qs; reg_rdata_next[1] = classd_ctrl_lock_qs; reg_rdata_next[2] = classd_ctrl_en_e0_qs; @@ -10151,47 +10931,47 @@ reg_rdata_next[13:12] = classd_ctrl_map_e3_qs; end - addr_hit[214]: begin + addr_hit[234]: begin reg_rdata_next[0] = classd_clr_regwen_qs; end - addr_hit[215]: begin + addr_hit[235]: begin reg_rdata_next[0] = '0; end - addr_hit[216]: begin + addr_hit[236]: begin reg_rdata_next[15:0] = classd_accum_cnt_qs; end - addr_hit[217]: begin + addr_hit[237]: begin reg_rdata_next[15:0] = classd_accum_thresh_qs; end - addr_hit[218]: begin + addr_hit[238]: begin reg_rdata_next[31:0] = classd_timeout_cyc_qs; end - addr_hit[219]: begin + addr_hit[239]: begin reg_rdata_next[31:0] = classd_phase0_cyc_qs; end - addr_hit[220]: begin + addr_hit[240]: begin reg_rdata_next[31:0] = classd_phase1_cyc_qs; end - addr_hit[221]: begin + addr_hit[241]: begin reg_rdata_next[31:0] = classd_phase2_cyc_qs; end - addr_hit[222]: begin + addr_hit[242]: begin reg_rdata_next[31:0] = classd_phase3_cyc_qs; end - addr_hit[223]: begin + addr_hit[243]: begin reg_rdata_next[31:0] = classd_esc_cnt_qs; end - addr_hit[224]: begin + addr_hit[244]: begin reg_rdata_next[2:0] = classd_state_qs; end
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv index f428fb1..fbe7cbf 100644 --- a/hw/top_earlgrey/ip/ast/rtl/ast.sv +++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -614,8 +614,8 @@ assign ast2padmux_o = {Ast2PadOutWidth{1'b0}}; // `ifndef ANALOGSIM -assign ast2pad_t0_ao = 0.0; -assign ast2pad_t1_ao = 0.1; +assign ast2pad_t0_ao = '0; +assign ast2pad_t1_ao = '0; `else assign ast2pad_t0_ao = 1'bz; assign ast2pad_t1_ao = 1'bz;
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson index 82d3c79..e57e547 100644 --- a/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson +++ b/hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson
@@ -23,7 +23,7 @@ param_list: [ { name: "NumAlerts", type: "int", - default: "7", + default: "11", desc: "Number of alerts", local: "true" }, @@ -33,48 +33,6 @@ desc: "Number of IO rails", local: "true" }, - { name: "AsSel", - type: "int", - default: "0", - desc: "Active shield alert bit position", - local: "true" - } - { name: "CgSel", - type: "int", - default: "1", - desc: "Clock glitch alert bit position", - local: "true" - } - { name: "GdSel", - type: "int", - default: "2", - desc: "Glitch detector alert bit position", - local: "true" - } - { name: "TsHiSel", - type: "int", - default: "3", - desc: "Temperature high alert bit position", - local: "true" - } - { name: "TsLoSel", - type: "int", - default: "4", - desc: "Temperature low alert bit position", - local: "true" - } - { name: "LsSel", - type: "int", - default: "5", - desc: "Laser alert bit position", - local: "true" - } - { name: "OtSel", - type: "int", - default: "6", - desc: "Other alert bit position", - local: "true" - } ], alert_list: [ @@ -93,10 +51,22 @@ { name: "recov_ts_lo", desc: "Triggered through AST", }, - { name: "recov_ls", + { name: "recov_fla", desc: "Triggered through AST", }, - { name: "recov_ot", + { name: "recov_otp", + desc: "Triggered through AST", + }, + { name: "recov_ot0", + desc: "Triggered through AST", + }, + { name: "recov_ot1", + desc: "Triggered through AST", + }, + { name: "recov_ot2", + desc: "Triggered through AST", + }, + { name: "recov_ot3", desc: "Triggered through AST", }, ] @@ -120,6 +90,13 @@ { struct: "logic", type: "uni", + name: "ast_init_done", + act: "rcv", + package: "", + }, + + { struct: "logic", + type: "uni", name: "ast2pinmux", act: "rcv", width: 9, @@ -229,7 +206,14 @@ ''', fields: [ - { bits: "NumIoRails-1:0", + { bits: "0", + name: "ast_init_done", + desc: ''' + AST has finished initializing + ''', + resval: "0", + }, + { bits: "NumIoRails:1", name: "io_pok", desc: ''' IO power is ready
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv index f32b1ad..68a8ef3 100644 --- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv +++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl.sv
@@ -25,6 +25,7 @@ output ast_pkg::ast_alert_rsp_t ast_alert_o, input ast_pkg::ast_status_t ast_status_i, input [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux_i, + input ast_init_done_i, // Interface to pinmux output logic [ast_pkg::Ast2PadOutWidth-1:0] cio_ast_debug_out_o, @@ -36,6 +37,8 @@ ); + // The reg_pkg number of alerts and ast alerts must always match + `ASSERT_INIT(NumAlertsMatch_A, ast_pkg::NumAlerts == NumAlerts) /////////////////////////// // Register interface @@ -54,8 +57,10 @@ .devmode_i(1'b1) ); - assign hw2reg.status.d = ast_status_i.io_pok; - assign hw2reg.status.de = 1'b1; + assign hw2reg.status.io_pok.d = ast_status_i.io_pok; + assign hw2reg.status.io_pok.de = 1'b1; + assign hw2reg.status.ast_init_done.d = ast_init_done_i; + assign hw2reg.status.ast_init_done.de = 1'b1; /////////////////////////// @@ -76,13 +81,28 @@ end // alert test connection - assign alert_test[AsSel] = reg2hw.alert_test.recov_as.qe & reg2hw.alert_test.recov_as.q; - assign alert_test[CgSel] = reg2hw.alert_test.recov_cg.qe & reg2hw.alert_test.recov_cg.q; - assign alert_test[GdSel] = reg2hw.alert_test.recov_gd.qe & reg2hw.alert_test.recov_gd.q; - assign alert_test[TsHiSel] = reg2hw.alert_test.recov_ts_hi.qe & reg2hw.alert_test.recov_ts_hi.q; - assign alert_test[TsLoSel] = reg2hw.alert_test.recov_ts_lo.qe & reg2hw.alert_test.recov_ts_lo.q; - assign alert_test[LsSel] = reg2hw.alert_test.recov_ls.qe & reg2hw.alert_test.recov_ls.q; - assign alert_test[OtSel] = reg2hw.alert_test.recov_ot.qe & reg2hw.alert_test.recov_ot.q; + assign alert_test[ast_pkg::AsSel] = reg2hw.alert_test.recov_as.qe & + reg2hw.alert_test.recov_as.q; + assign alert_test[ast_pkg::CgSel] = reg2hw.alert_test.recov_cg.qe & + reg2hw.alert_test.recov_cg.q; + assign alert_test[ast_pkg::GdSel] = reg2hw.alert_test.recov_gd.qe & + reg2hw.alert_test.recov_gd.q; + assign alert_test[ast_pkg::TsHiSel] = reg2hw.alert_test.recov_ts_hi.qe & + reg2hw.alert_test.recov_ts_hi.q; + assign alert_test[ast_pkg::TsLoSel] = reg2hw.alert_test.recov_ts_lo.qe & + reg2hw.alert_test.recov_ts_lo.q; + assign alert_test[ast_pkg::FlaSel] = reg2hw.alert_test.recov_fla.qe & + reg2hw.alert_test.recov_fla.q; + assign alert_test[ast_pkg::OtpSel] = reg2hw.alert_test.recov_otp.qe & + reg2hw.alert_test.recov_otp.q; + assign alert_test[ast_pkg::Ot0Sel] = reg2hw.alert_test.recov_ot0.qe & + reg2hw.alert_test.recov_ot0.q; + assign alert_test[ast_pkg::Ot1Sel] = reg2hw.alert_test.recov_ot1.qe & + reg2hw.alert_test.recov_ot1.q; + assign alert_test[ast_pkg::Ot2Sel] = reg2hw.alert_test.recov_ot2.qe & + reg2hw.alert_test.recov_ot2.q; + assign alert_test[ast_pkg::Ot3Sel] = reg2hw.alert_test.recov_ot3.qe & + reg2hw.alert_test.recov_ot3.q; // fire an alert whenever indicated
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv index 79cd3a2..4dd9321 100644 --- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv +++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_pkg.sv
@@ -7,15 +7,8 @@ package sensor_ctrl_reg_pkg; // Param list - parameter int NumAlerts = 7; + parameter int NumAlerts = 11; parameter int NumIoRails = 2; - parameter int AsSel = 0; - parameter int CgSel = 1; - parameter int GdSel = 2; - parameter int TsHiSel = 3; - parameter int TsLoSel = 4; - parameter int LsSel = 5; - parameter int OtSel = 6; // Address widths within the block parameter int BlockAw = 5; @@ -48,11 +41,27 @@ struct packed { logic q; logic qe; - } recov_ls; + } recov_fla; struct packed { logic q; logic qe; - } recov_ot; + } recov_otp; + struct packed { + logic q; + logic qe; + } recov_ot0; + struct packed { + logic q; + logic qe; + } recov_ot1; + struct packed { + logic q; + logic qe; + } recov_ot2; + struct packed { + logic q; + logic qe; + } recov_ot3; } sensor_ctrl_reg2hw_alert_test_reg_t; typedef struct packed { @@ -74,22 +83,28 @@ } sensor_ctrl_hw2reg_alert_state_mreg_t; typedef struct packed { - logic [1:0] d; - logic de; + struct packed { + logic d; + logic de; + } ast_init_done; + struct packed { + logic [1:0] d; + logic de; + } io_pok; } sensor_ctrl_hw2reg_status_reg_t; // Register -> HW type typedef struct packed { - sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [48:35] - sensor_ctrl_reg2hw_ack_mode_mreg_t [6:0] ack_mode; // [34:21] - sensor_ctrl_reg2hw_alert_trig_mreg_t [6:0] alert_trig; // [20:14] - sensor_ctrl_reg2hw_alert_state_mreg_t [6:0] alert_state; // [13:0] + sensor_ctrl_reg2hw_alert_test_reg_t alert_test; // [76:55] + sensor_ctrl_reg2hw_ack_mode_mreg_t [10:0] ack_mode; // [54:33] + sensor_ctrl_reg2hw_alert_trig_mreg_t [10:0] alert_trig; // [32:22] + sensor_ctrl_reg2hw_alert_state_mreg_t [10:0] alert_state; // [21:0] } sensor_ctrl_reg2hw_t; // HW -> register type typedef struct packed { - sensor_ctrl_hw2reg_alert_state_mreg_t [6:0] alert_state; // [16:3] - sensor_ctrl_hw2reg_status_reg_t status; // [2:0] + sensor_ctrl_hw2reg_alert_state_mreg_t [10:0] alert_state; // [26:5] + sensor_ctrl_hw2reg_status_reg_t status; // [4:0] } sensor_ctrl_hw2reg_t; // Register offsets @@ -101,14 +116,18 @@ parameter logic [BlockAw-1:0] SENSOR_CTRL_STATUS_OFFSET = 5'h 14; // Reset values for hwext registers and their fields - parameter logic [6:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 7'h 0; + parameter logic [10:0] SENSOR_CTRL_ALERT_TEST_RESVAL = 11'h 0; parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_AS_RESVAL = 1'h 0; parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_CG_RESVAL = 1'h 0; parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_GD_RESVAL = 1'h 0; parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_TS_HI_RESVAL = 1'h 0; parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_TS_LO_RESVAL = 1'h 0; - parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_LS_RESVAL = 1'h 0; - parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT_RESVAL = 1'h 0; + parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_FLA_RESVAL = 1'h 0; + parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OTP_RESVAL = 1'h 0; + parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT0_RESVAL = 1'h 0; + parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT1_RESVAL = 1'h 0; + parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT2_RESVAL = 1'h 0; + parameter logic [0:0] SENSOR_CTRL_ALERT_TEST_RECOV_OT3_RESVAL = 1'h 0; // Register index typedef enum int { @@ -122,11 +141,11 @@ // Register width information to check illegal writes parameter logic [3:0] SENSOR_CTRL_PERMIT [6] = '{ - 4'b 0001, // index[0] SENSOR_CTRL_ALERT_TEST + 4'b 0011, // index[0] SENSOR_CTRL_ALERT_TEST 4'b 0001, // index[1] SENSOR_CTRL_CFG_REGWEN - 4'b 0011, // index[2] SENSOR_CTRL_ACK_MODE - 4'b 0001, // index[3] SENSOR_CTRL_ALERT_TRIG - 4'b 0001, // index[4] SENSOR_CTRL_ALERT_STATE + 4'b 0111, // index[2] SENSOR_CTRL_ACK_MODE + 4'b 0011, // index[3] SENSOR_CTRL_ALERT_TRIG + 4'b 0011, // index[4] SENSOR_CTRL_ALERT_STATE 4'b 0001 // index[5] SENSOR_CTRL_STATUS };
diff --git a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv index ade2435..8716401 100644 --- a/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv +++ b/hw/top_earlgrey/ip/sensor_ctrl/rtl/sensor_ctrl_reg_top.sv
@@ -114,10 +114,18 @@ logic alert_test_recov_ts_hi_we; logic alert_test_recov_ts_lo_wd; logic alert_test_recov_ts_lo_we; - logic alert_test_recov_ls_wd; - logic alert_test_recov_ls_we; - logic alert_test_recov_ot_wd; - logic alert_test_recov_ot_we; + logic alert_test_recov_fla_wd; + logic alert_test_recov_fla_we; + logic alert_test_recov_otp_wd; + logic alert_test_recov_otp_we; + logic alert_test_recov_ot0_wd; + logic alert_test_recov_ot0_we; + logic alert_test_recov_ot1_wd; + logic alert_test_recov_ot1_we; + logic alert_test_recov_ot2_wd; + logic alert_test_recov_ot2_we; + logic alert_test_recov_ot3_wd; + logic alert_test_recov_ot3_we; logic cfg_regwen_qs; logic cfg_regwen_wd; logic cfg_regwen_we; @@ -142,6 +150,18 @@ logic [1:0] ack_mode_val_6_qs; logic [1:0] ack_mode_val_6_wd; logic ack_mode_val_6_we; + logic [1:0] ack_mode_val_7_qs; + logic [1:0] ack_mode_val_7_wd; + logic ack_mode_val_7_we; + logic [1:0] ack_mode_val_8_qs; + logic [1:0] ack_mode_val_8_wd; + logic ack_mode_val_8_we; + logic [1:0] ack_mode_val_9_qs; + logic [1:0] ack_mode_val_9_wd; + logic ack_mode_val_9_we; + logic [1:0] ack_mode_val_10_qs; + logic [1:0] ack_mode_val_10_wd; + logic ack_mode_val_10_we; logic alert_trig_val_0_qs; logic alert_trig_val_0_wd; logic alert_trig_val_0_we; @@ -163,6 +183,18 @@ logic alert_trig_val_6_qs; logic alert_trig_val_6_wd; logic alert_trig_val_6_we; + logic alert_trig_val_7_qs; + logic alert_trig_val_7_wd; + logic alert_trig_val_7_we; + logic alert_trig_val_8_qs; + logic alert_trig_val_8_wd; + logic alert_trig_val_8_we; + logic alert_trig_val_9_qs; + logic alert_trig_val_9_wd; + logic alert_trig_val_9_we; + logic alert_trig_val_10_qs; + logic alert_trig_val_10_wd; + logic alert_trig_val_10_we; logic alert_state_val_0_qs; logic alert_state_val_0_wd; logic alert_state_val_0_we; @@ -184,7 +216,20 @@ logic alert_state_val_6_qs; logic alert_state_val_6_wd; logic alert_state_val_6_we; - logic [1:0] status_qs; + logic alert_state_val_7_qs; + logic alert_state_val_7_wd; + logic alert_state_val_7_we; + logic alert_state_val_8_qs; + logic alert_state_val_8_wd; + logic alert_state_val_8_we; + logic alert_state_val_9_qs; + logic alert_state_val_9_wd; + logic alert_state_val_9_we; + logic alert_state_val_10_qs; + logic alert_state_val_10_wd; + logic alert_state_val_10_we; + logic status_ast_init_done_qs; + logic [1:0] status_io_pok_qs; // Register instances // R[alert_test]: V(True) @@ -264,32 +309,92 @@ ); - // F[recov_ls]: 5:5 + // F[recov_fla]: 5:5 prim_subreg_ext #( .DW (1) - ) u_alert_test_recov_ls ( + ) u_alert_test_recov_fla ( .re (1'b0), - .we (alert_test_recov_ls_we), - .wd (alert_test_recov_ls_wd), + .we (alert_test_recov_fla_we), + .wd (alert_test_recov_fla_wd), .d ('0), .qre (), - .qe (reg2hw.alert_test.recov_ls.qe), - .q (reg2hw.alert_test.recov_ls.q ), + .qe (reg2hw.alert_test.recov_fla.qe), + .q (reg2hw.alert_test.recov_fla.q ), .qs () ); - // F[recov_ot]: 6:6 + // F[recov_otp]: 6:6 prim_subreg_ext #( .DW (1) - ) u_alert_test_recov_ot ( + ) u_alert_test_recov_otp ( .re (1'b0), - .we (alert_test_recov_ot_we), - .wd (alert_test_recov_ot_wd), + .we (alert_test_recov_otp_we), + .wd (alert_test_recov_otp_wd), .d ('0), .qre (), - .qe (reg2hw.alert_test.recov_ot.qe), - .q (reg2hw.alert_test.recov_ot.q ), + .qe (reg2hw.alert_test.recov_otp.qe), + .q (reg2hw.alert_test.recov_otp.q ), + .qs () + ); + + + // F[recov_ot0]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_ot0 ( + .re (1'b0), + .we (alert_test_recov_ot0_we), + .wd (alert_test_recov_ot0_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.recov_ot0.qe), + .q (reg2hw.alert_test.recov_ot0.q ), + .qs () + ); + + + // F[recov_ot1]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_ot1 ( + .re (1'b0), + .we (alert_test_recov_ot1_we), + .wd (alert_test_recov_ot1_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.recov_ot1.qe), + .q (reg2hw.alert_test.recov_ot1.q ), + .qs () + ); + + + // F[recov_ot2]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_ot2 ( + .re (1'b0), + .we (alert_test_recov_ot2_we), + .wd (alert_test_recov_ot2_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.recov_ot2.qe), + .q (reg2hw.alert_test.recov_ot2.q ), + .qs () + ); + + + // F[recov_ot3]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_ot3 ( + .re (1'b0), + .we (alert_test_recov_ot3_we), + .wd (alert_test_recov_ot3_wd), + .d ('0), + .qre (), + .qe (reg2hw.alert_test.recov_ot3.qe), + .q (reg2hw.alert_test.recov_ot3.q ), .qs () ); @@ -507,6 +612,110 @@ ); + // F[val_7]: 15:14 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_ack_mode_val_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (ack_mode_val_7_we & cfg_regwen_qs), + .wd (ack_mode_val_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ack_mode[7].q ), + + // to register interface (read) + .qs (ack_mode_val_7_qs) + ); + + + // F[val_8]: 17:16 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_ack_mode_val_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (ack_mode_val_8_we & cfg_regwen_qs), + .wd (ack_mode_val_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ack_mode[8].q ), + + // to register interface (read) + .qs (ack_mode_val_8_qs) + ); + + + // F[val_9]: 19:18 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_ack_mode_val_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (ack_mode_val_9_we & cfg_regwen_qs), + .wd (ack_mode_val_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ack_mode[9].q ), + + // to register interface (read) + .qs (ack_mode_val_9_qs) + ); + + + // F[val_10]: 21:20 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_ack_mode_val_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface (qualified with register enable) + .we (ack_mode_val_10_we & cfg_regwen_qs), + .wd (ack_mode_val_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.ack_mode[10].q ), + + // to register interface (read) + .qs (ack_mode_val_10_qs) + ); + + // Subregister 0 of Multireg alert_trig @@ -694,6 +903,110 @@ ); + // F[val_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_trig_val_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_trig_val_7_we), + .wd (alert_trig_val_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_trig[7].q ), + + // to register interface (read) + .qs (alert_trig_val_7_qs) + ); + + + // F[val_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_trig_val_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_trig_val_8_we), + .wd (alert_trig_val_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_trig[8].q ), + + // to register interface (read) + .qs (alert_trig_val_8_qs) + ); + + + // F[val_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_trig_val_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_trig_val_9_we), + .wd (alert_trig_val_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_trig[9].q ), + + // to register interface (read) + .qs (alert_trig_val_9_qs) + ); + + + // F[val_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_alert_trig_val_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_trig_val_10_we), + .wd (alert_trig_val_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.alert_trig[10].q ), + + // to register interface (read) + .qs (alert_trig_val_10_qs) + ); + + // Subregister 0 of Multireg alert_state @@ -881,14 +1194,119 @@ ); + // F[val_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_state_val_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_state_val_7_we), + .wd (alert_state_val_7_wd), + + // from internal hardware + .de (hw2reg.alert_state[7].de), + .d (hw2reg.alert_state[7].d ), + + // to internal hardware + .qe (reg2hw.alert_state[7].qe), + .q (reg2hw.alert_state[7].q ), + + // to register interface (read) + .qs (alert_state_val_7_qs) + ); + + + // F[val_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_state_val_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_state_val_8_we), + .wd (alert_state_val_8_wd), + + // from internal hardware + .de (hw2reg.alert_state[8].de), + .d (hw2reg.alert_state[8].d ), + + // to internal hardware + .qe (reg2hw.alert_state[8].qe), + .q (reg2hw.alert_state[8].q ), + + // to register interface (read) + .qs (alert_state_val_8_qs) + ); + + + // F[val_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_state_val_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_state_val_9_we), + .wd (alert_state_val_9_wd), + + // from internal hardware + .de (hw2reg.alert_state[9].de), + .d (hw2reg.alert_state[9].d ), + + // to internal hardware + .qe (reg2hw.alert_state[9].qe), + .q (reg2hw.alert_state[9].q ), + + // to register interface (read) + .qs (alert_state_val_9_qs) + ); + + + // F[val_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_alert_state_val_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (alert_state_val_10_we), + .wd (alert_state_val_10_wd), + + // from internal hardware + .de (hw2reg.alert_state[10].de), + .d (hw2reg.alert_state[10].d ), + + // to internal hardware + .qe (reg2hw.alert_state[10].qe), + .q (reg2hw.alert_state[10].q ), + + // to register interface (read) + .qs (alert_state_val_10_qs) + ); + + // R[status]: V(False) + // F[ast_init_done]: 0:0 prim_subreg #( - .DW (2), + .DW (1), .SWACCESS("RO"), - .RESVAL (2'h3) - ) u_status ( + .RESVAL (1'h0) + ) u_status_ast_init_done ( .clk_i (clk_i ), .rst_ni (rst_ni ), @@ -896,15 +1314,40 @@ .wd ('0 ), // from internal hardware - .de (hw2reg.status.de), - .d (hw2reg.status.d ), + .de (hw2reg.status.ast_init_done.de), + .d (hw2reg.status.ast_init_done.d ), // to internal hardware .qe (), .q (), // to register interface (read) - .qs (status_qs) + .qs (status_ast_init_done_qs) + ); + + + // F[io_pok]: 2:1 + prim_subreg #( + .DW (2), + .SWACCESS("RO"), + .RESVAL (2'h3) + ) u_status_io_pok ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (hw2reg.status.io_pok.de), + .d (hw2reg.status.io_pok.d ), + + // to internal hardware + .qe (), + .q (), + + // to register interface (read) + .qs (status_io_pok_qs) ); @@ -949,11 +1392,23 @@ assign alert_test_recov_ts_lo_we = addr_hit[0] & reg_we & !reg_error; assign alert_test_recov_ts_lo_wd = reg_wdata[4]; - assign alert_test_recov_ls_we = addr_hit[0] & reg_we & !reg_error; - assign alert_test_recov_ls_wd = reg_wdata[5]; + assign alert_test_recov_fla_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_recov_fla_wd = reg_wdata[5]; - assign alert_test_recov_ot_we = addr_hit[0] & reg_we & !reg_error; - assign alert_test_recov_ot_wd = reg_wdata[6]; + assign alert_test_recov_otp_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_recov_otp_wd = reg_wdata[6]; + + assign alert_test_recov_ot0_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_recov_ot0_wd = reg_wdata[7]; + + assign alert_test_recov_ot1_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_recov_ot1_wd = reg_wdata[8]; + + assign alert_test_recov_ot2_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_recov_ot2_wd = reg_wdata[9]; + + assign alert_test_recov_ot3_we = addr_hit[0] & reg_we & !reg_error; + assign alert_test_recov_ot3_wd = reg_wdata[10]; assign cfg_regwen_we = addr_hit[1] & reg_we & !reg_error; assign cfg_regwen_wd = reg_wdata[0]; @@ -979,6 +1434,18 @@ assign ack_mode_val_6_we = addr_hit[2] & reg_we & !reg_error; assign ack_mode_val_6_wd = reg_wdata[13:12]; + assign ack_mode_val_7_we = addr_hit[2] & reg_we & !reg_error; + assign ack_mode_val_7_wd = reg_wdata[15:14]; + + assign ack_mode_val_8_we = addr_hit[2] & reg_we & !reg_error; + assign ack_mode_val_8_wd = reg_wdata[17:16]; + + assign ack_mode_val_9_we = addr_hit[2] & reg_we & !reg_error; + assign ack_mode_val_9_wd = reg_wdata[19:18]; + + assign ack_mode_val_10_we = addr_hit[2] & reg_we & !reg_error; + assign ack_mode_val_10_wd = reg_wdata[21:20]; + assign alert_trig_val_0_we = addr_hit[3] & reg_we & !reg_error; assign alert_trig_val_0_wd = reg_wdata[0]; @@ -1000,6 +1467,18 @@ assign alert_trig_val_6_we = addr_hit[3] & reg_we & !reg_error; assign alert_trig_val_6_wd = reg_wdata[6]; + assign alert_trig_val_7_we = addr_hit[3] & reg_we & !reg_error; + assign alert_trig_val_7_wd = reg_wdata[7]; + + assign alert_trig_val_8_we = addr_hit[3] & reg_we & !reg_error; + assign alert_trig_val_8_wd = reg_wdata[8]; + + assign alert_trig_val_9_we = addr_hit[3] & reg_we & !reg_error; + assign alert_trig_val_9_wd = reg_wdata[9]; + + assign alert_trig_val_10_we = addr_hit[3] & reg_we & !reg_error; + assign alert_trig_val_10_wd = reg_wdata[10]; + assign alert_state_val_0_we = addr_hit[4] & reg_we & !reg_error; assign alert_state_val_0_wd = reg_wdata[0]; @@ -1021,6 +1500,18 @@ assign alert_state_val_6_we = addr_hit[4] & reg_we & !reg_error; assign alert_state_val_6_wd = reg_wdata[6]; + assign alert_state_val_7_we = addr_hit[4] & reg_we & !reg_error; + assign alert_state_val_7_wd = reg_wdata[7]; + + assign alert_state_val_8_we = addr_hit[4] & reg_we & !reg_error; + assign alert_state_val_8_wd = reg_wdata[8]; + + assign alert_state_val_9_we = addr_hit[4] & reg_we & !reg_error; + assign alert_state_val_9_wd = reg_wdata[9]; + + assign alert_state_val_10_we = addr_hit[4] & reg_we & !reg_error; + assign alert_state_val_10_wd = reg_wdata[10]; + // Read data return always_comb begin reg_rdata_next = '0; @@ -1033,6 +1524,10 @@ reg_rdata_next[4] = '0; reg_rdata_next[5] = '0; reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; end addr_hit[1]: begin @@ -1047,6 +1542,10 @@ reg_rdata_next[9:8] = ack_mode_val_4_qs; reg_rdata_next[11:10] = ack_mode_val_5_qs; reg_rdata_next[13:12] = ack_mode_val_6_qs; + reg_rdata_next[15:14] = ack_mode_val_7_qs; + reg_rdata_next[17:16] = ack_mode_val_8_qs; + reg_rdata_next[19:18] = ack_mode_val_9_qs; + reg_rdata_next[21:20] = ack_mode_val_10_qs; end addr_hit[3]: begin @@ -1057,6 +1556,10 @@ reg_rdata_next[4] = alert_trig_val_4_qs; reg_rdata_next[5] = alert_trig_val_5_qs; reg_rdata_next[6] = alert_trig_val_6_qs; + reg_rdata_next[7] = alert_trig_val_7_qs; + reg_rdata_next[8] = alert_trig_val_8_qs; + reg_rdata_next[9] = alert_trig_val_9_qs; + reg_rdata_next[10] = alert_trig_val_10_qs; end addr_hit[4]: begin @@ -1067,10 +1570,15 @@ reg_rdata_next[4] = alert_state_val_4_qs; reg_rdata_next[5] = alert_state_val_5_qs; reg_rdata_next[6] = alert_state_val_6_qs; + reg_rdata_next[7] = alert_state_val_7_qs; + reg_rdata_next[8] = alert_state_val_8_qs; + reg_rdata_next[9] = alert_state_val_9_qs; + reg_rdata_next[10] = alert_state_val_10_qs; end addr_hit[5]: begin - reg_rdata_next[1:0] = status_qs; + reg_rdata_next[0] = status_ast_init_done_qs; + reg_rdata_next[2:1] = status_io_pok_qs; end default: begin
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv index 8425a3f..7711e6f 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -867,15 +867,6 @@ // Jitter enable logic jen; - // Alert connections - import sensor_ctrl_reg_pkg::AsSel; - import sensor_ctrl_reg_pkg::CgSel; - import sensor_ctrl_reg_pkg::GdSel; - import sensor_ctrl_reg_pkg::TsHiSel; - import sensor_ctrl_reg_pkg::TsLoSel; - import sensor_ctrl_reg_pkg::LsSel; - import sensor_ctrl_reg_pkg::OtSel; - // reset domain connections import rstmgr_pkg::PowerDomains; import rstmgr_pkg::DomainAonSel; @@ -961,16 +952,14 @@ assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel]; assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel]; -// TODO Connet to FLASH & OTP -ast_pkg::ast_dif_t fla_alert_in_i; -ast_pkg::ast_dif_t otp_alert_in_i; -assign fla_alert_in_i = '{p: 1'b0, n: 1'b1}; -assign otp_alert_in_i = '{p: 1'b0, n: 1'b1}; + ast_pkg::ast_dif_t flash_alert; + ast_pkg::ast_dif_t otp_alert; + logic ast_init_done; ast #( - .EntropyStreams(top_pkg::ENTROPY_STREAM), - .AdcChannels(top_pkg::ADC_CHANNELS), - .AdcDataWidth(top_pkg::ADC_DATAW), + .EntropyStreams(ast_pkg::EntropyStreams), + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), .UsbCalibWidth(ast_pkg::UsbCalibWidth), .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) @@ -978,7 +967,8 @@ // tlul .tl_i ( base_ast_bus ), .tl_o ( ast_base_bus ), - .ast_init_done_o ( ), // TODO Connect to? + // init done indication + .ast_init_done_o ( ast_init_done ), // buffered clocks & resets // Reset domain connection is manual at the moment .clk_ast_adc_i ( clks_ast.clk_ast_adc_ctrl_aon_io_div4_peri ), @@ -1051,10 +1041,10 @@ .entropy_rsp_i ( ast_edn_edn_rsp ), .entropy_req_o ( ast_edn_edn_req ), // alerts - .fla_alert_in_i ( fla_alert_in_i ), - .otp_alert_in_i ( otp_alert_in_i ), - .alert_rsp_i ( ast_alert_rsp ), - .alert_req_o ( ast_alert_req ), + .fla_alert_in_i ( flash_alert ), + .otp_alert_in_i ( otp_alert ), + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), // dft .dft_strap_test_i ( dft_strap_test ), .lc_dft_en_i ( dft_en ), @@ -1121,15 +1111,18 @@ .ast_edn_rsp_o ( ast_edn_edn_rsp ), .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), + .otp_alert_o ( otp_alert ), .flash_bist_enable_i ( flash_bist_enable ), .flash_power_down_h_i ( flash_power_down_h ), .flash_power_ready_h_i ( flash_power_ready_h ), + .flash_alert_o ( flash_alert ), .es_rng_req_o ( es_rng_req ), .es_rng_rsp_i ( es_rng_rsp ), .es_rng_fips_o ( es_rng_fips ), .ast_clk_byp_req_o ( ast_clk_byp_req ), .ast_clk_byp_ack_i ( ast_clk_byp_ack ), .ast2pinmux_i ( ast2pinmux ), + .ast_init_done_i ( ast_init_done ), // Flash test mode voltages .flash_test_mode_a_io ( {FLASH_TEST_MODE1,
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv index 96bf208..8ae70cc 100644 --- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv +++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -755,6 +755,7 @@ .ast_tl_rsp_i ( '0 ), .otp_ctrl_otp_ast_pwr_seq_o ( ), .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ), + .otp_alert_o ( ), .es_rng_req_o ( ), .es_rng_rsp_i ( '0 ), .es_rng_fips_o ( ),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index a530f3d..38d3422 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -68,6 +68,7 @@ output logic clk_main_jitter_en_o, output lc_ctrl_pkg::lc_tx_t ast_clk_byp_req_o, input lc_ctrl_pkg::lc_tx_t ast_clk_byp_ack_i, + output ast_pkg::ast_dif_t flash_alert_o, input lc_ctrl_pkg::lc_tx_t flash_bist_enable_i, input logic flash_power_down_h_i, input logic flash_power_ready_h_i, @@ -82,10 +83,12 @@ input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i, output otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq_o, input otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h_i, + output ast_pkg::ast_dif_t otp_alert_o, input ast_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i, output ast_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o, input ast_pkg::ast_status_t sensor_ctrl_ast_status_i, input logic [8:0] ast2pinmux_i, + input logic ast_init_done_i, output logic usbdev_usb_ref_val_o, output logic usbdev_usb_ref_pulse_o, output clkmgr_pkg::clkmgr_ast_out_t clks_ast_o, @@ -1016,6 +1019,7 @@ .flash_power_ready_h_i, .flash_test_mode_a_io, .flash_test_voltage_h_io, + .flash_alert_o, .scanmode_i, .scan_en_i, .scan_rst_ni @@ -1494,6 +1498,7 @@ // Inter-module signals .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o), .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i), + .otp_alert_o(otp_alert_o), .edn_o(edn0_edn_req[1]), .edn_i(edn0_edn_rsp[1]), .pwr_otp_i(pwrmgr_aon_pwr_otp_req), @@ -1857,7 +1862,7 @@ ); sensor_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:4]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[14:4]) ) u_sensor_ctrl_aon ( // Output @@ -1868,15 +1873,20 @@ // [6]: recov_gd // [7]: recov_ts_hi // [8]: recov_ts_lo - // [9]: recov_ls - // [10]: recov_ot - .alert_tx_o ( alert_tx[10:4] ), - .alert_rx_i ( alert_rx[10:4] ), + // [9]: recov_fla + // [10]: recov_otp + // [11]: recov_ot0 + // [12]: recov_ot1 + // [13]: recov_ot2 + // [14]: recov_ot3 + .alert_tx_o ( alert_tx[14:4] ), + .alert_rx_i ( alert_rx[14:4] ), // Inter-module signals .ast_alert_i(sensor_ctrl_ast_alert_req_i), .ast_alert_o(sensor_ctrl_ast_alert_rsp_o), .ast_status_i(sensor_ctrl_ast_status_i), + .ast_init_done_i(ast_init_done_i), .ast2pinmux_i(ast2pinmux_i), .tl_i(sensor_ctrl_aon_tl_req), .tl_o(sensor_ctrl_aon_tl_rsp), @@ -1887,16 +1897,16 @@ ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[12:11]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:15]), .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey), .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce), .RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm), .InstrExec(SramCtrlRetAonInstrExec) ) u_sram_ctrl_ret_aon ( - // [11]: fatal_intg_error - // [12]: fatal_parity_error - .alert_tx_o ( alert_tx[12:11] ), - .alert_rx_i ( alert_rx[12:11] ), + // [15]: fatal_intg_error + // [16]: fatal_parity_error + .alert_tx_o ( alert_tx[16:15] ), + .alert_rx_i ( alert_rx[16:15] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), @@ -1921,7 +1931,7 @@ ); flash_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[16:13]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:17]), .RndCnstAddrKey(RndCnstFlashCtrlAddrKey), .RndCnstDataKey(RndCnstFlashCtrlDataKey), .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed), @@ -1944,12 +1954,12 @@ .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl), .intr_op_done_o (intr_flash_ctrl_op_done), .intr_err_o (intr_flash_ctrl_err), - // [13]: recov_err - // [14]: recov_mp_err - // [15]: recov_ecc_err - // [16]: fatal_intg_err - .alert_tx_o ( alert_tx[16:13] ), - .alert_rx_i ( alert_rx[16:13] ), + // [17]: recov_err + // [18]: recov_mp_err + // [19]: recov_ecc_err + // [20]: fatal_intg_err + .alert_tx_o ( alert_tx[20:17] ), + .alert_rx_i ( alert_rx[20:17] ), // Inter-module signals .flash_o(flash_ctrl_flash_req), @@ -1995,7 +2005,7 @@ ); aes #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:17]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:21]), .AES192Enable(1'b1), .Masking(AesMasking), .SBoxImpl(AesSBoxImpl), @@ -2008,10 +2018,10 @@ .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), .RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm) ) u_aes ( - // [17]: recov_ctrl_update_err - // [18]: fatal_fault - .alert_tx_o ( alert_tx[18:17] ), - .alert_rx_i ( alert_rx[18:17] ), + // [21]: recov_ctrl_update_err + // [22]: fatal_fault + .alert_tx_o ( alert_tx[22:21] ), + .alert_rx_i ( alert_rx[22:21] ), // Inter-module signals .idle_o(clkmgr_aon_idle[0]), @@ -2073,7 +2083,7 @@ ); keymgr #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:19]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]), .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed), .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm), .RndCnstRandPerm(RndCnstKeymgrRandPerm), @@ -2091,10 +2101,10 @@ // Interrupt .intr_op_done_o (intr_keymgr_op_done), - // [19]: fatal_fault_err - // [20]: recov_operation_err - .alert_tx_o ( alert_tx[20:19] ), - .alert_rx_i ( alert_rx[20:19] ), + // [23]: fatal_fault_err + // [24]: recov_operation_err + .alert_tx_o ( alert_tx[24:23] ), + .alert_rx_i ( alert_rx[24:23] ), // Inter-module signals .edn_o(edn0_edn_req[0]), @@ -2121,7 +2131,7 @@ ); csrng #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:25]), .SBoxImpl(CsrngSBoxImpl) ) u_csrng ( @@ -2130,9 +2140,9 @@ .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), - // [21]: fatal_alert - .alert_tx_o ( alert_tx[21:21] ), - .alert_rx_i ( alert_rx[21:21] ), + // [25]: fatal_alert + .alert_tx_o ( alert_tx[25:25] ), + .alert_rx_i ( alert_rx[25:25] ), // Inter-module signals .csrng_cmd_i(csrng_csrng_cmd_req), @@ -2152,7 +2162,7 @@ ); entropy_src #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:22]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:26]), .Stub(EntropySrcStub) ) u_entropy_src ( @@ -2160,10 +2170,10 @@ .intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid), .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), - // [22]: recov_alert - // [23]: fatal_alert - .alert_tx_o ( alert_tx[23:22] ), - .alert_rx_i ( alert_rx[23:22] ), + // [26]: recov_alert + // [27]: fatal_alert + .alert_tx_o ( alert_tx[27:26] ), + .alert_rx_i ( alert_rx[27:26] ), // Inter-module signals .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), @@ -2185,15 +2195,15 @@ ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:24]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28]) ) u_edn0 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), - // [24]: fatal_alert - .alert_tx_o ( alert_tx[24:24] ), - .alert_rx_i ( alert_rx[24:24] ), + // [28]: fatal_alert + .alert_tx_o ( alert_tx[28:28] ), + .alert_rx_i ( alert_rx[28:28] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[0]), @@ -2209,15 +2219,15 @@ ); edn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:25]) + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29]) ) u_edn1 ( // Interrupt .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), - // [25]: fatal_alert - .alert_tx_o ( alert_tx[25:25] ), - .alert_rx_i ( alert_rx[25:25] ), + // [29]: fatal_alert + .alert_tx_o ( alert_tx[29:29] ), + .alert_rx_i ( alert_rx[29:29] ), // Inter-module signals .csrng_cmd_o(csrng_csrng_cmd_req[1]), @@ -2233,16 +2243,16 @@ ); sram_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:26]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:30]), .RndCnstSramKey(RndCnstSramCtrlMainSramKey), .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), .RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm), .InstrExec(SramCtrlMainInstrExec) ) u_sram_ctrl_main ( - // [26]: fatal_intg_error - // [27]: fatal_parity_error - .alert_tx_o ( alert_tx[27:26] ), - .alert_rx_i ( alert_rx[27:26] ), + // [30]: fatal_intg_error + // [31]: fatal_parity_error + .alert_tx_o ( alert_tx[31:30] ), + .alert_rx_i ( alert_rx[31:30] ), // Inter-module signals .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), @@ -2267,7 +2277,7 @@ ); otbn #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]), .Stub(OtbnStub), .RegFile(OtbnRegFile), .RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed), @@ -2276,10 +2286,10 @@ // Interrupt .intr_done_o (intr_otbn_done), - // [28]: fatal - // [29]: recov - .alert_tx_o ( alert_tx[29:28] ), - .alert_rx_i ( alert_rx[29:28] ), + // [32]: fatal + // [33]: recov + .alert_tx_o ( alert_tx[33:32] ), + .alert_rx_i ( alert_rx[33:32] ), // Inter-module signals .edn_rnd_o(edn1_edn_req[0]), @@ -2299,15 +2309,15 @@ ); rom_ctrl #( - .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]), .BootRomInitFile(RomCtrlBootRomInitFile), .RndCnstScrNonce(RndCnstRomCtrlScrNonce), .RndCnstScrKey(RndCnstRomCtrlScrKey), .SkipCheck(RomCtrlSkipCheck) ) u_rom_ctrl ( - // [30]: fatal - .alert_tx_o ( alert_tx[30:30] ), - .alert_rx_i ( alert_rx[30:30] ), + // [34]: fatal + .alert_tx_o ( alert_tx[34:34] ), + .alert_rx_i ( alert_rx[34:34] ), // Inter-module signals .rom_cfg_i(ast_rom_cfg),
diff --git a/hw/top_earlgrey/rtl/top_pkg.sv b/hw/top_earlgrey/rtl/top_pkg.sv index 98e902d..91ea430 100644 --- a/hw/top_earlgrey/rtl/top_pkg.sv +++ b/hw/top_earlgrey/rtl/top_pkg.sv
@@ -13,10 +13,4 @@ localparam int TL_DUW=14; // d_user localparam int TL_DBW=(TL_DW>>3); localparam int TL_SZW=$clog2($clog2(TL_DBW)+1); -localparam int NUM_AST_ALERTS=7; -localparam int NUM_IO_RAILS=2; -localparam int ENTROPY_STREAM=4; -localparam int ADC_CHANNELS=2; -localparam int ADC_DATAW=10; - endpackage
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c index f58a052..61e2ae5 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -201,7 +201,7 @@ * `top_earlgrey_alert_peripheral_t`. */ const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[31] = { + top_earlgrey_alert_for_peripheral[35] = { [kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl, [kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl, [kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl, @@ -211,8 +211,12 @@ [kTopEarlgreyAlertIdSensorCtrlAonRecovGd] = kTopEarlgreyAlertPeripheralSensorCtrlAon, [kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi] = kTopEarlgreyAlertPeripheralSensorCtrlAon, [kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo] = kTopEarlgreyAlertPeripheralSensorCtrlAon, - [kTopEarlgreyAlertIdSensorCtrlAonRecovLs] = kTopEarlgreyAlertPeripheralSensorCtrlAon, - [kTopEarlgreyAlertIdSensorCtrlAonRecovOt] = kTopEarlgreyAlertPeripheralSensorCtrlAon, + [kTopEarlgreyAlertIdSensorCtrlAonRecovFla] = kTopEarlgreyAlertPeripheralSensorCtrlAon, + [kTopEarlgreyAlertIdSensorCtrlAonRecovOtp] = kTopEarlgreyAlertPeripheralSensorCtrlAon, + [kTopEarlgreyAlertIdSensorCtrlAonRecovOt0] = kTopEarlgreyAlertPeripheralSensorCtrlAon, + [kTopEarlgreyAlertIdSensorCtrlAonRecovOt1] = kTopEarlgreyAlertPeripheralSensorCtrlAon, + [kTopEarlgreyAlertIdSensorCtrlAonRecovOt2] = kTopEarlgreyAlertPeripheralSensorCtrlAon, + [kTopEarlgreyAlertIdSensorCtrlAonRecovOt3] = kTopEarlgreyAlertPeripheralSensorCtrlAon, [kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon, [kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon, [kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index f61a6c5..d24be99 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1120,29 +1120,33 @@ kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 6, /**< sensor_ctrl_aon_recov_gd */ kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 7, /**< sensor_ctrl_aon_recov_ts_hi */ kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 8, /**< sensor_ctrl_aon_recov_ts_lo */ - kTopEarlgreyAlertIdSensorCtrlAonRecovLs = 9, /**< sensor_ctrl_aon_recov_ls */ - kTopEarlgreyAlertIdSensorCtrlAonRecovOt = 10, /**< sensor_ctrl_aon_recov_ot */ - kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 11, /**< sram_ctrl_ret_aon_fatal_intg_error */ - kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 12, /**< sram_ctrl_ret_aon_fatal_parity_error */ - kTopEarlgreyAlertIdFlashCtrlRecovErr = 13, /**< flash_ctrl_recov_err */ - kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 14, /**< flash_ctrl_recov_mp_err */ - kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 15, /**< flash_ctrl_recov_ecc_err */ - kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 16, /**< flash_ctrl_fatal_intg_err */ - kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 17, /**< aes_recov_ctrl_update_err */ - kTopEarlgreyAlertIdAesFatalFault = 18, /**< aes_fatal_fault */ - kTopEarlgreyAlertIdKeymgrFatalFaultErr = 19, /**< keymgr_fatal_fault_err */ - kTopEarlgreyAlertIdKeymgrRecovOperationErr = 20, /**< keymgr_recov_operation_err */ - kTopEarlgreyAlertIdCsrngFatalAlert = 21, /**< csrng_fatal_alert */ - kTopEarlgreyAlertIdEntropySrcRecovAlert = 22, /**< entropy_src_recov_alert */ - kTopEarlgreyAlertIdEntropySrcFatalAlert = 23, /**< entropy_src_fatal_alert */ - kTopEarlgreyAlertIdEdn0FatalAlert = 24, /**< edn0_fatal_alert */ - kTopEarlgreyAlertIdEdn1FatalAlert = 25, /**< edn1_fatal_alert */ - kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 26, /**< sram_ctrl_main_fatal_intg_error */ - kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 27, /**< sram_ctrl_main_fatal_parity_error */ - kTopEarlgreyAlertIdOtbnFatal = 28, /**< otbn_fatal */ - kTopEarlgreyAlertIdOtbnRecov = 29, /**< otbn_recov */ - kTopEarlgreyAlertIdRomCtrlFatal = 30, /**< rom_ctrl_fatal */ - kTopEarlgreyAlertIdLast = 30, /**< \internal The Last Valid Alert ID. */ + kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 9, /**< sensor_ctrl_aon_recov_fla */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 10, /**< sensor_ctrl_aon_recov_otp */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 11, /**< sensor_ctrl_aon_recov_ot0 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 12, /**< sensor_ctrl_aon_recov_ot1 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 13, /**< sensor_ctrl_aon_recov_ot2 */ + kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 14, /**< sensor_ctrl_aon_recov_ot3 */ + kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 15, /**< sram_ctrl_ret_aon_fatal_intg_error */ + kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 16, /**< sram_ctrl_ret_aon_fatal_parity_error */ + kTopEarlgreyAlertIdFlashCtrlRecovErr = 17, /**< flash_ctrl_recov_err */ + kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 18, /**< flash_ctrl_recov_mp_err */ + kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 19, /**< flash_ctrl_recov_ecc_err */ + kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 20, /**< flash_ctrl_fatal_intg_err */ + kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 21, /**< aes_recov_ctrl_update_err */ + kTopEarlgreyAlertIdAesFatalFault = 22, /**< aes_fatal_fault */ + kTopEarlgreyAlertIdKeymgrFatalFaultErr = 23, /**< keymgr_fatal_fault_err */ + kTopEarlgreyAlertIdKeymgrRecovOperationErr = 24, /**< keymgr_recov_operation_err */ + kTopEarlgreyAlertIdCsrngFatalAlert = 25, /**< csrng_fatal_alert */ + kTopEarlgreyAlertIdEntropySrcRecovAlert = 26, /**< entropy_src_recov_alert */ + kTopEarlgreyAlertIdEntropySrcFatalAlert = 27, /**< entropy_src_fatal_alert */ + kTopEarlgreyAlertIdEdn0FatalAlert = 28, /**< edn0_fatal_alert */ + kTopEarlgreyAlertIdEdn1FatalAlert = 29, /**< edn1_fatal_alert */ + kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 30, /**< sram_ctrl_main_fatal_intg_error */ + kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 31, /**< sram_ctrl_main_fatal_parity_error */ + kTopEarlgreyAlertIdOtbnFatal = 32, /**< otbn_fatal */ + kTopEarlgreyAlertIdOtbnRecov = 33, /**< otbn_recov */ + kTopEarlgreyAlertIdRomCtrlFatal = 34, /**< rom_ctrl_fatal */ + kTopEarlgreyAlertIdLast = 34, /**< \internal The Last Valid Alert ID. */ } top_earlgrey_alert_id_t; /** @@ -1152,7 +1156,7 @@ * `top_earlgrey_alert_peripheral_t`. */ extern const top_earlgrey_alert_peripheral_t - top_earlgrey_alert_for_peripheral[31]; + top_earlgrey_alert_for_peripheral[35]; #define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2