Add option for ibex pipeline in fpga
diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index 7e97113..488730d 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -14,7 +14,8 @@
parameter bit RV32E = 0,
parameter bit RV32M = 1,
parameter int unsigned DmHaltAddr = 32'h1A110800,
- parameter int unsigned DmExceptionAddr = 32'h1A110808
+ parameter int unsigned DmExceptionAddr = 32'h1A110808,
+ parameter bit PipeLine = 0
) (
// Clock and Reset
input logic clk_i,
@@ -49,6 +50,12 @@
);
import top_pkg::*;
+ import tlul_pkg::*;
+
+ // if pipeline=1, do not allow pass through and always break the path
+ // if pipeline is 0, passthrough the fifo completely
+ localparam int FifoPass = PipeLine ? 1'b0 : 1'b1;
+ localparam int FifoDepth = PipeLine ? 4'h2 : 4'h0;
// Inst interface (internal)
logic instr_req_o;
@@ -68,6 +75,12 @@
logic [31:0] data_rdata_i;
logic data_err_i;
+ // Pipeline interfaces
+ tl_h2d_t tl_i_ibex2fifo;
+ tl_d2h_t tl_i_fifo2ibex;
+ tl_h2d_t tl_d_ibex2fifo;
+ tl_d2h_t tl_d_fifo2ibex;
+
`ifdef RVFI
logic rvfi_valid;
logic [63:0] rvfi_order;
@@ -177,7 +190,7 @@
end
// Convert core instruction interface to TL-UL
- assign tl_i_o = '{
+ assign tl_i_ibex2fifo = '{
a_valid: instr_req_o,
a_opcode: tlul_pkg::Get,
a_param: 3'h0,
@@ -191,10 +204,27 @@
d_ready: 1'b1
};
- assign instr_gnt_i = tl_i_i.a_ready & tl_i_o.a_valid;
- assign instr_rvalid_i = tl_i_i.d_valid;
- assign instr_rdata_i = tl_i_i.d_data;
- assign instr_err_i = tl_i_i.d_error;
+ assign instr_gnt_i = tl_i_fifo2ibex.a_ready & tl_i_ibex2fifo.a_valid;
+ assign instr_rvalid_i = tl_i_fifo2ibex.d_valid;
+ assign instr_rdata_i = tl_i_fifo2ibex.d_data;
+ assign instr_err_i = tl_i_fifo2ibex.d_error;
+
+ tlul_fifo_sync #(
+ .ReqPass(FifoPass),
+ .RspPass(FifoPass),
+ .ReqDepth(FifoDepth),
+ .RspDepth(FifoDepth)
+ ) fifo_i (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i (tl_i_ibex2fifo),
+ .tl_h_o (tl_i_fifo2ibex),
+ .tl_d_o (tl_i_o),
+ .tl_d_i (tl_i_i),
+ .spare_req_i (1'b0),
+ .spare_req_o (),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
// For core data interface, calculate a_size from data_be_o
logic [2:0] data_be_countones;
@@ -216,7 +246,7 @@
// a_address must be aligned with a_size (TL spec 6.2)
// if _address is not aligned to word address, it cannot handle the condition
// when addr[1:0] == 2'b01 and data_type == 2'b01 (Half-word)
- assign tl_d_o = '{
+ assign tl_d_ibex2fifo = '{
a_valid: data_req_o,
a_opcode: (~data_we_o) ? tlul_pkg::Get :
(data_be_o == 4'hf) ? tlul_pkg::PutFullData :
@@ -231,10 +261,28 @@
d_ready: 1'b1
};
- assign data_gnt_i = tl_d_i.a_ready & tl_d_o.a_valid;
- assign data_rvalid_i = tl_d_i.d_valid;
- assign data_rdata_i = tl_d_i.d_data;
- assign data_err_i = tl_d_i.d_error;
+ assign data_gnt_i = tl_d_fifo2ibex.a_ready & tl_d_ibex2fifo.a_valid;
+ assign data_rvalid_i = tl_d_fifo2ibex.d_valid;
+ assign data_rdata_i = tl_d_fifo2ibex.d_data;
+ assign data_err_i = tl_d_fifo2ibex.d_error;
+
+ tlul_fifo_sync #(
+ .ReqPass(FifoPass),
+ .RspPass(FifoPass),
+ .ReqDepth(FifoDepth),
+ .RspDepth(FifoDepth)
+ ) fifo_d (
+ .clk_i,
+ .rst_ni,
+ .tl_h_i (tl_d_ibex2fifo),
+ .tl_h_o (tl_d_fifo2ibex),
+ .tl_d_o (tl_d_o),
+ .tl_d_i (tl_d_i),
+ .spare_req_i (1'b0),
+ .spare_req_o (),
+ .spare_rsp_i (1'b0),
+ .spare_rsp_o ());
+
`ifdef RVFI
ibex_tracer ibex_tracer_i (
diff --git a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
index 373c87c..f3e1d24 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
+++ b/hw/top_earlgrey/doc/top_earlgrey.tpl.sv
@@ -4,7 +4,9 @@
<% import re
%>\
-module top_earlgrey (
+module top_earlgrey #(
+ parameter bit IbexPipeLine = 0
+) (
// Clock and Reset
input clk_i,
input rst_ni,
@@ -109,7 +111,8 @@
.RV32E (0),
.RV32M (1),
.DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
- .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress)
+ .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
+ .PipeLine (IbexPipeLine)
) core (
// clock and reset
.clk_i (clk_i),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey.sv b/hw/top_earlgrey/rtl/top_earlgrey.sv
index 0022526..910b6ca 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey.sv
@@ -2,7 +2,9 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-module top_earlgrey (
+module top_earlgrey #(
+ parameter bit IbexPipeLine = 0
+) (
// Clock and Reset
input clk_i,
input rst_ni,
@@ -119,7 +121,8 @@
.RV32E (0),
.RV32M (1),
.DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
- .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress)
+ .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
+ .PipeLine (IbexPipeLine)
) core (
// clock and reset
.clk_i (clk_i),
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
index f49f436..a7667ab 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
@@ -46,7 +46,9 @@
logic cio_jtag_trst_n_p2d, cio_jtag_srst_n_p2d;
// Top-level design
- top_earlgrey top_earlgrey (
+ top_earlgrey #(
+ .IbexPipeLine(1)
+ ) top_earlgrey (
.clk_i (clk_sys),
.rst_ni (rst_sys_n),
