[aon_timer] Initial commit of AON Timer docs
Just a basic translation of the proposal doc into markdown, plus an
initial draft of the HJSON spec.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
diff --git a/hw/ip/aon_timer/data/aon_timer.hjson b/hw/ip/aon_timer/data/aon_timer.hjson
new file mode 100644
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+++ b/hw/ip/aon_timer/data/aon_timer.hjson
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+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+{
+ name: "aon_timer",
+ clock_primary: "clk_i",
+ other_clock_list: [
+ "clk_aon_i"
+ ],
+ bus_device: "tlul",
+ interrupt_list: [
+ { name: "wkup_timer_expired",
+ desc: "Raised if the wakeup timer has hit the specified threshold"
+ },
+ { name: "wdog_timer_bark",
+ desc: "Raised if the watchdog timer has hit the bark threshold"
+ },
+ ],
+ wakeup_list: [
+ { name: "aon_timer",
+ desc: "Raised if the wakeup or watchdog timer has hit the specified threshold"
+ },
+ ],
+ inter_signal_list: [
+ { name: "counter_run",
+ type: "uni",
+ act: "rsp",
+ package: "",
+ struct: "logic",
+ width: "1"
+ },
+ { name: "sleep_mode",
+ type: "uni",
+ act: "rsp",
+ package: "",
+ struct: "logic",
+ width: "1"
+ }
+ ],
+ no_auto_intr_regs: "true",
+ regwidth: "32",
+ registers: [
+ { name: "WKUP_CTRL",
+ desc: "Wakeup Timer Control register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "enable",
+ desc: "When set to 1, the wakeup timer will count",
+ }
+ { bits: "12:1",
+ name: "prescaler",
+ desc: "Pre-scaler value for wakeup timer count",
+ }
+ ]
+ },
+ { name: "WKUP_THOLD",
+ desc: "Wakeup Timer Threshold Register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "31:0",
+ name: "threshold",
+ desc: "The count at which a wakeup interrupt should be generated",
+ }
+ ]
+ },
+ { name: "WKUP_COUNT",
+ desc: "Wakeup Timer Count Register",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "31:0",
+ name: "count",
+ desc: "The current wakeup counter value",
+ }
+ ]
+ },
+ { name: "WDOG_REGWEN",
+ desc: "Watchdog Timer Write Enable Register",
+ swaccess: "rw1c",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "regwen",
+ desc: "Once cleared, the watchdog configuration will be locked until the next reset",
+ resval: 1
+ }
+ ]
+ },
+ { name: "WDOG_CTRL",
+ desc: "Watchdog Timer Control register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WDOG_REGWEN",
+ fields: [
+ { bits: "0",
+ name: "enable",
+ desc: "When set to 1, the watchdog timer will count",
+ },
+ { bits: "1",
+ name: "pause_in_sleep",
+ desc: "When set to 1, the watchdog timer will not count during sleep",
+ }
+ ]
+ },
+ { name: "WDOG_BARK_THOLD",
+ desc: "Watchdog Timer Bark Threshold Register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WDOG_REGWEN",
+ fields: [
+ { bits: "31:0",
+ name: "threshold",
+ desc: "The count at which a watchdog bark interrupt should be generated",
+ }
+ ]
+ },
+ { name: "WDOG_BITE_THOLD",
+ desc: "Watchdog Timer Bite Threshold Register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WDOG_REGWEN",
+ fields: [
+ { bits: "31:0",
+ name: "threshold",
+ desc: "The count at which a watchdog bite reset should be generated",
+ }
+ ]
+ },
+ { name: "WDOG_COUNT",
+ desc: "Watchdog Timer Count Register",
+ swaccess: "rw",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "31:0",
+ name: "count",
+ desc: "The current watchdog counter value",
+ }
+ ]
+ },
+ { name: "INTR_STATE",
+ desc: "Interrupt State Register",
+ swaccess: "rw1c",
+ hwaccess: "hrw",
+ fields: [
+ { bits: "0",
+ name: "wkup_timer_expired",
+ desc: "Raised if the wakeup timer has hit the specified threshold",
+ }
+ { bits: "1",
+ name: "wdog_timer_expired",
+ desc: "Raised if the watchdog timer has hit the bark threshold",
+ }
+ ]
+ },
+ { name: "INTR_TEST",
+ desc: "Interrupt Test Register",
+ swaccess: "wo",
+ hwaccess: "hro",
+ fields: [
+ { bits: "0",
+ name: "wkup_timer_expired",
+ desc: "Write 1 to force wkup_timer_expired interrupt",
+ }
+ { bits: "1",
+ name: "wdog_timer_expired",
+ desc: "Write 1 to force wdog_timer_expired (watchdog bark) interrupt",
+ }
+ ]
+ },
+ ],
+}
+
diff --git a/hw/ip/aon_timer/data/aon_timer.prj.hjson b/hw/ip/aon_timer/data/aon_timer.prj.hjson
new file mode 100644
index 0000000..70b74c5
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+++ b/hw/ip/aon_timer/data/aon_timer.prj.hjson
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+{
+ name: "aon_timer",
+ design_spec: "hw/ip/aon_timer/doc",
+ dv_plan: "",
+ hw_checklist: "",
+ version: "0.1",
+ life_stage: "L0",
+ design_stage: "D0",
+ verification_stage: "V0",
+}
diff --git a/hw/ip/aon_timer/doc/_index.md b/hw/ip/aon_timer/doc/_index.md
new file mode 100644
index 0000000..50f5fc0
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+++ b/hw/ip/aon_timer/doc/_index.md
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+---
+title: "AON Timer Technical Specification"
+---
+
+# Overview
+
+This document specifies the Always-On ("AON") Timer IP functionality.
+This module conforms to the [Comportable guideline for peripheral functionality.]({{< relref "doc/rm/comportability_specification" >}})
+See that document for an overview of how it is integrated into the top level system.
+
+## Features
+
+- Two 32-bit upcounting timers: one timer functions as a wakeup timer, one as a watchdog timer
+- The watchdog timer has two thresholds: bark (generates an interrupt) and bite (resets core)
+- There is 12 bit pre-scaler for the wakeup timer to enable very long timeouts
+
+## Description
+
+### AON Wakeup timer
+
+The always-on wakeup timer operation is straightforward.
+A count starts at 0 and slowly ticks upwards (one tick every N+1 clock cycles, where N is the pre-scaler value).
+When it reaches / exceeds the wake count, a level wakeup signal is sent to the power manager and a level IRQ is sent to the processor.
+This wakeup signal stays high until it is explicitly acknowledged by software.
+The wakeup timer can be used like a real-time clock for long periods in a low-power mode (though it does not give any guarantees of time-accuracy TODO: specify accuracy).
+
+### AON Watchdog timer
+
+The always-on watchdog timer behaves similarly to the wakeup timer.
+It has an independent count starting at 0 which slowly ticks upwards.
+When the first threshold is met or exceeded, a level wakeup signal (if enabled) is sent to the power manager.
+Simultaneously, a level IRQ signal is also generated to the processor.
+
+If the system is in a low power state, the wakeup signal asks the power manager to wake the system such that the IRQ can be serviced.
+If the system is not in a low power mode, the IRQ is immediately serviced.
+Both the wakeup and the IRQ signals remain asserted until system reset or explicit acknowledgement by software.
+This first threshold is known as the watchdog bark.
+
+Note that it is not recommended to connect this IRQ to a non-maskable interrupt (NMI) pin.
+This would require the start-up (ROM) code to be able to handle the watchdog bark, or the core might get stuck when resuming from low-power modes.
+
+When the second threshold is met (this is known as the watchdog bite), a reset request is sent to the power manager which will trigger a system reset.
+This is independent of the IRQ sent as part of the watchdog bark.
+The system reset also resets the always-on timer, so software is not required to directly acknowledge anything after a watchdog reset.
+
+To prevent the watchdog bark or bite, software is expected to periodically reset the count when operating normally.
+This is referred to as petting the watchdog, and is achieved by resetting the count to zero.
+
+Since this timer functions as a watchdog, it has two additional functions not present in the always-on wakeup timer:
+* Watchdog configuration lock
+* Watchdog pause in sleep
+
+Unlike the wakeup timer, the watchdog timer configuration can be locked by firmware until the next system reset.
+This allows the option of preventing firmware from accidentally or maliciously disabling the watchdog.
+
+The "pause in sleep" option controls whether the watchdog timer continues to count in low-power modes.
+This allows configurations where the watchdog timer can remain programmed and locked while the device is put to sleep for relatively long periods, controlled by the wakeup timer.
+Without this feature, the watchdog timer might wake up the core prematurely by triggering a watchdog bark.
+
+# Theory of Operations
+
+## Block Diagram
+
+
+
+See the block diagram for high level function and connectivity.
+The timer interacts with the CPU core and the power manager and reset manager to drive wakeup / reset events and interrupts.
+There is also an extra input to tell the counter whether to run ("counter-run").
+This is used to stop the watchdog timer running when in debugging mode or when the alert handler has put the system in a "killed" state.
+
+## Hardware Interfaces
+
+{{< hwcfg "hw/ip/aon_timer/data/aon_timer.hjson" >}}
+
+## Design Details
+
+The always-on timer will run on a ~200KHz clock.
+The timers themselves are 32b wide, giving a maximum timeout window of roughly ~6 hours.
+For the wakeup timer, pre-scaler extends the maximum timeout to ~1000 days.
+
+Since the timer core runs on a slow clock, register values are sampled into the main clock domain to ensure register read / writes do not incur large latencies.
+
+# Programmers Guide
+
+## Initialization
+
+1. Write the timer values {{<regref"WKUP_COUNT">}} and {{<regref"WDOG_COUNT">}} to zero.
+2. Program the desired wakeup pre-scaler value in {{<regref"WKUP_CTRL">}}.
+3. Program the desired thresholds in {{<regref"WKUP_THOLD">}}, {{<regref"WDOG_BARK_THOLD">}} and {{<regref"WDOG_BITE_THOLD">}}.
+4. Set the enable bit to 1 in the {{<regref"WKUP_CTRL">}} / {{<regref"WDOG_CTRL">}} registers.
+5. If desired, lock the watchdog configuration by writing 1 to the `regwen` bit in {{<regref"WDOG_REGWEN">}}.
+
+## Watchdog pet
+
+Pet the watchdog by writing zero to the {{<regref"WDOG_COUNT">}} register.
+
+## Interrupt Handling
+
+If either timer reaches the programmed threshold, interrupts are generated from the AON_TIMER module.
+Disable or reinitialize the wakeup timer if required by clearing the enable bit in {{<regref"WKUP_CTRL">}} or clearing the timer value in {{<regref"WKUP_COUNT">}}.
+Clear the interrupt by writing 1 into the Interrupt Status Register {{<regref "INTR_STATE">}}.
+
+## Device Interface Functions (DIFs)
+
+TODO
+
+## Register Table
+
+{{< registers "hw/ip/aon_timer/data/aon_timer.hjson" >}}
diff --git a/hw/ip/aon_timer/doc/aon_timer_block_diagram.svg b/hw/ip/aon_timer/doc/aon_timer_block_diagram.svg
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\ No newline at end of file
diff --git a/util/build_docs.py b/util/build_docs.py
index e9f065e..9f4244f 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -55,6 +55,7 @@
# Pre-generate register and hwcfg fragments from these files.
"hardware_definitions": [
"hw/ip/aes/data/aes.hjson",
+ "hw/ip/aon_timer/data/aon_timer.hjson",
"hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson",
"hw/ip/entropy_src/data/entropy_src.hjson",
"hw/ip/csrng/data/csrng.hjson",
