| commit | d8c58fda0a57a056c5d3fabe592004ab550f3843 | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri May 13 14:26:23 2022 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Mon May 16 14:41:12 2022 +0100 |
| tree | 6ccd4e63f4056744c28c3f09f095b7d8110c375a | |
| parent | 382709a4fb915c894bafaee9e1d3119d82633e7a [diff] |
[dv] Cleanups in TL error vseq's tl_instr_type_err task This was prompted by an Xcelium warning caused by the fact instr_type was of type bit[3:0] and was passed to a port expecting a mubi4_t. Because it seemed a bit tidier, I've refactored things a bit so that the randcase just picks values that will be passed to a tl_access task that runs afterwards. We're also now randomising data properly in the second case, which I think we'd missed before. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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