[fpv] Fix fusesoc dependecy issue
When CSR assertions can be generated automatically, we encountered some
fusesoc dependency issue. Because CSR auto-gen assertions depend on
RTL(reg core file), for most of IPs, there isn't an independent reg file
core, thus the auto-gen file directly used the rtl core file. And formal
target is build on the default RTL core file. Now we try to import the
CSR auto-gen core file, and this creates a dependency issue.
To solve this issue, the new formal core file is built on IP_sva.core
instead of RTL core file.
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/util/uvmdvgen/sva.core.tpl b/util/uvmdvgen/sva.core.tpl
index 89863d7..3324369 100644
--- a/util/uvmdvgen/sva.core.tpl
+++ b/util/uvmdvgen/sva.core.tpl
@@ -15,6 +15,10 @@
- ${name}_bind.sv
file_type: systemVerilogSource
+ files_formal:
+ depend:
+ - lowrisc:ip:${name}
+
% if has_ral:
generate:
csr_assert_gen:
@@ -25,10 +29,16 @@
% endif
targets:
- default:
+ default: &default_target
filesets:
- files_dv
% if has_ral:
generate:
- csr_assert_gen
+ formal:
+ <<: *default_target
+ filesets:
+ - files_formal
+ - files_dv
+ toplevel: ${name}
% endif
