[aes] Specify missing reset values for shadowed control register
Previously, some fields in the control register did not have a specified
reset value. They were implicitly reset to 0. This commit 1) specifies
these reset values and 2) uses the corresponding _RESVAL parameters
exported by the regtool to define the reset value control register (hwext).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/ip/aes/aes.core b/hw/ip/aes/aes.core
index c0f50f0..f2b7d8b 100644
--- a/hw/ip/aes/aes.core
+++ b/hw/ip/aes/aes.core
@@ -14,8 +14,8 @@
- lowrisc:ip:lc_ctrl_pkg
- lowrisc:ip:edn_pkg
files:
- - rtl/aes_pkg.sv
- rtl/aes_reg_pkg.sv
+ - rtl/aes_pkg.sv
- rtl/aes_reg_top.sv
- rtl/aes_core.sv
- rtl/aes_ctr.sv
diff --git a/hw/ip/aes/data/aes.hjson b/hw/ip/aes/data/aes.hjson
index 6049db5..6277274 100644
--- a/hw/ip/aes/data/aes.hjson
+++ b/hw/ip/aes/data/aes.hjson
@@ -329,6 +329,7 @@
fields: [
{ bits: "0",
name: "OPERATION",
+ resval: "0",
desc: '''
Select encryption(0) or decryption(1) operation of AES unit.
'''
@@ -413,6 +414,7 @@
}
{ bits: "10",
name: "MANUAL_OPERATION",
+ resval: "0"
desc: '''
Controls whether the AES unit is operated in normal/automatic mode (0) or fully manual mode (1).
In automatic mode (0), the AES unit automatically i) starts to encrypt/decrypt when it receives new input data, and ii) stalls during the last encryption/decryption cycle if the previous output data has not yet been read.
diff --git a/hw/ip/aes/rtl/aes_pkg.sv b/hw/ip/aes/rtl/aes_pkg.sv
index 245dbf1..a22977e 100644
--- a/hw/ip/aes/rtl/aes_pkg.sv
+++ b/hw/ip/aes/rtl/aes_pkg.sv
@@ -316,11 +316,11 @@
} ctrl_reg_t;
parameter ctrl_reg_t CTRL_RESET = '{
- force_zero_masks: '0,
- manual_operation: '0,
- key_len: AES_128,
- mode: AES_NONE,
- operation: AES_ENC
+ force_zero_masks: aes_reg_pkg::AES_CTRL_SHADOWED_FORCE_ZERO_MASKS_RESVAL,
+ manual_operation: aes_reg_pkg::AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL,
+ key_len: key_len_e'(aes_reg_pkg::AES_CTRL_SHADOWED_KEY_LEN_RESVAL),
+ mode: aes_mode_e'(aes_reg_pkg::AES_CTRL_SHADOWED_MODE_RESVAL),
+ operation: aes_op_e'(aes_reg_pkg::AES_CTRL_SHADOWED_OPERATION_RESVAL)
};
// Multiplication by {02} (i.e. x) on GF(2^8)
diff --git a/hw/ip/aes/rtl/aes_reg_pkg.sv b/hw/ip/aes/rtl/aes_reg_pkg.sv
index f0e9d9f..0673577 100644
--- a/hw/ip/aes/rtl/aes_reg_pkg.sv
+++ b/hw/ip/aes/rtl/aes_reg_pkg.sv
@@ -281,8 +281,10 @@
parameter logic [31:0] AES_DATA_OUT_2_RESVAL = 32'h 0;
parameter logic [31:0] AES_DATA_OUT_3_RESVAL = 32'h 0;
parameter logic [11:0] AES_CTRL_SHADOWED_RESVAL = 12'h c0;
+ parameter logic [0:0] AES_CTRL_SHADOWED_OPERATION_RESVAL = 1'h 0;
parameter logic [5:0] AES_CTRL_SHADOWED_MODE_RESVAL = 6'h 20;
parameter logic [2:0] AES_CTRL_SHADOWED_KEY_LEN_RESVAL = 3'h 1;
+ parameter logic [0:0] AES_CTRL_SHADOWED_MANUAL_OPERATION_RESVAL = 1'h 0;
parameter logic [0:0] AES_CTRL_SHADOWED_FORCE_ZERO_MASKS_RESVAL = 1'h 0;
// Register index
