| commit | f56b9b4ce2107c85d2206dff3554aaa7f5abd3af | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@google.com> | Tue Mar 16 16:42:47 2021 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Wed Mar 17 16:35:14 2021 -0700 |
| tree | 0f25a3b573b70c58732c8f3653d1208bbb618fa2 | |
| parent | a4e2d7f2e1d7d76455558187a7792fa9176f6ee4 [diff] |
[dv/top_earlgrey] chip csr_aliasing timeout Current chip csr_aliasing automation test timeout because chip level totally has 1510 csrs in csr_aliasing test. So totally there are around 1510 * 1510 csr access in one iteration. To reduce the runtime, For each CSR in top-level, we only randomly pick 100 CSRs, so the totally csr access is 1510 * 100. For two iterations, this fix reduce the runtime to 38 mins. Signed-off-by: Cindy Chen <chencindy@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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