| commit | 7d6d53d11f21675a558da1eb51fc93c1329ca7c9 | [log] [tgz] |
|---|---|---|
| author | Timothy Chen <timothytim@google.com> | Mon Nov 01 15:17:08 2021 -0700 |
| committer | tjaychen <timothytim@google.com> | Tue Nov 02 15:15:07 2021 -0700 |
| tree | c64254dcc30e8cd8cb84c4f27ac6ed8966ffe09b | |
| parent | 0a345f9331a47c2179b353259e288d12eab13cc1 [diff] |
[sram_ctrl] Fix sram error checking and byte sequencing - Should fix #8905 - Previously, the error checking was mostly done downstream of sram_byte. This meant that illegal write transactions would become correctly transformed by the sram_byte module, and thus the would-be error silenced. - This PR moves all the error checking upstream of the sram byte module and passes the error through if it is observed. This is more consistent error behavior. - The documentation is also updated with a high level overview on how the adapater sram behaves. Signed-off-by: Timothy Chen <timothytim@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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