[systemtest] Adjust Verilator UART frequency
The UART frequency was changed, but not copied over into all places that
need it. Fix that and add a comment to make it less likely to go out of
sync the next time.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/sw/device/lib/arch/device_sim_verilator.c b/sw/device/lib/arch/device_sim_verilator.c
index 2d0d9fe..cfd4ef0 100644
--- a/sw/device/lib/arch/device_sim_verilator.c
+++ b/sw/device/lib/arch/device_sim_verilator.c
@@ -12,7 +12,8 @@
const device_type_t kDeviceType = kDeviceSimVerilator;
// Changes to the clock frequency or UART baud rate must also be reflected at
-// `hw/top_earlgrey/rtl/top_earlgrey_verilator.sv`.
+// `hw/top_earlgrey/rtl/top_earlgrey_verilator.sv` and
+// `test/systemtest/earlgrey/test_sim_verilator.py`.
const uint64_t kClockFreqCpuHz = 500 * 1000; // 500kHz
const uint64_t kClockFreqPeripheralHz = 125 * 1000; // 125kHz
