[util] Prep work for shadow reset impelemtation
- This cleans up the python files behind rstmgr a bit
and makes them into a class (following clk examples)
- Add some plumbing for resets to self determine domains
and need for shadow resets. This will remove the need
for correct accounting in the hjson
- Concentrate some information into the reset class instead
of having it spread around topgen / various dicts. Also
add helper functions to retrive this information.
- The level of abstraction is probably a bit too much, but
this is probably a bit cleaner until we get a chance to organize
into a "top" class that represents the entire design.
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Auto generate
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Some touch-ups based on comments
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/util/reggen/ip_block.py b/util/reggen/ip_block.py
index 594e019..06d473c 100644
--- a/util/reggen/ip_block.py
+++ b/util/reggen/ip_block.py
@@ -10,7 +10,7 @@
from .alert import Alert
from .bus_interfaces import BusInterfaces
-from .clocking import Clocking
+from .clocking import Clocking, ClockingItem
from .inter_signal import InterSignal
from .lib import (check_keys, check_name, check_int, check_bool,
check_list, check_optional_str)
@@ -348,3 +348,18 @@
else:
raise ValueError("Signal {} does not exist in IP block {}"
.format(name, self.name))
+
+ def has_shadowed_reg(self) -> bool:
+ '''Return boolean indication whether reg block contains shadowed registers'''
+
+ for rb in self.reg_blocks.values():
+ if rb.has_shadowed_reg():
+ return True
+
+ # if we are here, then no one has has a shadowed register
+ return False
+
+ def get_primary_clock(self) -> ClockingItem:
+ '''Return primary clock of an block'''
+
+ return self.clocking.primary
