[dv/rstmgr] Fix POR reset and add increase coverage
Make sure tests start after at least one full aon cycle out of reset,
otherwise the SVA will miss sampling reset.
Delay the pwrmgr rst_lc_req and rst_sys_req to be more realistic and to
visit more of the state space.
Signed-off-by: Guillermo Maturana <maturana@google.com>
diff --git a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
index 629e6cf..49cdc9b 100644
--- a/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
+++ b/hw/ip/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv
@@ -205,8 +205,11 @@
task send_reset(pwrmgr_pkg::reset_cause_e reset_cause,
logic [pwrmgr_pkg::TotalResetWidth-1:0] rstreqs);
set_reset_cause(reset_cause);
- set_pwrmgr_rst_reqs(.rst_lc_req('1), .rst_sys_req('1));
set_rstreqs(rstreqs);
+ cfg.io_div4_clk_rst_vif.wait_clks(2);
+ // These lag the reset requests since they are set after the pwrmgr fast fsm has made some
+ // state transitions.
+ set_pwrmgr_rst_reqs(.rst_lc_req('1), .rst_sys_req('1));
`uvm_info(`gfn, $sformatf("Sending %0s reset", reset_cause.name()), UVM_LOW)
cfg.io_div4_clk_rst_vif.wait_clks(non_ndm_reset_cycles);
// Cause the reset to drop.
@@ -270,11 +273,14 @@
join
endtask
- // This waits till the outgoing POR reset for the CPU goes inactive.
+ // This waits till the outgoing reset for the CPU goes inactive. It also waits at least one
+ // aon cycle to make sure we don't drop por_n_i before SVA has time to detect the por_aon
+ // reset went inactive.
local task wait_for_cpu_out_of_reset();
`DV_SPINWAIT_EXIT(wait (cfg.rstmgr_vif.resets_o.rst_sys_n[1] == 1'b1);,
cfg.clk_rst_vif.wait_clks(CPU_RESET_CLK_CYCLES);,
"timeout waiting for cpu reset inactive")
+ cfg.aon_clk_rst_vif.wait_clks(1);
endtask
virtual task apply_reset(string kind = "HARD");
