[top, util] Add quick support for multiple power domain resets
This commits adds the ability for modules to be declared under
multiple power domains and thus assign resets of different domains
to each port.
Note this is a quick bolt on and not the ideal way of doing things.
Ideally, the concept of multiple domains should be expressed in the
ip.hjson themselves. The top level then hierarchically connects the
available top level domains to the sub-domains.
The ip.hjson would then also clearly state what local domain each
reset is related to, and the connective tissue should be built-up that
way instead of being mandated from the top.
However, that is a larger change than necessary at this point, and should
be accounted for later in the reset generation refactoring.
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/rstmgr/data/rstmgr.sv.tpl b/hw/ip/rstmgr/data/rstmgr.sv.tpl
index ae9c5f2..d425a86 100644
--- a/hw/ip/rstmgr/data/rstmgr.sv.tpl
+++ b/hw/ip/rstmgr/data/rstmgr.sv.tpl
@@ -390,7 +390,7 @@
% for intf, eps in export_rsts.items():
% for ep, rsts in eps.items():
% for rst in rsts:
- assign resets_${intf}_o.rst_${intf}_${ep}_${rst}_n = resets_o.rst_${rst}_n;
+ assign resets_${intf}_o.rst_${intf}_${ep}_${rst['name']}_n = resets_o.rst_${rst['name']}_n;
% endfor
% endfor
% endfor
diff --git a/hw/ip/rstmgr/data/rstmgr_pkg.sv.tpl b/hw/ip/rstmgr/data/rstmgr_pkg.sv.tpl
index f99775e..47c8b25 100644
--- a/hw/ip/rstmgr/data/rstmgr_pkg.sv.tpl
+++ b/hw/ip/rstmgr/data/rstmgr_pkg.sv.tpl
@@ -44,7 +44,7 @@
typedef struct packed {
% for ep, rsts in eps.items():
% for rst in rsts:
- logic [PowerDomains-1:0] rst_${intf}_${ep}_${rst}_n;
+ logic [PowerDomains-1:0] rst_${intf}_${ep}_${rst['name']}_n;
% endfor
% endfor
} rstmgr_${intf}_out_t;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index b66fd81..63a3a10 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -515,13 +515,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -555,13 +562,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -595,13 +609,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -635,13 +656,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -675,13 +703,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -716,14 +751,21 @@
clock_group: peri
reset_connections:
{
- rst_ni: spi_device
+ rst_ni:
+ {
+ name: spi_device
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -792,15 +834,26 @@
clock_group: peri
reset_connections:
{
- rst_ni: spi_host0
- rst_core_ni: spi_host0_core
+ rst_ni:
+ {
+ name: spi_host0
+ domain: "0"
+ }
+ rst_core_ni:
+ {
+ name: spi_host0_core
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_core_i: clkmgr_aon_clocks.clk_io_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -847,15 +900,26 @@
clock_group: peri
reset_connections:
{
- rst_ni: spi_host1
- rst_core_ni: spi_host1_core
+ rst_ni:
+ {
+ name: spi_host1
+ domain: "0"
+ }
+ rst_core_ni:
+ {
+ name: spi_host1_core
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
clk_core_i: clkmgr_aon_clocks.clk_io_div2_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -899,13 +963,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: i2c0
+ rst_ni:
+ {
+ name: i2c0
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -939,13 +1010,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: i2c1
+ rst_ni:
+ {
+ name: i2c1
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -979,13 +1057,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: i2c2
+ rst_ni:
+ {
+ name: i2c2
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -1019,13 +1104,20 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -1059,13 +1151,20 @@
clock_group: timers
reset_connections:
{
- rst_ni: sys_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_timers
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -1105,9 +1204,21 @@
]
reset_connections:
{
- rst_ni: usb
- rst_aon_ni: sys_aon
- rst_usb_48mhz_ni: usbif
+ rst_ni:
+ {
+ name: usb
+ domain: "0"
+ }
+ rst_aon_ni:
+ {
+ name: sys_aon
+ domain: "0"
+ }
+ rst_usb_48mhz_ni:
+ {
+ name: usbif
+ domain: "0"
+ }
}
clock_connections:
{
@@ -1115,7 +1226,10 @@
clk_aon_i: clkmgr_aon_clocks.clk_aon_peri
clk_usb_48mhz_i: clkmgr_aon_clocks.clk_usb_peri
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -1256,8 +1370,16 @@
clock_group: secure
reset_connections:
{
- rst_ni: lc_io_div4
- rst_edn_ni: sys
+ rst_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
+ rst_edn_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
base_addrs:
{
@@ -1269,7 +1391,10 @@
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -1583,15 +1708,26 @@
clock_group: secure
reset_connections:
{
- rst_ni: lc_io_div4
- rst_kmac_ni: sys
+ rst_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
+ rst_kmac_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_kmac_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -2051,8 +2187,16 @@
clock_group: secure
reset_connections:
{
- rst_ni: lc_io_div4
- rst_edn_ni: sys
+ rst_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
+ rst_edn_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
attr: templated
clock_connections:
@@ -2060,7 +2204,10 @@
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -2172,10 +2319,21 @@
clock_group: powerup
reset_connections:
{
- rst_ni: por_io_div4
- rst_slow_ni: por_aon
+ rst_ni:
+ {
+ name: por_io_div4
+ domain: Aon
+ }
+ rst_slow_ni:
+ {
+ name: por_aon
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
attr: templated
clock_connections:
{
@@ -2418,9 +2576,16 @@
clock_group: powerup
reset_connections:
{
- rst_ni: por_io_div4
+ rst_ni:
+ {
+ name: por_io_div4
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
attr: templated
clock_connections:
{
@@ -2563,14 +2728,41 @@
clock_group: powerup
reset_connections:
{
- rst_ni: por_io_div4
- rst_main_ni: por
- rst_io_ni: por_io
- rst_usb_ni: por_usb
- rst_io_div2_ni: por_io_div2
- rst_io_div4_ni: por_io_div4
+ rst_ni:
+ {
+ name: por_io_div4
+ domain: Aon
+ }
+ rst_main_ni:
+ {
+ name: por
+ domain: Aon
+ }
+ rst_io_ni:
+ {
+ name: por_io
+ domain: Aon
+ }
+ rst_usb_ni:
+ {
+ name: por_usb
+ domain: Aon
+ }
+ rst_io_div2_ni:
+ {
+ name: por_io_div2
+ domain: Aon
+ }
+ rst_io_div4_ni:
+ {
+ name: por_io_div4
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
attr: templated
clock_connections:
{
@@ -2788,10 +2980,21 @@
clock_group: infra
reset_connections:
{
- rst_ni: sys_io_div4
- rst_aon_ni: sys_aon
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: Aon
+ }
+ rst_aon_ni:
+ {
+ name: sys_aon
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_infra
@@ -2855,14 +3058,25 @@
clock_group: peri
reset_connections:
{
- rst_ni: sys_io_div4
- rst_aon_ni: sys_aon
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: Aon
+ }
+ rst_aon_ni:
+ {
+ name: sys_aon
+ domain: Aon
+ }
}
clock_reset_export:
[
ast
]
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_peri
@@ -2927,10 +3141,21 @@
clock_group: powerup
reset_connections:
{
- rst_ni: sys_io_div4
- rst_core_ni: sys_aon
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: Aon
+ }
+ rst_core_ni:
+ {
+ name: sys_aon
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
@@ -2970,10 +3195,21 @@
clock_group: powerup
reset_connections:
{
- rst_ni: sys_io_div4
- rst_aon_ni: sys_aon
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: Aon
+ }
+ rst_aon_ni:
+ {
+ name: sys_aon
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
attr: templated
clock_connections:
{
@@ -3223,10 +3459,21 @@
clock_group: timers
reset_connections:
{
- rst_ni: lc_io_div4
- rst_aon_ni: lc_aon
+ rst_ni:
+ {
+ name: lc_io_div4
+ domain: Aon
+ }
+ rst_aon_ni:
+ {
+ name: lc_aon
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
attr: templated
clock_connections:
{
@@ -3332,14 +3579,21 @@
]
reset_connections:
{
- rst_ni: lc_io_div4
+ rst_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
}
attr: reggen_only
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -3374,9 +3628,16 @@
]
reset_connections:
{
- rst_ni: lc_io_div4
+ rst_ni:
+ {
+ name: lc_io_div4
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
attr: reggen_top
clock_connections:
{
@@ -3468,10 +3729,21 @@
clock_group: infra
reset_connections:
{
- rst_ni: sys_io_div4
- rst_otp_ni: lc_io_div4
+ rst_ni:
+ {
+ name: sys_io_div4
+ domain: Aon
+ }
+ rst_otp_ni:
+ {
+ name: lc_io_div4
+ domain: Aon
+ }
}
- domain: Aon
+ domain:
+ [
+ Aon
+ ]
param_decl:
{
InstrExec: "0"
@@ -3655,8 +3927,16 @@
clock_group: infra
reset_connections:
{
- rst_ni: lc
- rst_otp_ni: lc_io_div4
+ rst_ni:
+ {
+ name: lc
+ domain: "0"
+ }
+ rst_otp_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
}
base_addrs:
{
@@ -3690,7 +3970,10 @@
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list:
[
@@ -4031,7 +4314,11 @@
clock_group: infra
reset_connections:
{
- rst_ni: lc
+ rst_ni:
+ {
+ name: lc
+ domain: "0"
+ }
}
base_addrs:
{
@@ -4042,7 +4329,10 @@
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -4179,14 +4469,21 @@
clock_group: secure
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
attr: templated
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -4258,8 +4555,16 @@
clock_group: trans
reset_connections:
{
- rst_ni: sys
- rst_edn_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_edn_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
param_decl:
{
@@ -4271,7 +4576,10 @@
clk_i: clkmgr_aon_clocks.clk_main_aes
clk_edn_i: clkmgr_aon_clocks.clk_main_aes
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
memory: {}
param_list:
[
@@ -4459,13 +4767,20 @@
clock_group: trans
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_hmac
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -4517,15 +4832,26 @@
clock_group: trans
reset_connections:
{
- rst_ni: sys
- rst_edn_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_edn_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_kmac
clk_edn_i: clkmgr_aon_clocks.clk_main_kmac
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
memory: {}
param_list:
[
@@ -4665,15 +4991,26 @@
clock_group: secure
reset_connections:
{
- rst_ni: sys
- rst_edn_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_edn_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -4990,13 +5327,20 @@
clock_group: secure
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -5125,7 +5469,11 @@
clock_group: secure
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_reset_export:
[
@@ -5135,7 +5483,10 @@
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -5264,7 +5615,11 @@
clock_group: secure
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_reset_export:
[
@@ -5274,7 +5629,10 @@
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -5343,13 +5701,20 @@
clock_group: secure
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_secure
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
param_list: []
inter_signal_list:
@@ -5419,8 +5784,16 @@
clock_group: infra
reset_connections:
{
- rst_ni: sys
- rst_otp_ni: lc_io_div4
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_otp_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
}
param_decl:
{
@@ -5447,7 +5820,10 @@
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_list:
[
{
@@ -5608,9 +5984,21 @@
clock_group: trans
reset_connections:
{
- rst_ni: sys
- rst_edn_ni: sys
- rst_otp_ni: lc_io_div4
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_edn_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_otp_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
@@ -5618,7 +6006,10 @@
clk_edn_i: clkmgr_aon_clocks.clk_main_otbn
clk_otp_i: clkmgr_aon_clocks.clk_io_div4_otbn
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_decl: {}
memory: {}
param_list:
@@ -5795,7 +6186,11 @@
clock_group: infra
reset_connections:
{
- rst_ni: sys
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
}
base_addrs:
{
@@ -5821,7 +6216,10 @@
{
clk_i: clkmgr_aon_clocks.clk_main_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
param_list:
[
{
@@ -5982,15 +6380,26 @@
clock_group: infra
reset_connections:
{
- rst_ni: sys
- rst_esc_ni: lc_io_div4
+ rst_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_esc_ni:
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_i: clkmgr_aon_clocks.clk_main_infra
clk_esc_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
memory: {}
param_list:
[
@@ -7052,15 +7461,26 @@
reset: rst_main_ni
reset_connections:
{
- rst_main_ni: sys
- rst_fixed_ni: sys_io_div4
+ rst_main_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_fixed_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_main_i: clkmgr_aon_clocks.clk_main_infra
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
connections:
{
rv_core_ibex.corei:
@@ -7839,13 +8259,20 @@
reset: rst_peri_ni
reset_connections:
{
- rst_peri_ni: sys_io_div4
+ rst_peri_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
connections:
{
main:
@@ -13061,30 +13488,57 @@
{
usbdev:
[
- usb
- sys_aon
- usbif
+ {
+ name: usb
+ domain: "0"
+ }
+ {
+ name: sys_aon
+ domain: "0"
+ }
+ {
+ name: usbif
+ domain: "0"
+ }
]
adc_ctrl_aon:
[
- sys_io_div4
- sys_aon
+ {
+ name: sys_io_div4
+ domain: Aon
+ }
+ {
+ name: sys_aon
+ domain: Aon
+ }
]
ast:
[
- lc_io_div4
+ {
+ name: lc_io_div4
+ domain: "0"
+ }
]
sensor_ctrl_aon:
[
- lc_io_div4
+ {
+ name: lc_io_div4
+ domain: Aon
+ }
]
entropy_src:
[
- sys
+ {
+ name: sys
+ domain: "0"
+ }
]
edn0:
[
- sys
+ {
+ name: sys
+ domain: "0"
+ }
]
}
}
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 4e33a23..1efb334 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -133,7 +133,7 @@
// domains: The power domains of a particular reset
// This is a list of of the supported power domains.
// Valid values are Aon and (power domain)0 ~ (power domain)1.
- // If no value is supplied, the default is only the Aon version.
+ // If no value is supplied, the default is specified by the power configuration.
//
// clk: related clock domain for synchronous release
// If type is "por", there is not related clock, since it is
@@ -339,7 +339,7 @@
clock_srcs: {clk_i: "io_div4", clk_slow_i: "aon"},
clock_group: "powerup",
reset_connections: {rst_ni: "por_io_div4", rst_slow_ni: "por_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40400000",
attr: "templated",
@@ -350,7 +350,7 @@
clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4"},
clock_group: "powerup",
reset_connections: {rst_ni: "por_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40410000",
attr: "templated",
},
@@ -360,7 +360,7 @@
clock_group: "powerup",
reset_connections: {rst_ni: "por_io_div4", rst_main_ni: "por", rst_io_ni: "por_io", rst_usb_ni: "por_usb"
rst_io_div2_ni: "por_io_div2", rst_io_div4_ni: "por_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40420000",
attr: "templated",
},
@@ -369,7 +369,7 @@
clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
clock_group: "infra",
reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40430000"
},
{ name: "adc_ctrl_aon",
@@ -378,7 +378,7 @@
clock_group: "peri",
reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon"},
clock_reset_export: ["ast"],
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40440000"
},
{ name: "pwm_aon",
@@ -386,7 +386,7 @@
clock_srcs: {clk_i: "io_div4", clk_core_i: "aon"},
clock_group: "powerup",
reset_connections: {rst_ni: "sys_io_div4", rst_core_ni: "sys_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40450000",
},
{ name: "pinmux_aon",
@@ -394,7 +394,7 @@
clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
clock_group: "powerup",
reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40460000",
attr: "templated",
},
@@ -403,7 +403,7 @@
clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
clock_group: "timers",
reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40470000",
attr: "templated",
},
@@ -422,7 +422,7 @@
clock_group: "secure",
clock_reset_export: ["ast"],
reset_connections: {rst_ni: "lc_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40490000",
attr: "reggen_top",
},
@@ -430,8 +430,8 @@
type: "sram_ctrl",
clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"},
clock_group: "infra",
- reset_connections: {rst_ni: "sys_io_div4", rst_otp_ni: "lc_io_div4"},
- domain: "Aon",
+ reset_connections: {rst_ni: "sys_io_div4", rst_otp_ni: "lc_io_div4"}
+ domain: ["Aon"],
param_decl: {
InstrExec: "0",
}
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 4601376..e9e4e87 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -17,15 +17,26 @@
reset: rst_main_ni
reset_connections:
{
- rst_main_ni: sys
- rst_fixed_ni: sys_io_div4
+ rst_main_ni:
+ {
+ name: sys
+ domain: "0"
+ }
+ rst_fixed_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_main_i: clkmgr_aon_clocks.clk_main_infra
clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
connections:
{
rv_core_ibex.corei:
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 2ccbd5e..214a9bb 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -16,13 +16,20 @@
reset: rst_peri_ni
reset_connections:
{
- rst_peri_ni: sys_io_div4
+ rst_peri_ni:
+ {
+ name: sys_io_div4
+ domain: "0"
+ }
}
clock_connections:
{
clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
}
- domain: "0"
+ domain:
+ [
+ "0"
+ ]
connections:
{
main:
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index 25aedf6..6c09ac0 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -236,7 +236,7 @@
clock_srcs: {clk_i: "io_div4", clk_slow_i: "aon"},
clock_group: "powerup",
reset_connections: {rst_ni: "por", rst_slow_ni: "por_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40400000",
attr: "templated",
@@ -247,7 +247,7 @@
clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4"},
clock_group: "powerup",
reset_connections: {rst_ni: "por_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40410000",
attr: "templated",
},
@@ -257,7 +257,7 @@
clock_group: "powerup",
reset_connections: {rst_ni: "por_io_div4", rst_main_ni: "por", rst_io_ni: "por_io", rst_usb_ni: "por_usb"
rst_io_div2_ni: "por_io_div2", rst_io_div4_ni: "por_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40420000",
attr: "templated",
},
@@ -266,7 +266,7 @@
clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
clock_group: "powerup",
reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40460000",
attr: "templated",
},
@@ -275,7 +275,7 @@
clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"},
clock_group: "timers",
reset_connections: {rst_ni: "sys_io_div4", rst_aon_ni: "sys_aon"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40470000",
attr: "templated",
},
@@ -285,7 +285,7 @@
clock_group: "secure",
clock_reset_export: ["ast"],
reset_connections: {rst_ni: "sys_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
base_addr: "0x40490000",
attr: "reggen_top",
},
@@ -294,7 +294,7 @@
clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"},
clock_group: "infra",
reset_connections: {rst_ni: "sys_io_div4", rst_otp_ni: "lc_io_div4"},
- domain: "Aon",
+ domain: ["Aon"],
param_decl: {
InstrExec: "0",
}
diff --git a/util/topgen/lib.py b/util/topgen/lib.py
index 663cf8b..047e926 100644
--- a/util/topgen/lib.py
+++ b/util/topgen/lib.py
@@ -308,10 +308,10 @@
return 'rst_shadowed_ni'
-def get_reset_path(top: object, reset: str, domain: str, shadow_sel = False):
+def get_reset_path(top: object, reset: str, shadow_sel = False):
"""Return the appropriate reset path given name
"""
- return top['resets'].get_path(reset, domain, shadow_sel)
+ return top['resets'].get_path(reset['name'], reset['domain'], shadow_sel)
def get_unused_resets(top):
diff --git a/util/topgen/merge.py b/util/topgen/merge.py
index 9d31b67..2f4fe7c 100644
--- a/util/topgen/merge.py
+++ b/util/topgen/merge.py
@@ -712,14 +712,14 @@
# shadowed determination
if block.has_shadowed_reg():
- top_resets.mark_reset_shadowed(primary_reset)
+ top_resets.mark_reset_shadowed(primary_reset['name'])
# domain determination
- if module['domain']:
+ for d in module["domain"]:
for r in block.clocking.items:
if r.reset:
reset = module['reset_connections'][r.reset]
- top_resets.add_reset_domain(reset, module['domain'])
+ top_resets.add_reset_domain(reset['name'], d)
# This code is here to ensure if amend_clocks/resets switched order
# everything would still work
diff --git a/util/topgen/templates/toplevel.sv.tpl b/util/topgen/templates/toplevel.sv.tpl
index f623e25..7a61454 100644
--- a/util/topgen/templates/toplevel.sv.tpl
+++ b/util/topgen/templates/toplevel.sv.tpl
@@ -407,9 +407,9 @@
% endfor
% for port, reset in m["reset_connections"].items():
% if lib.is_shadowed_port(block, port):
- .${lib.shadow_name(port)} (${lib.get_reset_path(top, reset, m['domain'], True)}),
+ .${lib.shadow_name(port)} (${lib.get_reset_path(top, reset, True)}),
% endif:
- .${port} (${lib.get_reset_path(top, reset, m['domain'])})${"," if not loop.last else ""}
+ .${port} (${lib.get_reset_path(top, reset)})${"," if not loop.last else ""}
% endfor
);
@@ -434,7 +434,7 @@
.${k} (${v}),
% endfor
% for port, reset in xbar["reset_connections"].items():
- .${port} (${lib.get_reset_path(top, reset, xbar["domain"])}),
+ .${port} (${lib.get_reset_path(top, reset)}),
% endfor
## Inter-module signal
diff --git a/util/topgen/validate.py b/util/topgen/validate.py
index 53413f4..cce14a3 100644
--- a/util/topgen/validate.py
+++ b/util/topgen/validate.py
@@ -187,7 +187,7 @@
}
module_optional = {
- 'domain': ['s', 'power domain, defaults to Domain0'],
+ 'domain': ['l', 'optional list of power domains, defaults to Domain0'],
'clock_reset_export': ['l', 'optional list with prefixes for exported '
'clocks and resets at the chip level'],
'attr': ['s', 'optional attribute indicating whether the IP is '
@@ -220,6 +220,14 @@
memory_added = {
}
+reset_connection_required = {
+ 'name': ['s', 'name of the connecting reset'],
+ 'domain': ['s', 'connected domain'],
+}
+
+reset_connection_optional = {}
+reset_connection_added = {}
+
# Supported PAD types.
# Needs to coincide with enum definition in prim_pad_wrapper_pkg.sv
@@ -300,15 +308,15 @@
(self.pages_per_bank <= Flash.max_pages_per_bank))
if not pow2_check:
- raise ValueError(f'flash power of 2 check failed. A supplied parameter '
+ raise ValueError('flash power of 2 check failed. A supplied parameter '
'is not power of 2')
if not limit_check:
- raise ValueError(f'flash number of banks and pages per bank too large')
+ raise ValueError('flash number of banks and pages per bank too large')
def _asdict(self):
return {
- 'banks': self.banks,
+ 'banks': self.banks,
'pages_per_bank': self.pages_per_bank,
'program_resolution': self.pgm_resolution_bytes,
'bytes_per_page': self.bytes_per_page,
@@ -316,6 +324,7 @@
'size': self.size
}
+
# Check to see if each module/xbar defined in top.hjson exists as ip/xbar.hjson
# Also check to make sure there are not multiple definitions of ip/xbar.hjson for each
# top level definition
@@ -653,6 +662,37 @@
log.info("%s %s resets are %s" %
(prefix, name, reset_signals))
+ # Check if reset connections are properly formatted
+ # There are two options
+ # The reset connection for a particular port must be a str
+ # The reset connection for a paritcular port must be a dict
+ # If value is a string, the module can only have ONE domain
+ # If value is a dict, it must have the keys name / domain, and the
+ # value of domain must match that defined for the module.
+ for port, reset in top["reset_connections"].items():
+ if isinstance(reset, str):
+ top["reset_connections"][port] = {}
+ top["reset_connections"][port]['name'] = reset
+
+ if len(top["domain"]) > 1:
+ raise ValueError(f"{top['name']} reset connection {reset} "
+ "has no assigned domain")
+ else:
+ top["reset_connections"][port]['domain'] = top["domain"][0]
+
+ if isinstance(reset, dict):
+ error += check_keys(reset,
+ reset_connection_required,
+ reset_connection_optional,
+ reset_connection_added,
+ 'dict structure for reset connections')
+
+ if reset['domain'] not in top["domain"]:
+ error += 1
+ log.error(f"domain {reset['domain']} defined for reset {reset['name']} "
+ f"is not a domain of {top['name']}")
+
+ # Check if the reset connections are fully populated
if len(top['reset_connections']) != len(reset_signals):
error += 1
log.error("%s %s mismatched number of reset ports and nets" %
@@ -670,8 +710,8 @@
[log.error("%s" % port) for port in missing_port]
missing_net = [
- net for port, net in top['reset_connections'].items()
- if net not in reset_nets
+ net['name'] for net in top['reset_connections'].values()
+ if net['name'] not in reset_nets
]
if missing_net:
@@ -735,35 +775,28 @@
for mem in top['memory']:
if mem['type'] == "eflash":
- raise ValueError(f'top level flash memory definition not supported. Please use '
+ raise ValueError('top level flash memory definition not supported. Please use '
'the flash embedded inside flash_ctrl instead. If there is a '
'need for top level flash memory, please file an issue.')
def check_power_domains(top):
- error = 0
# check that the default domain is valid
if top['power']['default'] not in top['power']['domains']:
- error += 1
- return error
+ raise ValueError(f"Default power domain {top['power']['default']} is "
+ "not a valid domain")
# Check that each module, xbar, memory has a power domain defined.
# If not, give it a default.
# If there is one defined, check that it is a valid definition
for end_point in top['module'] + top['memory'] + top['xbar']:
if 'domain' not in end_point:
- end_point['domain'] = top['power']['default']
+ end_point['domain'] = [top['power']['default']]
- if end_point['domain'] not in top['power']['domains']:
- log.error("{} defined invalid domain {}"
- .format(end_point['name'],
- end_point['domain']))
- error += 1
- return error
-
- # arrived without incident, return
- return error
+ for d in end_point['domain']:
+ if d not in top['power']['domains']:
+ raise ValueError(f"{end_point['name']} defined invalid domain {d}")
def check_modules(top, prefix):
@@ -845,7 +878,7 @@
check_flash(top)
# Power domain check
- error += check_power_domains(top)
+ check_power_domains(top)
# Clock / Reset check
error += check_clocks_resets(top, ipobjs, ip_idxs, xbarobjs, xbar_idxs)
