| commit | 7a2805857340ecd1ae19a271f0405e7ad7690935 | [log] [tgz] |
|---|---|---|
| author | Guillermo Maturana <maturana@google.com> | Thu Sep 08 16:40:25 2022 -0700 |
| committer | Timothy Trippel <5633066+timothytrippel@users.noreply.github.com> | Thu Sep 08 19:46:18 2022 -0700 |
| tree | 6a4329a99da479bbbaadc08dcfad1ae6d6cc4bbb | |
| parent | ec81414ee206d73d50902a680316e67ee1a3b01d [diff] |
[dv,top] Fix chip_sw_aon_timer_irq The test is requires an ISR to happen at within a certain number of cycles of the programmed timeout. It provides some slack to account for the time it takes to service the ISR, but that slack is too tight. This increases the slack from 500 to 600 CPU cycles. Fixes #14838 Signed-off-by: Guillermo Maturana <maturana@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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