[otbn,dv] Add missing wait for valid instruction in `otbn_ctrl_redun_vseq`
When `otbn_ctrl_redun_vseq` injects a fault into the bignum MAC op and
the instruction is not valid, no error will be raised, which is correct.
So this sequence must either wait for a valid instruction before
injecting a fault, or it must not signal an error to the model if it
injects an error during an invalid instruction. The latter would give
more coverage, since it would also test that injected faults for invalid
instructions do not result in an error. However, this sequence
currently waits for a valid instruction before injecting any of the
other faults.
Thus, this commit adds the missing wait for a valid instruction when
injecting faults into the bignum MAC op.
Signed-off-by: Andreas Kurth <adk@lowrisc.org>
diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv
index 58472c2..de19cbe 100644
--- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv
+++ b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_ctrl_redun_vseq.sv
@@ -155,9 +155,18 @@
5: begin
bit mac_en;
bit choose_err;
+ bit insn_valid;
`DV_WAIT(cfg.model_agent_cfg.vif.status == otbn_pkg::StatusBusyExecute)
cfg.clk_rst_vif.wait_clks($urandom_range(10, 100));
`DV_CHECK_STD_RANDOMIZE_FATAL(choose_err)
+ // Wait for valid instruction, because `otbn_core` only propagates bignum MAC predec errors
+ // for valid instructions.
+ `DV_SPINWAIT(
+ do begin
+ @(cfg.clk_rst_vif.cb);
+ uvm_hdl_read("tb.dut.u_otbn_core.insn_valid", insn_valid);
+ end while(!insn_valid);
+ )
case(choose_err)
0: begin
err_path = "tb.dut.u_otbn_core.u_otbn_mac_bignum.mac_en_i";
