| commit | 7a00ba3c0c680a7ad80e5cf6e16da3484703d6d0 | [log] [tgz] |
|---|---|---|
| author | Andreas Kurth <adk@lowrisc.org> | Fri Aug 19 18:56:27 2022 +0200 |
| committer | Canberk Topal <87007427+ctopal@users.noreply.github.com> | Mon Aug 22 13:35:26 2022 +0100 |
| tree | 65b5cdda923b113f490d713456d65d75eaaa853a | |
| parent | f000c1335596c1163d71302ff269d3dd261f07eb [diff] |
[otbn,dv] Add missing wait for valid instruction in `otbn_ctrl_redun_vseq` When `otbn_ctrl_redun_vseq` injects a fault into the bignum MAC op and the instruction is not valid, no error will be raised, which is correct. So this sequence must either wait for a valid instruction before injecting a fault, or it must not signal an error to the model if it injects an error during an invalid instruction. The latter would give more coverage, since it would also test that injected faults for invalid instructions do not result in an error. However, this sequence currently waits for a valid instruction before injecting any of the other faults. Thus, this commit adds the missing wait for a valid instruction when injecting faults into the bignum MAC op. Signed-off-by: Andreas Kurth <adk@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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