| commit | a842077c8c161586e01555cf85cb84f8da5cd6b7 | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Wed Jul 21 14:23:18 2021 -0700 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Mon Aug 02 13:15:09 2021 -0700 |
| tree | 2de7b9802557eaff66a95d1f6782559bda1a001c | |
| parent | e8d047c0f6ed77c492e8a00017db472884732b51 [diff] |
[spi_device] Add Last Read Address CSR This commit adds last read address accessed by the host system. While operating (SPI interface is in active), the CSR is not updated. The CSB signal is synchronized into the bus clock domain and the logic creates a pulse indicator. Then using the pulse signal, the logic latches readbuf address from SCK domain into bus clock domain. It does not create the CDC issue as the readbuf address won't be changed during CSb is high. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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