| commit | 5d45379e3d57f669cc27c6579a40394790cb0384 | [log] [tgz] |
|---|---|---|
| author | Michael Schaffner <msf@google.com> | Tue Jul 20 16:56:39 2021 -0700 |
| committer | Michael Schaffner <msf@google.com> | Wed Jul 21 10:43:40 2021 -0700 |
| tree | 671033c308741d08d4662350f8297c708d63a7b9 | |
| parent | 29dd5d69a763ba1768e3b5bdab7a7b65f7f28929 [diff] |
[prim_lfsr] Fix assertion issue occuring right after reset There are cases where the LFSR enable signal remains asserted by the instantiating design while in reset. In such a case, the NextStateCheck_A may erroneously fire in the first cycle after reset release due to a SystemVerilog scheduler peculiarity when the reset is synchronized with a reset synchronizer flop that releases the reset right on the active clock edge with 0 simulation delay. If this happens, the assertion body may be out of sync with the design, since the assertion disable_iff statement is NOT evaluated with a value sampled in the PREPONED region. In other words: when the assertion is evaluated in the OBSERVED region (after active and NBA), rst_ni may already read as 1 due to reset deassertion - however the flops in the design may not have seen that change yet, leading to an assertion failure because the flops have not yet changed state, whereas the assertion expects them to have changed state. There are a couple of possible solutions: 1) ignore the first clock tick after reset release by shifting the assertion by one clock tick to the right 2) use a sampled reset value for disable_iff (#sampled(!rst_ni)) 3) make sure the surrounding logic never asserts the LFSR enable signal while in reset. 4) make sure that there is an artificial propagation delay on all reset synchronizer outputs to shift reset deassertion away from the active clock edge. This patch implements solution 1) since this should ensure that the issue does not occur anymore (also in future designs that instantiate this prim). Signed-off-by: Michael Schaffner <msf@google.com>
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