| commit | 9aff7c2b71cad5e64bedb3dfb8e3c52b545f7019 | [log] [tgz] |
|---|---|---|
| author | Timothy Chen <timothytim@google.com> | Tue Apr 19 08:28:53 2022 -0700 |
| committer | Michael Schaffner <msf@google.com> | Fri Apr 22 16:28:29 2022 -0700 |
| tree | 29a473c4b94463ff8238388c30ccf16c75599622 | |
| parent | 432474a9f2c36811ae477b0a135f878852a28a61 [diff] |
[flash_ctrl] Switch phy arbitration mechanism to prim_arbiter_tree This is done a minor refactor PR to harden the arbitration function. The usage of prim_arbiter_tree is a little awkward here. The flash is able to support rd/program/erase from the controller, but only read from the host. So when arbitrating between the host and the controller, the "ready" signal is different because for reads, it only cares if the first stage of the read pipeline is ready, while for other operations we care about whether the entire flash is idle. To get around this, we use 'rd_stage_rdy' as the ready signal, since an idle flash also implies that rd_stage is ready. Further, since controller operations take longer, there is already an upstream entity that holds the attribute lines (address, partition, etc) steady, so there is no additional capturing of this information in the program/erase handlnig. This is however not true for read, as that works more in the traditional valid/ready handshake. Because of this, the arbiter data port is also not used since after the handshake there is no reason for the attribute lines to still be held. Signed-off-by: Timothy Chen <timothytim@google.com>
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