[Spi_host/doc] updated dv documentation and checklist accordign to V! review comments
Signed-off-by: Rasmus Madsen <rasmus.madsen@wdc.com>
diff --git a/hw/ip/spi_host/data/spi_host.prj.hjson b/hw/ip/spi_host/data/spi_host.prj.hjson
index df9959b..86cf37a 100644
--- a/hw/ip/spi_host/data/spi_host.prj.hjson
+++ b/hw/ip/spi_host/data/spi_host.prj.hjson
@@ -12,7 +12,7 @@
version: "0.5",
life_stage: "L1",
design_stage: "D1",
- verification_stage: "V0",
+ verification_stage: "V1",
dif_stage: "S0",
}
]
diff --git a/hw/ip/spi_host/data/spi_host_testplan.hjson b/hw/ip/spi_host/data/spi_host_testplan.hjson
index 634b9e9..3d8c21c 100644
--- a/hw/ip/spi_host/data/spi_host_testplan.hjson
+++ b/hw/ip/spi_host/data/spi_host_testplan.hjson
@@ -180,7 +180,7 @@
- verify that the DUT support both half and full duplex in standard mode.
'''
milestone: V2
- tests: []
+ tests: ["spi_host_smoke"]
}
{
name: tx_rx_only
@@ -194,7 +194,7 @@
- verify that the DUT does not drain the tx fifo in rx only mode
'''
milestone: V2
- tests: []
+ tests: ["spi_host_smoke"]
}
{
name: stress_all
@@ -213,6 +213,21 @@
milestone: V2
tests: []
}
+ {
+ name: winbond
+ desc: '''
+ Replace SPI agent with the Winbond Flash model
+
+ Stimulus:
+ - constraint the Sequence to create welformed transactions that the model understands
+
+ Checking:
+ - Verify the DUT against the WindBond bfm by making the spi agent passive
+ to verify that we comply with the spi targeted for opentitan
+ '''
+ milestone: V2
+ tests: []
+ }
]
covergroups: [
{
@@ -326,11 +341,38 @@
'''
}
{
+ name: interrupt_cg
+ desc: '''
+ - check that we see all scenarios that can cause an interrupt and that the interrupts is fired.
+ - also check we can clear the interrupt
+ '''
+ }
+ {
name: different_ch_settings_cg
desc: '''
- - check that multiple end points was running at different speeds concurrently.
- - collect coverage that multiple SPI endpoints was run with different config opts
+ - Check that multiple end points was running at different speeds concurrently.
+ - Collect coverage that multiple SPI endpoints was run with different config opts
'''
- }
+ }
+ {
+ name: stall_cg
+ desc: '''
+ - Check that the DUT stalls if a command is configured to transmit data but the tx fifo is empty
+ - check that the data is transmitted when written to the TX fifo after a stall
+ '''
+ }
+ {
+ name: num_segment_cg
+ desc: '''
+ - Check that the DUT only transmits what is in a command even if more segments are in the TX FIFO
+ '''
+ }
+ {
+ name: segment_speed_cg
+ desc: '''
+ - Check that we test with transactions that uses different speeds
+ i.e first segment in standard mode, followed by segments in dual or quad mode
+ '''
+ }
]
}
diff --git a/hw/ip/spi_host/doc/checklist.md b/hw/ip/spi_host/doc/checklist.md
index d736300..0842edf 100644
--- a/hw/ip/spi_host/doc/checklist.md
+++ b/hw/ip/spi_host/doc/checklist.md
@@ -140,15 +140,15 @@
Tests | [SIM_SMOKE_TEST_PASSING][] | DONE |
Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | DONE |
Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |
-Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium (signoff), VCS (alt)
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | DONE | Xcelium (signoff), VCS (alt)
Regression | [SIM_SMOKE_REGRESSION_SETUP][] | DONE |
-Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | TBD When 8856 goes in
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | DONE |
Regression | [FPV_REGRESSION_SETUP][] | N/A |
Coverage | [SIM_COVERAGE_MODEL_ADDED][] | DONE |
Code Quality | [TB_LINT_SETUP][] | DONE |
Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A |
Review | [DESIGN_SPEC_REVIEWED][] | DONE |
-Review | [TESTPLAN_REVIEWED][] | Not Started | TBD in V1 review
+Review | [TESTPLAN_REVIEWED][] | DONE |
Review | [STD_TEST_CATEGORIES_PLANNED][] | DONE |
Review | [V2_CHECKLIST_SCOPED][] | Not Started |
diff --git a/hw/ip/spi_host/doc/dv/index.md b/hw/ip/spi_host/doc/dv/index.md
index c6bfc99..d02df31 100644
--- a/hw/ip/spi_host/doc/dv/index.md
+++ b/hw/ip/spi_host/doc/dv/index.md
@@ -44,15 +44,90 @@
### Compile-time configurations
[list compile time configurations, if any and what are they used for]
```systemverilog
-TODO
+ // sets the number of spi devices
+ parameter int NumCS = 1;
```
+Currently there verification only covers NumCS = 1 since this is the configuration that will be used in tapeout.
### Global types & methods
All common types and methods defined at the package level can be found in
`spi_host_env_pkg`. Some of them in use are:
```systemverilog
-TODO
+ // types
+ typedef enum int {
+ SpiHostError = 0,
+ SpiHostEvent = 1,
+ NumSpiHostIntr = 2
+ } spi_host_intr_e;
+
+ typedef enum int {
+ TxFifo = 0,
+ RxFifo = 1,
+ AllFifos = 2
+ } spi_host_fifo_e;
+
+ typedef enum {
+ Command,
+ Address,
+ Dummy,
+ Data
+ } spi_segment_type_e;
+
+ // spi config
+ typedef struct {
+ // configopts register fields
+ rand bit cpol[SPI_HOST_NUM_CS];
+ rand bit cpha[SPI_HOST_NUM_CS];
+ rand bit fullcyc[SPI_HOST_NUM_CS];
+ rand bit [3:0] csnlead[SPI_HOST_NUM_CS];
+ rand bit [3:0] csntrail[SPI_HOST_NUM_CS];
+ rand bit [3:0] csnidle[SPI_HOST_NUM_CS];
+ rand bit [15:0] clkdiv[SPI_HOST_NUM_CS];
+ } spi_host_configopts_t;
+
+ typedef struct {
+ // csid register
+ rand bit [31:0] csid;
+ // control register fields
+ rand bit [8:0] tx_watermark;
+ rand bit [6:0] rx_watermark;
+ } spi_host_ctrl_t;
+
+ // spi direction
+ typedef enum bit [1:0] {
+ None = 2'b00,
+ RxOnly = 2'b01,
+ TxOnly = 2'b10,
+ Bidir = 2'b11
+ } spi_dir_e;
+
+ typedef struct {
+ // command register fields
+ rand spi_mode_e mode;
+ rand spi_dir_e direction;
+ rand bit csaat;
+ rand bit [8:0] len;
+ } spi_host_command_t;
+
+ typedef struct packed {
+ bit status;
+ bit active;
+ bit txfull;
+ bit txempty;
+ bit txstall;
+ bit tx_wm;
+ bit rxfull;
+ bit rxempty;
+ bit rxstall;
+ bit byteorder;
+ bit rsv_0;
+ bit rx_wm;
+ bit [19:16] rsv_1;
+ bit [15:8] rx_qd;
+ bit [7:0] tx_qd;
+ } spi_host_status_t;
```
+
### TL_agent
SPI_HOST testbench instantiates (already handled in CIP base env)
[tl_agent]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
