commit 78bb2aefea4cfb100ea4b845cb674595796b0586
author Tom Roberts <tomroberts@lowrisc.org> Wed Jun 03 15:24:22 2020 +0100
committer Philipp Wagner <mail@philipp-wagner.com> Wed Jun 03 16:31:04 2020 +0100
tree 1031e43f262fc3342b081332b47c17826d7163cf
parent d1bccc51d300e437029a7c557e2f37916f68b928

[ibex] Add new parameters

- Add new parameters for ICache and security features but leave them
  disabled for now (in master)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>

hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv

diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index b2ef194..7d6c65e 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -19,7 +19,10 @@
   parameter bit          BranchTargetALU          = 1,
   parameter bit          WritebackStage           = 1,
   parameter              MultiplierImplementation = "single-cycle",
+  parameter bit          ICache                   = 1'b0,
+  parameter bit          ICacheECC                = 1'b0,
   parameter bit          DbgTriggerEn             = 1'b1,
+  parameter bit          SecureIbex               = 1'b0,
   parameter int unsigned DmHaltAddr               = 32'h1A110800,
   parameter int unsigned DmExceptionAddr          = 32'h1A110808,
   parameter bit          PipeLine                 = 0
@@ -126,7 +129,10 @@
     .BranchTargetALU          ( BranchTargetALU          ),
     .WritebackStage           ( WritebackStage           ),
     .MultiplierImplementation ( MultiplierImplementation ),
+    .ICache                   ( ICache                   ),
+    .ICacheECC                ( ICacheECC                ),
     .DbgTriggerEn             ( DbgTriggerEn             ),
+    .SecureIbex               ( SecureIbex               ),
     .DmHaltAddr               ( DmHaltAddr               ),
     .DmExceptionAddr          ( DmExceptionAddr          )
   ) u_core (

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 21dba85..77307c6 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -244,7 +244,10 @@
     .BranchTargetALU          (1),
     .WritebackStage           (1),
     .MultiplierImplementation ("single-cycle"),
+    .ICache                   (0),
+    .ICacheECC                (0),
     .DbgTriggerEn             (1),
+    .SecureIbex               (0),
     .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
     .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
     .PipeLine                 (IbexPipeLine)

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index e1d9674..874ee99 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -278,7 +278,10 @@
     .BranchTargetALU          (1),
     .WritebackStage           (1),
     .MultiplierImplementation ("single-cycle"),
+    .ICache                   (0),
+    .ICacheECC                (0),
     .DbgTriggerEn             (1),
+    .SecureIbex               (0),
     .DmHaltAddr               (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
     .DmExceptionAddr          (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
     .PipeLine                 (IbexPipeLine)