[kmac] CFG to shadow register
This commit changes CFG to shadowed register type and connect the
storage error to the alert and update error to the error interrupt.
Co-Authored-by: Cindy Chen <chencindy@google.com>
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/hw/ip/kmac/data/kmac.hjson b/hw/ip/kmac/data/kmac.hjson
index be9b504..7b91e46 100644
--- a/hw/ip/kmac/data/kmac.hjson
+++ b/hw/ip/kmac/data/kmac.hjson
@@ -23,11 +23,16 @@
}
]
alert_list: [
- { name: "fatal_fault",
+ { name: "fatal_fault_err",
desc: '''
- This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected or the shadow registers storage error occurs.
'''
}
+ { name: "recov_operation_err"
+ desc: '''
+ Alert for KMAC operation error. It occurs when the shadow registers have update errors.
+ '''
+ }
],
param_list: [
{ name: "EnMasking"
@@ -159,16 +164,20 @@
// by software.
"excl:CsrNonInitTests:CsrExclCheck"]
} // R : CFG_REGWEN
- { name: "CFG"
+ { name: "CFG_SHADOWED"
desc: '''KMAC Configuration register.
This register is updated when the hashing engine is in Idle.
If the software updates the register while the engine computes, the
updated value will be discarded.
'''
- regwen: "CFG_REGWEN"
+ regwen: "CFG_REGWEN"
swaccess: "rw"
hwaccess: "hro"
+ shadowed: "true"
+ hwqe: "true"
+ update_err_alert: "recov_operation_err"
+ storage_err_alert: "fatal_fault_err"
fields: [
{ bits: "0"
name: "kmac_en"
@@ -178,7 +187,9 @@
with the secret key.
'''
tags: [// don't enable kmac and sha data paths - we will do that in functional tests
- "excl:CsrNonInitTests:CsrExclWrite"]
+ "excl:CsrNonInitTests:CsrExclWrite",
+ "shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_kmac_en"
+ ]
} // f: kmac_en
{ bits: "3:1"
name: "kstrength"
@@ -211,6 +222,7 @@
desc: "512 bit strength. Keccak rate is 576 bit"
}
]
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_kstrength"]
} // f: strength
{ bits: "5:4"
name: "mode"
@@ -234,6 +246,7 @@
desc: "cSHAKE hashing mode. It appends `00` to the end of msg"
}
]
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_mode"]
} // f: mode
{ bits: "8"
name: "msg_endianness"
@@ -250,6 +263,7 @@
word granularity.
'''
resval: "0"
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_msg_endianness"]
} // f: msg_endianness
{ bits: "9"
name: "state_endianness"
@@ -262,6 +276,7 @@
This setting does not affect how the state is interpreted
during computation.
'''
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_state_endianness"]
} // f: state_endianness
{ bits: "12"
name: "sideload"
@@ -272,6 +287,7 @@
configuration when KeyMgr initiates the KMAC operation for
Key Derivation Function (KDF).
'''
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_sideload"]
} // f: sideload
{ bits: "17:16"
name: entropy_mode
@@ -302,6 +318,7 @@
interface'''
}
]
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_entropy_mode"]
} // f: entropy_mode
{ bits: "19"
name: entropy_fast_process
@@ -312,6 +329,7 @@
expand the entropy when it is consumed. Only it refreshes the
entropy while processing the secret key block.
'''
+ tags: ["shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_entropy_fast_process"]
} // f: entropy_fast_process
{ bits: "24"
name: entropy_ready
@@ -320,9 +338,9 @@
Software sets this field to allow the entropy generator in KMAC to
fetch the entropy and run.
'''
- hwaccess: "hrw"
tags: [// Randomly write mem will cause this reg updated by design
- "excl:CsrAllTests:CsrExclWrite"]
+ "excl:CsrAllTests:CsrExclWrite",
+ "shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_entropy_ready"]
} // f: entropy_ready
{ bits: "25"
name: err_processed
@@ -330,11 +348,15 @@
Error handling state, SW may process the error based on
ERR_CODE, then let FSM back to the reset state
'''
- hwaccess: "hrw"
tags: [// Randomly write mem will cause this reg updated by design
- "excl:CsrNonInitTests:CsrExclCheck"]
+ "excl:CsrNonInitTests:CsrExclCheck",
+ "shadowed_reg_path:u_cfg_reg_shadowed.u_cfg_reg_shadowed_err_processed"]
} // f: err_processed
]
+ tags: [
+ "excl:CsrNonInitTests:CsrExclWriteCheck",
+ "shadowed_reg_path:u_cfg_reg_shadowed"
+ ]
} // R: CFG
{ name: "CMD"
desc: '''KMAC/ SHA3 command register.
diff --git a/hw/ip/kmac/dv/env/kmac_env_pkg.sv b/hw/ip/kmac/dv/env/kmac_env_pkg.sv
index cdc68aa..d414b1b 100644
--- a/hw/ip/kmac/dv/env/kmac_env_pkg.sv
+++ b/hw/ip/kmac/dv/env/kmac_env_pkg.sv
@@ -63,8 +63,8 @@
parameter int MAX_ENCODE_WIDTH = 2040;
// alerts
- parameter uint NUM_ALERTS = 1;
- parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
+ parameter uint NUM_ALERTS = 2;
+ parameter string LIST_OF_ALERTS[] = {"fatal_fault_err", "recov_operation_err"};
parameter uint NUM_EDN = 1;
diff --git a/hw/ip/kmac/dv/env/kmac_scoreboard.sv b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
index fd934c9..5aab558 100644
--- a/hw/ip/kmac/dv/env/kmac_scoreboard.sv
+++ b/hw/ip/kmac/dv/env/kmac_scoreboard.sv
@@ -463,7 +463,7 @@
end
StError: begin
- if (`gmv(ral.cfg.err_processed)) begin
+ if (`gmv(ral.cfg_shadowed.err_processed)) begin
app_st = StIdle;
end else begin
app_st = StError;
@@ -1886,7 +1886,7 @@
virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
uvm_reg csr;
- dv_base_reg check_locked_reg;
+ dv_base_reg dv_base_csr;
string csr_name = "";
@@ -1908,7 +1908,7 @@
if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin
csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr);
`DV_CHECK_NE_FATAL(csr, null)
- `downcast(check_locked_reg, csr)
+ `downcast(dv_base_csr, csr)
csr_name = csr.get_name();
@@ -1922,7 +1922,7 @@
// - entropy_seed_upper
// - key_len
// if writes to these csrs are seen, must check that they are not locked first.
- if (ral.cfg_regwen.locks_reg_or_fld(check_locked_reg) &&
+ if (ral.cfg_regwen.locks_reg_or_fld(dv_base_csr) &&
`gmv(ral.cfg_regwen) == 0) return;
void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask)));
@@ -2003,7 +2003,13 @@
"cfg_regwen": begin
// do nothing
end
- "cfg": begin
+ "cfg_shadowed": begin
+ // don't continue if the write is shadow register's first write,
+ // or the second write has update error
+ if (addr_phase_write &&
+ (dv_base_csr.is_staged() || dv_base_csr.get_shadow_update_err())) begin
+ return;
+ end
if (addr_phase_write) begin
// don't continue if the KMAC is currently operating
if (!sha3_idle) begin
@@ -2311,7 +2317,7 @@
// This way we can also preserve little-endian ordering.
for (int i = 0; i < TL_DBW; i++) begin
if (item.a_mask[i]) begin
- masked_data = `gmv(ral.cfg.msg_endianness) ? {full_data[i], masked_data} :
+ masked_data = `gmv(ral.cfg_shadowed.msg_endianness) ? {full_data[i], masked_data} :
{masked_data, full_data[i]};
end
end
@@ -2349,7 +2355,7 @@
`uvm_info(`gfn, $sformatf("state read mask: 0b%0b", state_mask), UVM_HIGH)
`uvm_info(`gfn, $sformatf("digest_word: 0x%0x", digest_word), UVM_HIGH)
- if (`gmv(ral.cfg.state_endianness)) begin
+ if (`gmv(ral.cfg_shadowed.state_endianness)) begin
digest_word = {<< byte {digest_word}};
state_mask = {<< bit {state_mask}};
@@ -2570,8 +2576,8 @@
// sample configuration coverage, as only now do we know which KMAC variant is used
// (xof/non-xof)
cov.sample_cfg(kmac_en, xof_en, strength, hash_mode, key_len,
- `gmv(ral.cfg.msg_endianness), `gmv(ral.cfg.state_endianness),
- `gmv(ral.cfg.sideload), entropy_mode, entropy_fast_process);
+ `gmv(ral.cfg_shadowed.msg_endianness), `gmv(ral.cfg_shadowed.state_endianness),
+ `gmv(ral.cfg_shadowed.sideload), entropy_mode, entropy_fast_process);
// sample coverage on the digest length
if (cfg.en_cov) begin
@@ -2669,7 +2675,7 @@
if (kmac_en) begin
// Calculate the unmasked key
- exp_keys = `gmv(ral.cfg.sideload) ? keymgr_keys : keys;
+ exp_keys = `gmv(ral.cfg_shadowed.sideload) ? keymgr_keys : keys;
for (int i = 0; i < key_word_len; i++) begin
if (cfg.enable_masking) begin
unmasked_key.push_back(exp_keys[0][i] ^ exp_keys[1][i]);
diff --git a/hw/ip/kmac/dv/env/seq_lib/kmac_base_vseq.sv b/hw/ip/kmac/dv/env/seq_lib/kmac_base_vseq.sv
index 33ba2dd..344d34e 100644
--- a/hw/ip/kmac/dv/env/seq_lib/kmac_base_vseq.sv
+++ b/hw/ip/kmac/dv/env/seq_lib/kmac_base_vseq.sv
@@ -273,17 +273,17 @@
`uvm_info(`gfn, $sformatf("intr[KmacErr] = %0b", enable_intr[KmacErr]), UVM_HIGH)
// setup CFG csr with default random values
- ral.cfg.kmac_en.set(kmac_en);
- ral.cfg.kstrength.set(strength);
- ral.cfg.mode.set(hash_mode);
- ral.cfg.msg_endianness.set(msg_endian);
- ral.cfg.state_endianness.set(state_endian);
- ral.cfg.sideload.set(en_sideload);
- ral.cfg.entropy_mode.set(entropy_mode);
- ral.cfg.entropy_fast_process.set(entropy_fast_process);
- ral.cfg.entropy_ready.set(entropy_ready);
- ral.cfg.err_processed.set(1'b0);
- csr_update(.csr(ral.cfg));
+ ral.cfg_shadowed.kmac_en.set(kmac_en);
+ ral.cfg_shadowed.kstrength.set(strength);
+ ral.cfg_shadowed.mode.set(hash_mode);
+ ral.cfg_shadowed.msg_endianness.set(msg_endian);
+ ral.cfg_shadowed.state_endianness.set(state_endian);
+ ral.cfg_shadowed.sideload.set(en_sideload);
+ ral.cfg_shadowed.entropy_mode.set(entropy_mode);
+ ral.cfg_shadowed.entropy_fast_process.set(entropy_fast_process);
+ ral.cfg_shadowed.entropy_ready.set(entropy_ready);
+ ral.cfg_shadowed.err_processed.set(1'b0);
+ csr_update(.csr(ral.cfg_shadowed));
// setup KEY_LEN csr
csr_wr(.ptr(ral.key_len), .value(key_len));
@@ -328,19 +328,19 @@
kmac_err_type inside {kmac_pkg::ErrIncorrectEntropyMode,
kmac_pkg::ErrWaitTimerExpired}) begin
cfg.clk_rst_vif.wait_clks($urandom_range(10, 50));
- ral.cfg.err_processed.set(1);
+ ral.cfg_shadowed.err_processed.set(1);
if (kmac_err_type == kmac_pkg::ErrIncorrectEntropyMode) begin
`DV_CHECK_MEMBER_RANDOMIZE_FATAL(entropy_mode)
- ral.cfg.entropy_mode.set(entropy_mode);
+ ral.cfg_shadowed.entropy_mode.set(entropy_mode);
end
- csr_update(.csr(ral.cfg));
+ csr_update(.csr(ral.cfg_shadowed));
// Need to pulse `entropy_ready` once we signal that SW has finished processing
// the entropy-related errors, otherwise FSM will be infinitely looping in Reset state
- csr_wr(.ptr(ral.cfg.entropy_ready), .value(1'b1));
+ csr_wr(.ptr(ral.cfg_shadowed.entropy_ready), .value(1'b1));
end else if (kmac_err_type == kmac_pkg::ErrKeyNotValid) begin
- ral.cfg.err_processed.set(1);
- csr_update(.csr(ral.cfg));
+ ral.cfg_shadowed.err_processed.set(1);
+ csr_update(.csr(ral.cfg_shadowed));
end
`uvm_info(`gfn, "Finished checking error", UVM_HIGH)
endtask
diff --git a/hw/ip/kmac/dv/tb.sv b/hw/ip/kmac/dv/tb.sv
index 80397ce..8d212f3 100644
--- a/hw/ip/kmac/dv/tb.sv
+++ b/hw/ip/kmac/dv/tb.sv
@@ -14,7 +14,7 @@
`include "uvm_macros.svh"
`include "dv_macros.svh"
- wire clk, rst_n;
+ wire clk, rst_n, rst_shadowed_n;
wire devmode;
wire idle;
wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
@@ -26,6 +26,7 @@
// interfaces
clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
+ rst_shadowed_if rst_shadowed_if(.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n));
pins_if #(1) devmode_if(devmode);
pins_if #(1) idle_if(idle);
@@ -45,8 +46,9 @@
// dut
kmac #(.EnMasking(`EN_MASKING), .ReuseShare(`REUSE_SHARE)) dut (
- .clk_i (clk ),
- .rst_ni (rst_n ),
+ .clk_i (clk ),
+ .rst_ni (rst_n ),
+ .rst_shadowed_ni (rst_shadowed_n ),
// TLUL interface
.tl_i (tl_if.h2d ),
@@ -95,6 +97,8 @@
// drive clk and rst_n from clk_if
clk_rst_if.set_active();
uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
+ uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif",
+ rst_shadowed_if);
uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
diff --git a/hw/ip/kmac/rtl/kmac.sv b/hw/ip/kmac/rtl/kmac.sv
index e6103a3..9956b1e 100644
--- a/hw/ip/kmac/rtl/kmac.sv
+++ b/hw/ip/kmac/rtl/kmac.sv
@@ -36,6 +36,8 @@
input clk_i,
input rst_ni,
+ input rst_shadowed_ni,
+
input clk_edn_i,
input rst_edn_ni,
@@ -267,6 +269,9 @@
logic err_processed;
+ logic alert_fatal, alert_recov_operation;
+ logic alert_intg_err;
+
//////////////////////////////////////
// Connecting Register IF to logics //
//////////////////////////////////////
@@ -464,12 +469,10 @@
&& reg2hw.cmd.hash_cnt_clr.q;
// Entropy config
- assign entropy_ready = reg2hw.cfg.entropy_ready.q;
- assign entropy_mode = entropy_mode_e'(reg2hw.cfg.entropy_mode.q);
- assign entropy_fast_process = reg2hw.cfg.entropy_fast_process.q;
-
- assign hw2reg.cfg.entropy_ready.de = entropy_ready;
- assign hw2reg.cfg.entropy_ready.d = 1'b 0; // always clear when ready
+ assign entropy_ready = reg2hw.cfg_shadowed.entropy_ready.q
+ & reg2hw.cfg_shadowed.entropy_ready.qe;
+ assign entropy_mode = entropy_mode_e'(reg2hw.cfg_shadowed.entropy_mode.q);
+ assign entropy_fast_process = reg2hw.cfg_shadowed.entropy_fast_process.q;
`ASSERT(EntropyReadyLatched_A, $rose(entropy_ready) |=> !entropy_ready)
@@ -486,17 +489,16 @@
end
// Clear the error processed
- assign err_processed = reg2hw.cfg.err_processed.q;
- assign hw2reg.cfg.err_processed.de = err_processed;
- assign hw2reg.cfg.err_processed.d = 1'b 0;
+ assign err_processed = reg2hw.cfg_shadowed.err_processed.q
+ & reg2hw.cfg_shadowed.err_processed.qe;
// Make sure the field has latch in reg_top
`ASSERT(ErrProcessedLatched_A, $rose(err_processed) |=> !err_processed)
// App mode, strength, kmac_en
- assign reg_kmac_en = reg2hw.cfg.kmac_en.q;
- assign reg_sha3_mode = sha3_pkg::sha3_mode_e'(reg2hw.cfg.mode.q);
- assign reg_keccak_strength = sha3_pkg::keccak_strength_e'(reg2hw.cfg.kstrength.q);
+ assign reg_kmac_en = reg2hw.cfg_shadowed.kmac_en.q;
+ assign reg_sha3_mode = sha3_pkg::sha3_mode_e'(reg2hw.cfg_shadowed.mode.q);
+ assign reg_keccak_strength = sha3_pkg::keccak_strength_e'(reg2hw.cfg_shadowed.kstrength.q);
///////////////
// Interrupt //
@@ -545,7 +547,8 @@
logic event_error;
assign event_error = sha3_err.valid | app_err.valid
- | entropy_err.valid | errchecker_err.valid;
+ | entropy_err.valid | errchecker_err.valid
+ ;
// Assing error code to the register
assign hw2reg.err_code.de = event_error;
@@ -768,8 +771,10 @@
// big-endian, it needs to be swapped to little-endian to maintain the
// order. Internal SHA3(Keccak) runs in little-endian in contrast to HMAC
// So, no endian-swap after prim_packer.
- assign tlram_wdata_endian = conv_endian32(tlram_wdata, reg2hw.cfg.msg_endianness.q);
- assign tlram_wmask_endian = conv_endian32(tlram_wmask, reg2hw.cfg.msg_endianness.q);
+ assign tlram_wdata_endian = conv_endian32(tlram_wdata,
+ reg2hw.cfg_shadowed.msg_endianness.q);
+ assign tlram_wmask_endian = conv_endian32(tlram_wmask,
+ reg2hw.cfg_shadowed.msg_endianness.q);
// TL Adapter
tlul_adapter_sram #(
@@ -868,7 +873,7 @@
.reg_state_o (reg_state),
// Configuration: Sideloaded Key
- .keymgr_key_en_i (reg2hw.cfg.sideload.q),
+ .keymgr_key_en_i (reg2hw.cfg_shadowed.sideload.q),
.absorbed_i (sha3_absorbed), // from SHA3
.absorbed_o (event_absorbed), // to SW
@@ -928,7 +933,7 @@
.state_i (reg_state),
- .endian_swap_i (reg2hw.cfg.state_endianness.q)
+ .endian_swap_i (reg2hw.cfg_shadowed.state_endianness.q)
);
// Error checker
@@ -1065,9 +1070,12 @@
// Register top
logic [NumAlerts-1:0] alert_test, alerts;
+
+ logic shadowed_storage_err, shadowed_update_err;
kmac_reg_top u_reg (
.clk_i,
.rst_ni,
+ .rst_shadowed_ni,
.tl_i,
.tl_o,
@@ -1077,16 +1085,67 @@
.reg2hw,
.hw2reg,
- .intg_err_o(alerts[0]),
+ .intg_err_o(alert_intg_err),
.devmode_i (devmode)
);
+ assign shadowed_storage_err = |{
+ reg2hw.cfg_shadowed.kmac_en.err_storage ,
+ reg2hw.cfg_shadowed.kstrength.err_storage ,
+ reg2hw.cfg_shadowed.mode.err_storage ,
+ reg2hw.cfg_shadowed.msg_endianness.err_storage ,
+ reg2hw.cfg_shadowed.state_endianness.err_storage ,
+ reg2hw.cfg_shadowed.sideload.err_storage ,
+ reg2hw.cfg_shadowed.entropy_mode.err_storage ,
+ reg2hw.cfg_shadowed.entropy_fast_process.err_storage,
+ reg2hw.cfg_shadowed.entropy_ready.err_storage ,
+ reg2hw.cfg_shadowed.err_processed.err_storage
+ };
+
+ assign shadowed_update_err = |{
+ reg2hw.cfg_shadowed.kmac_en.err_update ,
+ reg2hw.cfg_shadowed.kstrength.err_update ,
+ reg2hw.cfg_shadowed.mode.err_update ,
+ reg2hw.cfg_shadowed.msg_endianness.err_update ,
+ reg2hw.cfg_shadowed.state_endianness.err_update ,
+ reg2hw.cfg_shadowed.sideload.err_update ,
+ reg2hw.cfg_shadowed.entropy_mode.err_update ,
+ reg2hw.cfg_shadowed.entropy_fast_process.err_update ,
+ reg2hw.cfg_shadowed.entropy_ready.err_update ,
+ reg2hw.cfg_shadowed.err_processed.err_update
+ };
+
+ logic unused_cfg_shadowed_qe;
+ assign unused_cfg_shadowed_qe = ^{
+ reg2hw.cfg_shadowed.kmac_en.qe ,
+ reg2hw.cfg_shadowed.kstrength.qe ,
+ reg2hw.cfg_shadowed.mode.qe ,
+ reg2hw.cfg_shadowed.msg_endianness.qe ,
+ reg2hw.cfg_shadowed.state_endianness.qe ,
+ reg2hw.cfg_shadowed.sideload.qe ,
+ reg2hw.cfg_shadowed.entropy_mode.qe ,
+ reg2hw.cfg_shadowed.entropy_fast_process.qe
+ };
+
// Alerts
assign alert_test = {
- reg2hw.alert_test.q &
- reg2hw.alert_test.qe
+ reg2hw.alert_test.recov_operation_err.q
+ & reg2hw.alert_test.recov_operation_err.qe, // [1]
+ reg2hw.alert_test.fatal_fault_err.q
+ & reg2hw.alert_test.fatal_fault_err.qe // [0]
};
+ assign alerts = {
+ alert_recov_operation, // Alerts[1]
+ alert_fatal // Alerts[0]
+ };
+
+ assign alert_recov_operation = shadowed_update_err;
+
+ assign alert_fatal = shadowed_storage_err
+ | alert_intg_err
+ ;
+
for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
prim_alert_sender #(
.AsyncOn(AlertAsyncOn[i]),
@@ -1095,7 +1154,7 @@
.clk_i,
.rst_ni,
.alert_test_i ( alert_test[i] ),
- .alert_req_i ( alerts[0] ),
+ .alert_req_i ( alerts[i] ),
.alert_ack_o ( ),
.alert_state_o ( ),
.alert_rx_i ( alert_rx_i[i] ),
diff --git a/hw/ip/kmac/rtl/kmac_pkg.sv b/hw/ip/kmac/rtl/kmac_pkg.sv
index 86d568a..c91d9b8 100644
--- a/hw/ip/kmac/rtl/kmac_pkg.sv
+++ b/hw/ip/kmac/rtl/kmac_pkg.sv
@@ -269,7 +269,10 @@
ErrIncorrectFunctionName = 8'h 07,
// ErrSwCmdSequence
- ErrSwCmdSequence = 8'h 08
+ ErrSwCmdSequence = 8'h 08,
+
+ // Error Shadow register update
+ ErrShadowRegUpdate = 8'h C0
} err_code_e;
typedef struct packed {
diff --git a/hw/ip/kmac/rtl/kmac_reg_pkg.sv b/hw/ip/kmac/rtl/kmac_reg_pkg.sv
index e136ff7..423fdae 100644
--- a/hw/ip/kmac/rtl/kmac_reg_pkg.sv
+++ b/hw/ip/kmac/rtl/kmac_reg_pkg.sv
@@ -10,7 +10,7 @@
parameter int NumWordsKey = 16;
parameter int NumWordsPrefix = 11;
parameter int unsigned HashCntW = 10;
- parameter int NumAlerts = 1;
+ parameter int NumAlerts = 2;
// Address widths within the block
parameter int BlockAw = 12;
@@ -59,42 +59,78 @@
} kmac_reg2hw_intr_test_reg_t;
typedef struct packed {
- logic q;
- logic qe;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_fault_err;
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_operation_err;
} kmac_reg2hw_alert_test_reg_t;
typedef struct packed {
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} kmac_en;
struct packed {
logic [2:0] q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} kstrength;
struct packed {
logic [1:0] q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} mode;
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} msg_endianness;
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} state_endianness;
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} sideload;
struct packed {
logic [1:0] q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} entropy_mode;
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} entropy_fast_process;
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} entropy_ready;
struct packed {
logic q;
+ logic qe;
+ logic err_update;
+ logic err_storage;
} err_processed;
- } kmac_reg2hw_cfg_reg_t;
+ } kmac_reg2hw_cfg_shadowed_reg_t;
typedef struct packed {
struct packed {
@@ -176,17 +212,6 @@
typedef struct packed {
struct packed {
logic d;
- logic de;
- } entropy_ready;
- struct packed {
- logic d;
- logic de;
- } err_processed;
- } kmac_hw2reg_cfg_reg_t;
-
- typedef struct packed {
- struct packed {
- logic d;
} sha3_idle;
struct packed {
logic d;
@@ -219,11 +244,11 @@
// Register -> HW type
typedef struct packed {
- kmac_reg2hw_intr_state_reg_t intr_state; // [1549:1547]
- kmac_reg2hw_intr_enable_reg_t intr_enable; // [1546:1544]
- kmac_reg2hw_intr_test_reg_t intr_test; // [1543:1538]
- kmac_reg2hw_alert_test_reg_t alert_test; // [1537:1536]
- kmac_reg2hw_cfg_reg_t cfg; // [1535:1522]
+ kmac_reg2hw_intr_state_reg_t intr_state; // [1561:1559]
+ kmac_reg2hw_intr_enable_reg_t intr_enable; // [1558:1556]
+ kmac_reg2hw_intr_test_reg_t intr_test; // [1555:1550]
+ kmac_reg2hw_alert_test_reg_t alert_test; // [1549:1546]
+ kmac_reg2hw_cfg_shadowed_reg_t cfg_shadowed; // [1545:1522]
kmac_reg2hw_cmd_reg_t cmd; // [1521:1513]
kmac_reg2hw_entropy_period_reg_t entropy_period; // [1512:1487]
kmac_reg2hw_entropy_refresh_reg_t entropy_refresh; // [1486:1477]
@@ -237,9 +262,8 @@
// HW -> register type
typedef struct packed {
- kmac_hw2reg_intr_state_reg_t intr_state; // [64:59]
- kmac_hw2reg_cfg_regwen_reg_t cfg_regwen; // [58:58]
- kmac_hw2reg_cfg_reg_t cfg; // [57:54]
+ kmac_hw2reg_intr_state_reg_t intr_state; // [60:55]
+ kmac_hw2reg_cfg_regwen_reg_t cfg_regwen; // [54:54]
kmac_hw2reg_status_reg_t status; // [53:44]
kmac_hw2reg_entropy_refresh_reg_t entropy_refresh; // [43:33]
kmac_hw2reg_err_code_reg_t err_code; // [32:0]
@@ -251,7 +275,7 @@
parameter logic [BlockAw-1:0] KMAC_INTR_TEST_OFFSET = 12'h 8;
parameter logic [BlockAw-1:0] KMAC_ALERT_TEST_OFFSET = 12'h c;
parameter logic [BlockAw-1:0] KMAC_CFG_REGWEN_OFFSET = 12'h 10;
- parameter logic [BlockAw-1:0] KMAC_CFG_OFFSET = 12'h 14;
+ parameter logic [BlockAw-1:0] KMAC_CFG_SHADOWED_OFFSET = 12'h 14;
parameter logic [BlockAw-1:0] KMAC_CMD_OFFSET = 12'h 18;
parameter logic [BlockAw-1:0] KMAC_STATUS_OFFSET = 12'h 1c;
parameter logic [BlockAw-1:0] KMAC_ENTROPY_PERIOD_OFFSET = 12'h 20;
@@ -309,8 +333,9 @@
parameter logic [0:0] KMAC_INTR_TEST_KMAC_DONE_RESVAL = 1'h 0;
parameter logic [0:0] KMAC_INTR_TEST_FIFO_EMPTY_RESVAL = 1'h 0;
parameter logic [0:0] KMAC_INTR_TEST_KMAC_ERR_RESVAL = 1'h 0;
- parameter logic [0:0] KMAC_ALERT_TEST_RESVAL = 1'h 0;
- parameter logic [0:0] KMAC_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
+ parameter logic [1:0] KMAC_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] KMAC_ALERT_TEST_FATAL_FAULT_ERR_RESVAL = 1'h 0;
+ parameter logic [0:0] KMAC_ALERT_TEST_RECOV_OPERATION_ERR_RESVAL = 1'h 0;
parameter logic [0:0] KMAC_CFG_REGWEN_RESVAL = 1'h 1;
parameter logic [0:0] KMAC_CFG_REGWEN_EN_RESVAL = 1'h 1;
parameter logic [9:0] KMAC_CMD_RESVAL = 10'h 0;
@@ -363,7 +388,7 @@
KMAC_INTR_TEST,
KMAC_ALERT_TEST,
KMAC_CFG_REGWEN,
- KMAC_CFG,
+ KMAC_CFG_SHADOWED,
KMAC_CMD,
KMAC_STATUS,
KMAC_ENTROPY_PERIOD,
@@ -424,7 +449,7 @@
4'b 0001, // index[ 2] KMAC_INTR_TEST
4'b 0001, // index[ 3] KMAC_ALERT_TEST
4'b 0001, // index[ 4] KMAC_CFG_REGWEN
- 4'b 1111, // index[ 5] KMAC_CFG
+ 4'b 1111, // index[ 5] KMAC_CFG_SHADOWED
4'b 0011, // index[ 6] KMAC_CMD
4'b 0011, // index[ 7] KMAC_STATUS
4'b 1111, // index[ 8] KMAC_ENTROPY_PERIOD
diff --git a/hw/ip/kmac/rtl/kmac_reg_top.sv b/hw/ip/kmac/rtl/kmac_reg_top.sv
index e824066..ee309e2 100644
--- a/hw/ip/kmac/rtl/kmac_reg_top.sv
+++ b/hw/ip/kmac/rtl/kmac_reg_top.sv
@@ -9,6 +9,7 @@
module kmac_reg_top (
input clk_i,
input rst_ni,
+ input rst_shadowed_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
@@ -181,30 +182,32 @@
logic intr_test_fifo_empty_wd;
logic intr_test_kmac_err_wd;
logic alert_test_we;
- logic alert_test_wd;
+ logic alert_test_fatal_fault_err_wd;
+ logic alert_test_recov_operation_err_wd;
logic cfg_regwen_re;
logic cfg_regwen_qs;
- logic cfg_we;
- logic cfg_kmac_en_qs;
- logic cfg_kmac_en_wd;
- logic [2:0] cfg_kstrength_qs;
- logic [2:0] cfg_kstrength_wd;
- logic [1:0] cfg_mode_qs;
- logic [1:0] cfg_mode_wd;
- logic cfg_msg_endianness_qs;
- logic cfg_msg_endianness_wd;
- logic cfg_state_endianness_qs;
- logic cfg_state_endianness_wd;
- logic cfg_sideload_qs;
- logic cfg_sideload_wd;
- logic [1:0] cfg_entropy_mode_qs;
- logic [1:0] cfg_entropy_mode_wd;
- logic cfg_entropy_fast_process_qs;
- logic cfg_entropy_fast_process_wd;
- logic cfg_entropy_ready_qs;
- logic cfg_entropy_ready_wd;
- logic cfg_err_processed_qs;
- logic cfg_err_processed_wd;
+ logic cfg_shadowed_re;
+ logic cfg_shadowed_we;
+ logic cfg_shadowed_kmac_en_qs;
+ logic cfg_shadowed_kmac_en_wd;
+ logic [2:0] cfg_shadowed_kstrength_qs;
+ logic [2:0] cfg_shadowed_kstrength_wd;
+ logic [1:0] cfg_shadowed_mode_qs;
+ logic [1:0] cfg_shadowed_mode_wd;
+ logic cfg_shadowed_msg_endianness_qs;
+ logic cfg_shadowed_msg_endianness_wd;
+ logic cfg_shadowed_state_endianness_qs;
+ logic cfg_shadowed_state_endianness_wd;
+ logic cfg_shadowed_sideload_qs;
+ logic cfg_shadowed_sideload_wd;
+ logic [1:0] cfg_shadowed_entropy_mode_qs;
+ logic [1:0] cfg_shadowed_entropy_mode_wd;
+ logic cfg_shadowed_entropy_fast_process_qs;
+ logic cfg_shadowed_entropy_fast_process_wd;
+ logic cfg_shadowed_entropy_ready_qs;
+ logic cfg_shadowed_entropy_ready_wd;
+ logic cfg_shadowed_err_processed_qs;
+ logic cfg_shadowed_err_processed_wd;
logic cmd_we;
logic [3:0] cmd_cmd_wd;
logic cmd_entropy_req_wd;
@@ -532,16 +535,31 @@
// R[alert_test]: V(True)
+ // F[fatal_fault_err]: 0:0
prim_subreg_ext #(
.DW (1)
- ) u_alert_test (
+ ) u_alert_test_fatal_fault_err (
.re (1'b0),
.we (alert_test_we),
- .wd (alert_test_wd),
+ .wd (alert_test_fatal_fault_err_wd),
.d ('0),
.qre (),
- .qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q),
+ .qe (reg2hw.alert_test.fatal_fault_err.qe),
+ .q (reg2hw.alert_test.fatal_fault_err.q),
+ .qs ()
+ );
+
+ // F[recov_operation_err]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_recov_operation_err (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_recov_operation_err_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.recov_operation_err.qe),
+ .q (reg2hw.alert_test.recov_operation_err.q),
.qs ()
);
@@ -561,255 +579,315 @@
);
- // R[cfg]: V(False)
+ // R[cfg_shadowed]: V(False)
// F[kmac_en]: 0:0
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_kmac_en (
+ ) u_cfg_shadowed_kmac_en (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_kmac_en_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_kmac_en_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.kmac_en.q),
+ .qe (reg2hw.cfg_shadowed.kmac_en.qe),
+ .q (reg2hw.cfg_shadowed.kmac_en.q),
// to register interface (read)
- .qs (cfg_kmac_en_qs)
+ .qs (cfg_shadowed_kmac_en_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.kmac_en.err_update),
+ .err_storage (reg2hw.cfg_shadowed.kmac_en.err_storage)
);
// F[kstrength]: 3:1
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (3),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (3'h0)
- ) u_cfg_kstrength (
+ ) u_cfg_shadowed_kstrength (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_kstrength_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_kstrength_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.kstrength.q),
+ .qe (reg2hw.cfg_shadowed.kstrength.qe),
+ .q (reg2hw.cfg_shadowed.kstrength.q),
// to register interface (read)
- .qs (cfg_kstrength_qs)
+ .qs (cfg_shadowed_kstrength_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.kstrength.err_update),
+ .err_storage (reg2hw.cfg_shadowed.kstrength.err_storage)
);
// F[mode]: 5:4
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
- ) u_cfg_mode (
+ ) u_cfg_shadowed_mode (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_mode_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_mode_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.mode.q),
+ .qe (reg2hw.cfg_shadowed.mode.qe),
+ .q (reg2hw.cfg_shadowed.mode.q),
// to register interface (read)
- .qs (cfg_mode_qs)
+ .qs (cfg_shadowed_mode_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.mode.err_update),
+ .err_storage (reg2hw.cfg_shadowed.mode.err_storage)
);
// F[msg_endianness]: 8:8
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_msg_endianness (
+ ) u_cfg_shadowed_msg_endianness (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_msg_endianness_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_msg_endianness_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.msg_endianness.q),
+ .qe (reg2hw.cfg_shadowed.msg_endianness.qe),
+ .q (reg2hw.cfg_shadowed.msg_endianness.q),
// to register interface (read)
- .qs (cfg_msg_endianness_qs)
+ .qs (cfg_shadowed_msg_endianness_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.msg_endianness.err_update),
+ .err_storage (reg2hw.cfg_shadowed.msg_endianness.err_storage)
);
// F[state_endianness]: 9:9
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_state_endianness (
+ ) u_cfg_shadowed_state_endianness (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_state_endianness_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_state_endianness_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.state_endianness.q),
+ .qe (reg2hw.cfg_shadowed.state_endianness.qe),
+ .q (reg2hw.cfg_shadowed.state_endianness.q),
// to register interface (read)
- .qs (cfg_state_endianness_qs)
+ .qs (cfg_shadowed_state_endianness_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.state_endianness.err_update),
+ .err_storage (reg2hw.cfg_shadowed.state_endianness.err_storage)
);
// F[sideload]: 12:12
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_sideload (
+ ) u_cfg_shadowed_sideload (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_sideload_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_sideload_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.sideload.q),
+ .qe (reg2hw.cfg_shadowed.sideload.qe),
+ .q (reg2hw.cfg_shadowed.sideload.q),
// to register interface (read)
- .qs (cfg_sideload_qs)
+ .qs (cfg_shadowed_sideload_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.sideload.err_update),
+ .err_storage (reg2hw.cfg_shadowed.sideload.err_storage)
);
// F[entropy_mode]: 17:16
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (2'h0)
- ) u_cfg_entropy_mode (
+ ) u_cfg_shadowed_entropy_mode (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_entropy_mode_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_entropy_mode_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.entropy_mode.q),
+ .qe (reg2hw.cfg_shadowed.entropy_mode.qe),
+ .q (reg2hw.cfg_shadowed.entropy_mode.q),
// to register interface (read)
- .qs (cfg_entropy_mode_qs)
+ .qs (cfg_shadowed_entropy_mode_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.entropy_mode.err_update),
+ .err_storage (reg2hw.cfg_shadowed.entropy_mode.err_storage)
);
// F[entropy_fast_process]: 19:19
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_entropy_fast_process (
+ ) u_cfg_shadowed_entropy_fast_process (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_entropy_fast_process_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_entropy_fast_process_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.entropy_fast_process.q),
+ .qe (reg2hw.cfg_shadowed.entropy_fast_process.qe),
+ .q (reg2hw.cfg_shadowed.entropy_fast_process.q),
// to register interface (read)
- .qs (cfg_entropy_fast_process_qs)
+ .qs (cfg_shadowed_entropy_fast_process_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.entropy_fast_process.err_update),
+ .err_storage (reg2hw.cfg_shadowed.entropy_fast_process.err_storage)
);
// F[entropy_ready]: 24:24
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_entropy_ready (
+ ) u_cfg_shadowed_entropy_ready (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_entropy_ready_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_entropy_ready_wd),
// from internal hardware
- .de (hw2reg.cfg.entropy_ready.de),
- .d (hw2reg.cfg.entropy_ready.d),
+ .de (1'b0),
+ .d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.entropy_ready.q),
+ .qe (reg2hw.cfg_shadowed.entropy_ready.qe),
+ .q (reg2hw.cfg_shadowed.entropy_ready.q),
// to register interface (read)
- .qs (cfg_entropy_ready_qs)
+ .qs (cfg_shadowed_entropy_ready_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.entropy_ready.err_update),
+ .err_storage (reg2hw.cfg_shadowed.entropy_ready.err_storage)
);
// F[err_processed]: 25:25
- prim_subreg #(
+ prim_subreg_shadow #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRW),
.RESVAL (1'h0)
- ) u_cfg_err_processed (
+ ) u_cfg_shadowed_err_processed (
.clk_i (clk_i),
.rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
// from register interface
- .we (cfg_we & cfg_regwen_qs),
- .wd (cfg_err_processed_wd),
+ .re (cfg_shadowed_re),
+ .we (cfg_shadowed_we & cfg_regwen_qs),
+ .wd (cfg_shadowed_err_processed_wd),
// from internal hardware
- .de (hw2reg.cfg.err_processed.de),
- .d (hw2reg.cfg.err_processed.d),
+ .de (1'b0),
+ .d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.cfg.err_processed.q),
+ .qe (reg2hw.cfg_shadowed.err_processed.qe),
+ .q (reg2hw.cfg_shadowed.err_processed.q),
// to register interface (read)
- .qs (cfg_err_processed_qs)
+ .qs (cfg_shadowed_err_processed_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.cfg_shadowed.err_processed.err_update),
+ .err_storage (reg2hw.cfg_shadowed.err_processed.err_storage)
);
@@ -1969,7 +2047,7 @@
addr_hit[ 2] = (reg_addr == KMAC_INTR_TEST_OFFSET);
addr_hit[ 3] = (reg_addr == KMAC_ALERT_TEST_OFFSET);
addr_hit[ 4] = (reg_addr == KMAC_CFG_REGWEN_OFFSET);
- addr_hit[ 5] = (reg_addr == KMAC_CFG_OFFSET);
+ addr_hit[ 5] = (reg_addr == KMAC_CFG_SHADOWED_OFFSET);
addr_hit[ 6] = (reg_addr == KMAC_CMD_OFFSET);
addr_hit[ 7] = (reg_addr == KMAC_STATUS_OFFSET);
addr_hit[ 8] = (reg_addr == KMAC_ENTROPY_PERIOD_OFFSET);
@@ -2109,29 +2187,32 @@
assign intr_test_kmac_err_wd = reg_wdata[2];
assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
- assign alert_test_wd = reg_wdata[0];
+ assign alert_test_fatal_fault_err_wd = reg_wdata[0];
+
+ assign alert_test_recov_operation_err_wd = reg_wdata[1];
assign cfg_regwen_re = addr_hit[4] & reg_re & !reg_error;
- assign cfg_we = addr_hit[5] & reg_we & !reg_error;
+ assign cfg_shadowed_re = addr_hit[5] & reg_re & !reg_error;
+ assign cfg_shadowed_we = addr_hit[5] & reg_we & !reg_error;
- assign cfg_kmac_en_wd = reg_wdata[0];
+ assign cfg_shadowed_kmac_en_wd = reg_wdata[0];
- assign cfg_kstrength_wd = reg_wdata[3:1];
+ assign cfg_shadowed_kstrength_wd = reg_wdata[3:1];
- assign cfg_mode_wd = reg_wdata[5:4];
+ assign cfg_shadowed_mode_wd = reg_wdata[5:4];
- assign cfg_msg_endianness_wd = reg_wdata[8];
+ assign cfg_shadowed_msg_endianness_wd = reg_wdata[8];
- assign cfg_state_endianness_wd = reg_wdata[9];
+ assign cfg_shadowed_state_endianness_wd = reg_wdata[9];
- assign cfg_sideload_wd = reg_wdata[12];
+ assign cfg_shadowed_sideload_wd = reg_wdata[12];
- assign cfg_entropy_mode_wd = reg_wdata[17:16];
+ assign cfg_shadowed_entropy_mode_wd = reg_wdata[17:16];
- assign cfg_entropy_fast_process_wd = reg_wdata[19];
+ assign cfg_shadowed_entropy_fast_process_wd = reg_wdata[19];
- assign cfg_entropy_ready_wd = reg_wdata[24];
+ assign cfg_shadowed_entropy_ready_wd = reg_wdata[24];
- assign cfg_err_processed_wd = reg_wdata[25];
+ assign cfg_shadowed_err_processed_wd = reg_wdata[25];
assign cmd_we = addr_hit[6] & reg_we & !reg_error;
assign cmd_cmd_wd = reg_wdata[3:0];
@@ -2311,6 +2392,7 @@
addr_hit[3]: begin
reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
end
addr_hit[4]: begin
@@ -2318,16 +2400,16 @@
end
addr_hit[5]: begin
- reg_rdata_next[0] = cfg_kmac_en_qs;
- reg_rdata_next[3:1] = cfg_kstrength_qs;
- reg_rdata_next[5:4] = cfg_mode_qs;
- reg_rdata_next[8] = cfg_msg_endianness_qs;
- reg_rdata_next[9] = cfg_state_endianness_qs;
- reg_rdata_next[12] = cfg_sideload_qs;
- reg_rdata_next[17:16] = cfg_entropy_mode_qs;
- reg_rdata_next[19] = cfg_entropy_fast_process_qs;
- reg_rdata_next[24] = cfg_entropy_ready_qs;
- reg_rdata_next[25] = cfg_err_processed_qs;
+ reg_rdata_next[0] = cfg_shadowed_kmac_en_qs;
+ reg_rdata_next[3:1] = cfg_shadowed_kstrength_qs;
+ reg_rdata_next[5:4] = cfg_shadowed_mode_qs;
+ reg_rdata_next[8] = cfg_shadowed_msg_endianness_qs;
+ reg_rdata_next[9] = cfg_shadowed_state_endianness_qs;
+ reg_rdata_next[12] = cfg_shadowed_sideload_qs;
+ reg_rdata_next[17:16] = cfg_shadowed_entropy_mode_qs;
+ reg_rdata_next[19] = cfg_shadowed_entropy_fast_process_qs;
+ reg_rdata_next[24] = cfg_shadowed_entropy_ready_qs;
+ reg_rdata_next[25] = cfg_shadowed_err_processed_qs;
end
addr_hit[6]: begin
@@ -2551,7 +2633,26 @@
// shadow busy
logic shadow_busy;
- assign shadow_busy = 1'b0;
+ logic rst_done;
+ logic shadow_rst_done;
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ rst_done <= '0;
+ end else begin
+ rst_done <= 1'b1;
+ end
+ end
+
+ always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
+ if (!rst_shadowed_ni) begin
+ shadow_rst_done <= '0;
+ end else begin
+ shadow_rst_done <= 1'b1;
+ end
+ end
+
+ // both shadow and normal resets have been released
+ assign shadow_busy = ~(rst_done & shadow_rst_done);
// register busy
logic reg_busy_sel;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index f4c0079..c2ee935 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -13601,7 +13601,16 @@
lpg_idx: 18
}
{
- name: kmac_fatal_fault
+ name: kmac_fatal_fault_err
+ width: 1
+ type: alert
+ async: "1"
+ module_name: kmac
+ lpg_name: trans_sys_0
+ lpg_idx: 18
+ }
+ {
+ name: kmac_recov_operation_err
width: 1
type: alert
async: "1"
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index fe4f224..9759cc5 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -44,21 +44,22 @@
assign alert_if[37].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
assign alert_if[38].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
assign alert_if[39].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[40].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[41].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[42].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[43].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[44].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[45].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
-assign alert_if[46].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[47].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[48].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[49].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
-assign alert_if[50].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[51].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
-assign alert_if[52].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[53].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
-assign alert_if[54].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
-assign alert_if[55].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
-assign alert_if[56].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
-assign alert_if[57].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1];
+assign alert_if[41].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[42].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[43].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[44].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[45].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[46].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1];
+assign alert_if[47].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[48].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[49].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[50].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1];
+assign alert_if[51].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[52].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1];
+assign alert_if[53].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[54].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[55].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[0];
+assign alert_if[56].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[1];
+assign alert_if[57].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[2];
+assign alert_if[58].alert_tx = `CHIP_HIER.u_rv_core_ibex.alert_tx_o[3];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index 61e8034..118a96e 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -44,7 +44,8 @@
"aes_recov_ctrl_update_err",
"aes_fatal_fault",
"hmac_fatal_fault",
- "kmac_fatal_fault",
+ "kmac_fatal_fault_err",
+ "kmac_recov_operation_err",
"otbn_fatal",
"otbn_recov",
"keymgr_fatal_fault_err",
@@ -65,4 +66,4 @@
"rv_core_ibex_recov_hw_err"
};
-parameter uint NUM_ALERTS = 58;
+parameter uint NUM_ALERTS = 59;
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
index 25c8773..0e27e4f 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
@@ -33,7 +33,7 @@
{ name: "NAlerts",
desc: "Number of alert channels.",
type: "int",
- default: "58",
+ default: "59",
local: "true"
},
{ name: "NLpg",
@@ -77,6 +77,7 @@
5'd18,
5'd18,
5'd18,
+ 5'd18,
5'd17,
5'd16,
5'd16,
@@ -194,6 +195,7 @@
1'b1,
1'b1,
1'b1,
+ 1'b1,
1'b1
}
'''
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
index ecbb162..dd7eab2 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/data/top_earlgrey_alert_handler.ipconfig.hjson
@@ -5,7 +5,7 @@
instance_name: top_earlgrey_alert_handler
param_values:
{
- n_alerts: 58
+ n_alerts: 59
esc_cnt_dw: 32
accu_cnt_dw: 16
async_on:
@@ -68,6 +68,7 @@
1'b1
1'b1
1'b1
+ 1'b1
]
n_classes: 4
n_lpg: 20
@@ -115,6 +116,7 @@
5'd18
5'd18
5'd18
+ 5'd18
5'd17
5'd17
5'd17
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
index 8f8fedc..99f1464 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv
@@ -7,7 +7,7 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 58;
+ parameter int NAlerts = 59;
parameter int NLpg = 20;
parameter int NLpgWidth = 5;
parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = {
@@ -33,6 +33,7 @@
5'd18,
5'd18,
5'd18,
+ 5'd18,
5'd17,
5'd16,
5'd16,
@@ -130,6 +131,7 @@
1'b1,
1'b1,
1'b1,
+ 1'b1,
1'b1
};
parameter int N_CLASSES = 4;
@@ -759,15 +761,15 @@
// Register -> HW type
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [1126:1123]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1122:1119]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [1118:1111]
- alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1110:1095]
- alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1094:1094]
- alert_handler_reg2hw_alert_regwen_mreg_t [57:0] alert_regwen; // [1093:1036]
- alert_handler_reg2hw_alert_en_shadowed_mreg_t [57:0] alert_en_shadowed; // [1035:978]
- alert_handler_reg2hw_alert_class_shadowed_mreg_t [57:0] alert_class_shadowed; // [977:862]
- alert_handler_reg2hw_alert_cause_mreg_t [57:0] alert_cause; // [861:804]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [1131:1128]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1127:1124]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [1123:1116]
+ alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1115:1100]
+ alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1099:1099]
+ alert_handler_reg2hw_alert_regwen_mreg_t [58:0] alert_regwen; // [1098:1040]
+ alert_handler_reg2hw_alert_en_shadowed_mreg_t [58:0] alert_en_shadowed; // [1039:981]
+ alert_handler_reg2hw_alert_class_shadowed_mreg_t [58:0] alert_class_shadowed; // [980:863]
+ alert_handler_reg2hw_alert_cause_mreg_t [58:0] alert_cause; // [862:804]
alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797]
alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0]
loc_alert_class_shadowed; // [796:783]
@@ -820,8 +822,8 @@
// HW -> register type
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [349:342]
- alert_handler_hw2reg_alert_cause_mreg_t [57:0] alert_cause; // [341:226]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [351:344]
+ alert_handler_hw2reg_alert_cause_mreg_t [58:0] alert_cause; // [343:226]
alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212]
alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -906,264 +908,268 @@
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_55_OFFSET = 11'h f4;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_56_OFFSET = 11'h f8;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 100;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 104;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 108;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 10c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 110;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 114;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 118;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 11c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 120;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 124;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 128;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 12c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 130;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 134;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 138;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 13c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 140;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 144;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 148;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 14c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 150;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 154;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 158;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 15c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 160;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 164;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 168;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 16c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 170;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 174;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 178;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 17c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 180;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 184;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 188;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 18c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 190;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 194;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 198;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 19c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 1e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 1ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 1f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 1f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 1f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 1fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 200;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 204;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 208;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 20c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 210;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 214;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 218;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 21c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 220;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 224;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 228;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 22c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 230;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 234;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 238;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 23c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 240;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 244;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 248;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 24c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 250;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 254;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 258;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 25c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 260;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 264;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 268;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 26c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 270;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 274;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 278;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 27c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 280;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 284;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 288;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 28c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 290;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 294;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 298;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 29c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 2d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 2d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 2d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 2dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 2e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 2e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 2e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 2ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 2f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 2f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 2f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 2fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 300;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 304;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 308;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 30c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 310;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 314;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 318;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 31c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 320;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 324;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 328;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 32c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 330;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 334;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 338;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 33c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 340;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 344;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 348;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 34c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 350;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 354;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 358;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 35c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 360;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 364;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 368;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 36c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 370;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 374;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 378;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 37c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 380;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 384;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 388;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 38c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 390;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 394;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 398;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 39c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 3b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 3bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 3c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 3c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 3c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 3cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 3d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 3d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 3d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 3dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 3e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 3e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 3e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 3ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 3f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 3f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 3f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 3fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 400;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 404;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 408;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 40c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 410;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 414;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 418;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 41c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 420;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 424;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 428;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 42c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 430;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 434;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 438;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 43c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 440;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 444;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 448;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 44c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 450;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 454;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 458;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 45c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 460;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 464;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 468;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 46c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 470;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 474;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 478;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 47c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 480;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 484;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 488;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 48c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 490;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 494;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 498;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 49c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 4c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 4cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 4d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 4d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 4d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 4dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 4e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 500;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 504;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 104;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 108;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 10c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 110;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 114;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 118;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 11c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 120;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 124;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 128;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 12c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 130;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 134;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 138;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 13c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 140;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 144;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 148;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 14c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 150;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 154;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 158;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 15c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 160;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 164;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 168;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 16c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 170;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 174;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 178;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 17c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 180;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 184;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 188;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 18c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 190;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 194;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 198;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 19c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 1a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 1a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 1a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 1ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 1b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 1b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 1b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 1bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 1c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 1c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 1c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 1cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 1d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 1d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 1d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 1dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 1e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 1e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 1e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 1ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 1f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 1f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 1f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 1fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 200;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 204;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 208;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 20c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 210;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 214;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 218;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 21c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 220;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 224;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 228;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 22c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 230;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 234;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 238;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 23c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 240;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 244;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 248;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 24c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 250;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 254;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 258;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 25c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 260;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 264;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 268;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 26c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 270;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 274;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 278;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 27c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 280;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 284;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 288;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 28c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 290;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 294;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 298;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 29c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 2a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 2a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 2a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 2ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 2b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 2b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 2b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 2bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 2c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 2c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 2c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 2cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 2d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 2d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 2d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 2dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 2e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 2e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 2e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 2ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 2f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 2f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 2f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 2fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 300;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 304;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 308;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 30c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 310;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 314;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 318;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 31c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 320;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 324;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 328;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 32c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 330;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 334;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 338;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 33c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 340;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 344;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 348;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 34c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 350;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 354;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 358;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 35c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 360;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 364;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 368;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 36c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 370;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 374;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 378;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 37c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 380;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 384;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 388;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 38c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 390;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 394;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 398;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 39c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 3a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 3a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 3a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 3ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 3b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 3b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 3bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 3c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 3c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 3c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 3cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 3d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 3d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 3d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 3dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 3e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 3e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 3e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 3ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 3f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 3f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 3f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 3fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 400;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 404;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 408;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 40c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 410;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 414;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 418;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 41c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 420;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 424;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 428;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 42c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 430;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 434;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 438;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 43c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 440;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 444;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 448;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 44c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 450;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 454;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 458;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 45c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 460;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 464;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 468;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 46c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 470;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 474;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 478;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 47c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 480;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 484;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 488;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 48c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 490;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 494;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 498;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 49c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 4a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 4a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 4a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 4ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 4b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 4b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 4b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 4c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 4cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 4d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 4d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 4d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 4dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 4e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 4e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 4e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 4ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 4f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 4f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 4f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 4fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 500;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 504;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 508;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 50c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 510;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 514;
// Reset values for hwext registers and their fields
parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -1250,6 +1256,7 @@
ALERT_HANDLER_ALERT_REGWEN_55,
ALERT_HANDLER_ALERT_REGWEN_56,
ALERT_HANDLER_ALERT_REGWEN_57,
+ ALERT_HANDLER_ALERT_REGWEN_58,
ALERT_HANDLER_ALERT_EN_SHADOWED_0,
ALERT_HANDLER_ALERT_EN_SHADOWED_1,
ALERT_HANDLER_ALERT_EN_SHADOWED_2,
@@ -1308,6 +1315,7 @@
ALERT_HANDLER_ALERT_EN_SHADOWED_55,
ALERT_HANDLER_ALERT_EN_SHADOWED_56,
ALERT_HANDLER_ALERT_EN_SHADOWED_57,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_58,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_0,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_1,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_2,
@@ -1366,6 +1374,7 @@
ALERT_HANDLER_ALERT_CLASS_SHADOWED_55,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_56,
ALERT_HANDLER_ALERT_CLASS_SHADOWED_57,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_58,
ALERT_HANDLER_ALERT_CAUSE_0,
ALERT_HANDLER_ALERT_CAUSE_1,
ALERT_HANDLER_ALERT_CAUSE_2,
@@ -1424,6 +1433,7 @@
ALERT_HANDLER_ALERT_CAUSE_55,
ALERT_HANDLER_ALERT_CAUSE_56,
ALERT_HANDLER_ALERT_CAUSE_57,
+ ALERT_HANDLER_ALERT_CAUSE_58,
ALERT_HANDLER_LOC_ALERT_REGWEN_0,
ALERT_HANDLER_LOC_ALERT_REGWEN_1,
ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1511,7 +1521,7 @@
} alert_handler_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ALERT_HANDLER_PERMIT [322] = '{
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [326] = '{
4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
@@ -1576,264 +1586,268 @@
4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_REGWEN_55
4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_REGWEN_56
4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57
- 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_SHADOWED_0
- 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_SHADOWED_1
- 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_SHADOWED_2
- 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_SHADOWED_3
- 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_SHADOWED_4
- 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_5
- 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_6
- 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_7
- 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_8
- 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_9
- 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_10
- 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_11
- 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_12
- 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_13
- 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_14
- 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_15
- 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_16
- 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_17
- 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_18
- 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_19
- 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_20
- 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_21
- 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_22
- 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_23
- 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_24
- 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_25
- 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_26
- 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_27
- 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_28
- 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_29
- 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_30
- 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_31
- 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_32
- 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_33
- 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_34
- 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_35
- 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_36
- 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_37
- 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_38
- 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_39
- 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_40
- 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_41
- 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_42
- 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_43
- 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_44
- 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_45
- 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_46
- 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_47
- 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_48
- 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_49
- 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_50
- 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_51
- 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_52
- 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_53
- 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_54
- 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_55
- 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_56
- 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_57
- 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
- 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
- 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
- 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
- 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
- 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
- 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
- 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
- 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
- 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
- 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
- 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
- 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
- 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
- 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
- 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
- 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
- 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
- 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
- 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
- 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
- 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
- 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
- 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
- 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
- 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
- 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
- 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
- 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
- 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
- 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
- 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
- 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
- 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
- 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
- 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
- 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
- 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
- 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
- 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
- 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
- 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
- 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
- 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
- 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
- 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
- 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
- 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
- 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
- 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
- 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
- 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
- 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
- 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
- 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
- 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
- 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
- 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
- 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CAUSE_0
- 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CAUSE_1
- 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CAUSE_2
- 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CAUSE_3
- 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CAUSE_4
- 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CAUSE_5
- 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_6
- 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_7
- 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_8
- 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_9
- 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_10
- 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_11
- 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_12
- 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_13
- 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_14
- 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_15
- 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_16
- 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_17
- 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_18
- 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_19
- 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_20
- 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_21
- 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_22
- 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_23
- 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_24
- 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_25
- 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_26
- 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_27
- 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_28
- 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_29
- 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_30
- 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_31
- 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_32
- 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_33
- 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_34
- 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_35
- 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_36
- 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_37
- 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_38
- 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_39
- 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_40
- 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_41
- 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_42
- 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_43
- 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_44
- 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_45
- 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_46
- 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_47
- 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_48
- 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_49
- 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_50
- 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_51
- 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_52
- 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_53
- 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_54
- 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_55
- 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_56
- 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_57
- 4'b 0001, // index[238] ALERT_HANDLER_LOC_ALERT_REGWEN_0
- 4'b 0001, // index[239] ALERT_HANDLER_LOC_ALERT_REGWEN_1
- 4'b 0001, // index[240] ALERT_HANDLER_LOC_ALERT_REGWEN_2
- 4'b 0001, // index[241] ALERT_HANDLER_LOC_ALERT_REGWEN_3
- 4'b 0001, // index[242] ALERT_HANDLER_LOC_ALERT_REGWEN_4
- 4'b 0001, // index[243] ALERT_HANDLER_LOC_ALERT_REGWEN_5
- 4'b 0001, // index[244] ALERT_HANDLER_LOC_ALERT_REGWEN_6
- 4'b 0001, // index[245] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
- 4'b 0001, // index[246] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
- 4'b 0001, // index[247] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
- 4'b 0001, // index[248] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
- 4'b 0001, // index[249] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
- 4'b 0001, // index[250] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
- 4'b 0001, // index[251] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
- 4'b 0001, // index[252] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
- 4'b 0001, // index[253] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
- 4'b 0001, // index[254] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
- 4'b 0001, // index[255] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
- 4'b 0001, // index[256] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
- 4'b 0001, // index[257] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
- 4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
- 4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_CAUSE_0
- 4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_CAUSE_1
- 4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_CAUSE_2
- 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_CAUSE_3
- 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_CAUSE_4
- 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_CAUSE_5
- 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_CAUSE_6
- 4'b 0001, // index[266] ALERT_HANDLER_CLASSA_REGWEN
- 4'b 0011, // index[267] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
- 4'b 0001, // index[268] ALERT_HANDLER_CLASSA_CLR_REGWEN
- 4'b 0001, // index[269] ALERT_HANDLER_CLASSA_CLR_SHADOWED
- 4'b 0011, // index[270] ALERT_HANDLER_CLASSA_ACCUM_CNT
- 4'b 0011, // index[271] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[272] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[273] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[274] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[275] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[276] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[277] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[278] ALERT_HANDLER_CLASSA_ESC_CNT
- 4'b 0001, // index[279] ALERT_HANDLER_CLASSA_STATE
- 4'b 0001, // index[280] ALERT_HANDLER_CLASSB_REGWEN
- 4'b 0011, // index[281] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
- 4'b 0001, // index[282] ALERT_HANDLER_CLASSB_CLR_REGWEN
- 4'b 0001, // index[283] ALERT_HANDLER_CLASSB_CLR_SHADOWED
- 4'b 0011, // index[284] ALERT_HANDLER_CLASSB_ACCUM_CNT
- 4'b 0011, // index[285] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[286] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[287] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[288] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[289] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[290] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[291] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[292] ALERT_HANDLER_CLASSB_ESC_CNT
- 4'b 0001, // index[293] ALERT_HANDLER_CLASSB_STATE
- 4'b 0001, // index[294] ALERT_HANDLER_CLASSC_REGWEN
- 4'b 0011, // index[295] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
- 4'b 0001, // index[296] ALERT_HANDLER_CLASSC_CLR_REGWEN
- 4'b 0001, // index[297] ALERT_HANDLER_CLASSC_CLR_SHADOWED
- 4'b 0011, // index[298] ALERT_HANDLER_CLASSC_ACCUM_CNT
- 4'b 0011, // index[299] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[300] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[301] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[302] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[303] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[304] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[305] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[306] ALERT_HANDLER_CLASSC_ESC_CNT
- 4'b 0001, // index[307] ALERT_HANDLER_CLASSC_STATE
- 4'b 0001, // index[308] ALERT_HANDLER_CLASSD_REGWEN
- 4'b 0011, // index[309] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
- 4'b 0001, // index[310] ALERT_HANDLER_CLASSD_CLR_REGWEN
- 4'b 0001, // index[311] ALERT_HANDLER_CLASSD_CLR_SHADOWED
- 4'b 0011, // index[312] ALERT_HANDLER_CLASSD_ACCUM_CNT
- 4'b 0011, // index[313] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
- 4'b 1111, // index[314] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
- 4'b 0001, // index[315] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
- 4'b 1111, // index[316] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
- 4'b 1111, // index[317] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
- 4'b 1111, // index[318] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
- 4'b 1111, // index[319] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
- 4'b 1111, // index[320] ALERT_HANDLER_CLASSD_ESC_CNT
- 4'b 0001 // index[321] ALERT_HANDLER_CLASSD_STATE
+ 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58
+ 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_SHADOWED_0
+ 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_SHADOWED_1
+ 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_SHADOWED_2
+ 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_SHADOWED_3
+ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_SHADOWED_4
+ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_SHADOWED_5
+ 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_SHADOWED_6
+ 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_SHADOWED_7
+ 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_SHADOWED_8
+ 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_SHADOWED_9
+ 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_SHADOWED_10
+ 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_SHADOWED_11
+ 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_SHADOWED_12
+ 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_SHADOWED_13
+ 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_SHADOWED_14
+ 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_SHADOWED_15
+ 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_SHADOWED_16
+ 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_SHADOWED_17
+ 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_SHADOWED_18
+ 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_SHADOWED_19
+ 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_SHADOWED_20
+ 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_SHADOWED_21
+ 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_SHADOWED_22
+ 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_EN_SHADOWED_23
+ 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_EN_SHADOWED_24
+ 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_EN_SHADOWED_25
+ 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_EN_SHADOWED_26
+ 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_EN_SHADOWED_27
+ 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_EN_SHADOWED_28
+ 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_EN_SHADOWED_29
+ 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_EN_SHADOWED_30
+ 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_EN_SHADOWED_31
+ 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_EN_SHADOWED_32
+ 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_EN_SHADOWED_33
+ 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_EN_SHADOWED_34
+ 4'b 0001, // index[100] ALERT_HANDLER_ALERT_EN_SHADOWED_35
+ 4'b 0001, // index[101] ALERT_HANDLER_ALERT_EN_SHADOWED_36
+ 4'b 0001, // index[102] ALERT_HANDLER_ALERT_EN_SHADOWED_37
+ 4'b 0001, // index[103] ALERT_HANDLER_ALERT_EN_SHADOWED_38
+ 4'b 0001, // index[104] ALERT_HANDLER_ALERT_EN_SHADOWED_39
+ 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_40
+ 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_41
+ 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_42
+ 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_43
+ 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_44
+ 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_45
+ 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_46
+ 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_47
+ 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_48
+ 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_49
+ 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_50
+ 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_51
+ 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_52
+ 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_53
+ 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_54
+ 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_55
+ 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_56
+ 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_57
+ 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_58
+ 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0
+ 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1
+ 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2
+ 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3
+ 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4
+ 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5
+ 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6
+ 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7
+ 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8
+ 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9
+ 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10
+ 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11
+ 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12
+ 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13
+ 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14
+ 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15
+ 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16
+ 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17
+ 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18
+ 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19
+ 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20
+ 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21
+ 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22
+ 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23
+ 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24
+ 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25
+ 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26
+ 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27
+ 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28
+ 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29
+ 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30
+ 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31
+ 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32
+ 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33
+ 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34
+ 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35
+ 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36
+ 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37
+ 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38
+ 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39
+ 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40
+ 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41
+ 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42
+ 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43
+ 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44
+ 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45
+ 4'b 0001, // index[170] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46
+ 4'b 0001, // index[171] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47
+ 4'b 0001, // index[172] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48
+ 4'b 0001, // index[173] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49
+ 4'b 0001, // index[174] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50
+ 4'b 0001, // index[175] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51
+ 4'b 0001, // index[176] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52
+ 4'b 0001, // index[177] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53
+ 4'b 0001, // index[178] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54
+ 4'b 0001, // index[179] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55
+ 4'b 0001, // index[180] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56
+ 4'b 0001, // index[181] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57
+ 4'b 0001, // index[182] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58
+ 4'b 0001, // index[183] ALERT_HANDLER_ALERT_CAUSE_0
+ 4'b 0001, // index[184] ALERT_HANDLER_ALERT_CAUSE_1
+ 4'b 0001, // index[185] ALERT_HANDLER_ALERT_CAUSE_2
+ 4'b 0001, // index[186] ALERT_HANDLER_ALERT_CAUSE_3
+ 4'b 0001, // index[187] ALERT_HANDLER_ALERT_CAUSE_4
+ 4'b 0001, // index[188] ALERT_HANDLER_ALERT_CAUSE_5
+ 4'b 0001, // index[189] ALERT_HANDLER_ALERT_CAUSE_6
+ 4'b 0001, // index[190] ALERT_HANDLER_ALERT_CAUSE_7
+ 4'b 0001, // index[191] ALERT_HANDLER_ALERT_CAUSE_8
+ 4'b 0001, // index[192] ALERT_HANDLER_ALERT_CAUSE_9
+ 4'b 0001, // index[193] ALERT_HANDLER_ALERT_CAUSE_10
+ 4'b 0001, // index[194] ALERT_HANDLER_ALERT_CAUSE_11
+ 4'b 0001, // index[195] ALERT_HANDLER_ALERT_CAUSE_12
+ 4'b 0001, // index[196] ALERT_HANDLER_ALERT_CAUSE_13
+ 4'b 0001, // index[197] ALERT_HANDLER_ALERT_CAUSE_14
+ 4'b 0001, // index[198] ALERT_HANDLER_ALERT_CAUSE_15
+ 4'b 0001, // index[199] ALERT_HANDLER_ALERT_CAUSE_16
+ 4'b 0001, // index[200] ALERT_HANDLER_ALERT_CAUSE_17
+ 4'b 0001, // index[201] ALERT_HANDLER_ALERT_CAUSE_18
+ 4'b 0001, // index[202] ALERT_HANDLER_ALERT_CAUSE_19
+ 4'b 0001, // index[203] ALERT_HANDLER_ALERT_CAUSE_20
+ 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CAUSE_21
+ 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CAUSE_22
+ 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CAUSE_23
+ 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CAUSE_24
+ 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CAUSE_25
+ 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CAUSE_26
+ 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CAUSE_27
+ 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CAUSE_28
+ 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CAUSE_29
+ 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CAUSE_30
+ 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CAUSE_31
+ 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CAUSE_32
+ 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CAUSE_33
+ 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CAUSE_34
+ 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CAUSE_35
+ 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CAUSE_36
+ 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CAUSE_37
+ 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CAUSE_38
+ 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CAUSE_39
+ 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CAUSE_40
+ 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CAUSE_41
+ 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CAUSE_42
+ 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CAUSE_43
+ 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CAUSE_44
+ 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CAUSE_45
+ 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CAUSE_46
+ 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CAUSE_47
+ 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CAUSE_48
+ 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CAUSE_49
+ 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CAUSE_50
+ 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CAUSE_51
+ 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CAUSE_52
+ 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CAUSE_53
+ 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CAUSE_54
+ 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CAUSE_55
+ 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CAUSE_56
+ 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CAUSE_57
+ 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CAUSE_58
+ 4'b 0001, // index[242] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+ 4'b 0001, // index[243] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+ 4'b 0001, // index[244] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+ 4'b 0001, // index[245] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+ 4'b 0001, // index[246] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+ 4'b 0001, // index[247] ALERT_HANDLER_LOC_ALERT_REGWEN_5
+ 4'b 0001, // index[248] ALERT_HANDLER_LOC_ALERT_REGWEN_6
+ 4'b 0001, // index[249] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0
+ 4'b 0001, // index[250] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1
+ 4'b 0001, // index[251] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2
+ 4'b 0001, // index[252] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3
+ 4'b 0001, // index[253] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4
+ 4'b 0001, // index[254] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5
+ 4'b 0001, // index[255] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6
+ 4'b 0001, // index[256] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0
+ 4'b 0001, // index[257] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1
+ 4'b 0001, // index[258] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2
+ 4'b 0001, // index[259] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3
+ 4'b 0001, // index[260] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4
+ 4'b 0001, // index[261] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5
+ 4'b 0001, // index[262] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6
+ 4'b 0001, // index[263] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+ 4'b 0001, // index[264] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+ 4'b 0001, // index[265] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+ 4'b 0001, // index[266] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+ 4'b 0001, // index[267] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+ 4'b 0001, // index[268] ALERT_HANDLER_LOC_ALERT_CAUSE_5
+ 4'b 0001, // index[269] ALERT_HANDLER_LOC_ALERT_CAUSE_6
+ 4'b 0001, // index[270] ALERT_HANDLER_CLASSA_REGWEN
+ 4'b 0011, // index[271] ALERT_HANDLER_CLASSA_CTRL_SHADOWED
+ 4'b 0001, // index[272] ALERT_HANDLER_CLASSA_CLR_REGWEN
+ 4'b 0001, // index[273] ALERT_HANDLER_CLASSA_CLR_SHADOWED
+ 4'b 0011, // index[274] ALERT_HANDLER_CLASSA_ACCUM_CNT
+ 4'b 0011, // index[275] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[276] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[277] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[278] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[279] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[280] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[281] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[282] ALERT_HANDLER_CLASSA_ESC_CNT
+ 4'b 0001, // index[283] ALERT_HANDLER_CLASSA_STATE
+ 4'b 0001, // index[284] ALERT_HANDLER_CLASSB_REGWEN
+ 4'b 0011, // index[285] ALERT_HANDLER_CLASSB_CTRL_SHADOWED
+ 4'b 0001, // index[286] ALERT_HANDLER_CLASSB_CLR_REGWEN
+ 4'b 0001, // index[287] ALERT_HANDLER_CLASSB_CLR_SHADOWED
+ 4'b 0011, // index[288] ALERT_HANDLER_CLASSB_ACCUM_CNT
+ 4'b 0011, // index[289] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[290] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[291] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[292] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[293] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[294] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[295] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[296] ALERT_HANDLER_CLASSB_ESC_CNT
+ 4'b 0001, // index[297] ALERT_HANDLER_CLASSB_STATE
+ 4'b 0001, // index[298] ALERT_HANDLER_CLASSC_REGWEN
+ 4'b 0011, // index[299] ALERT_HANDLER_CLASSC_CTRL_SHADOWED
+ 4'b 0001, // index[300] ALERT_HANDLER_CLASSC_CLR_REGWEN
+ 4'b 0001, // index[301] ALERT_HANDLER_CLASSC_CLR_SHADOWED
+ 4'b 0011, // index[302] ALERT_HANDLER_CLASSC_ACCUM_CNT
+ 4'b 0011, // index[303] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[304] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[305] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[306] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[307] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[308] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[309] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[310] ALERT_HANDLER_CLASSC_ESC_CNT
+ 4'b 0001, // index[311] ALERT_HANDLER_CLASSC_STATE
+ 4'b 0001, // index[312] ALERT_HANDLER_CLASSD_REGWEN
+ 4'b 0011, // index[313] ALERT_HANDLER_CLASSD_CTRL_SHADOWED
+ 4'b 0001, // index[314] ALERT_HANDLER_CLASSD_CLR_REGWEN
+ 4'b 0001, // index[315] ALERT_HANDLER_CLASSD_CLR_SHADOWED
+ 4'b 0011, // index[316] ALERT_HANDLER_CLASSD_ACCUM_CNT
+ 4'b 0011, // index[317] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED
+ 4'b 1111, // index[318] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED
+ 4'b 0001, // index[319] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED
+ 4'b 1111, // index[320] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED
+ 4'b 1111, // index[321] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED
+ 4'b 1111, // index[322] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED
+ 4'b 1111, // index[323] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED
+ 4'b 1111, // index[324] ALERT_HANDLER_CLASSD_ESC_CNT
+ 4'b 0001 // index[325] ALERT_HANDLER_CLASSD_STATE
};
endpackage
diff --git a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
index af4a3ec..6685e5c 100644
--- a/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv
@@ -317,6 +317,9 @@
logic alert_regwen_57_we;
logic alert_regwen_57_qs;
logic alert_regwen_57_wd;
+ logic alert_regwen_58_we;
+ logic alert_regwen_58_qs;
+ logic alert_regwen_58_wd;
logic alert_en_shadowed_0_re;
logic alert_en_shadowed_0_we;
logic alert_en_shadowed_0_qs;
@@ -549,6 +552,10 @@
logic alert_en_shadowed_57_we;
logic alert_en_shadowed_57_qs;
logic alert_en_shadowed_57_wd;
+ logic alert_en_shadowed_58_re;
+ logic alert_en_shadowed_58_we;
+ logic alert_en_shadowed_58_qs;
+ logic alert_en_shadowed_58_wd;
logic alert_class_shadowed_0_re;
logic alert_class_shadowed_0_we;
logic [1:0] alert_class_shadowed_0_qs;
@@ -781,6 +788,10 @@
logic alert_class_shadowed_57_we;
logic [1:0] alert_class_shadowed_57_qs;
logic [1:0] alert_class_shadowed_57_wd;
+ logic alert_class_shadowed_58_re;
+ logic alert_class_shadowed_58_we;
+ logic [1:0] alert_class_shadowed_58_qs;
+ logic [1:0] alert_class_shadowed_58_wd;
logic alert_cause_0_we;
logic alert_cause_0_qs;
logic alert_cause_0_wd;
@@ -955,6 +966,9 @@
logic alert_cause_57_we;
logic alert_cause_57_qs;
logic alert_cause_57_wd;
+ logic alert_cause_58_we;
+ logic alert_cause_58_qs;
+ logic alert_cause_58_wd;
logic loc_alert_regwen_0_we;
logic loc_alert_regwen_0_qs;
logic loc_alert_regwen_0_wd;
@@ -3237,6 +3251,33 @@
);
+ // Subregister 58 of Multireg alert_regwen
+ // R[alert_regwen_58]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_58_we),
+ .wd (alert_regwen_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[58].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_58_qs)
+ );
+
+
// Subregister 0 of Multireg alert_en_shadowed
// R[alert_en_shadowed_0]: V(False)
prim_subreg_shadow #(
@@ -5151,6 +5192,39 @@
);
+ // Subregister 58 of Multireg alert_en_shadowed
+ // R[alert_en_shadowed_58]: V(False)
+ prim_subreg_shadow #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (1'h0)
+ ) u_alert_en_shadowed_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_en_shadowed_58_re),
+ .we (alert_en_shadowed_58_we & alert_regwen_58_qs),
+ .wd (alert_en_shadowed_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en_shadowed[58].q),
+
+ // to register interface (read)
+ .qs (alert_en_shadowed_58_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.alert_en_shadowed[58].err_update),
+ .err_storage (reg2hw.alert_en_shadowed[58].err_storage)
+ );
+
+
// Subregister 0 of Multireg alert_class_shadowed
// R[alert_class_shadowed_0]: V(False)
prim_subreg_shadow #(
@@ -7065,6 +7139,39 @@
);
+ // Subregister 58 of Multireg alert_class_shadowed
+ // R[alert_class_shadowed_58]: V(False)
+ prim_subreg_shadow #(
+ .DW (2),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (2'h0)
+ ) u_alert_class_shadowed_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .rst_shadowed_ni (rst_shadowed_ni),
+
+ // from register interface
+ .re (alert_class_shadowed_58_re),
+ .we (alert_class_shadowed_58_we & alert_regwen_58_qs),
+ .wd (alert_class_shadowed_58_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class_shadowed[58].q),
+
+ // to register interface (read)
+ .qs (alert_class_shadowed_58_qs),
+
+ // Shadow register error conditions
+ .err_update (reg2hw.alert_class_shadowed[58].err_update),
+ .err_storage (reg2hw.alert_class_shadowed[58].err_storage)
+ );
+
+
// Subregister 0 of Multireg alert_cause
// R[alert_cause_0]: V(False)
prim_subreg #(
@@ -8631,6 +8738,33 @@
);
+ // Subregister 58 of Multireg alert_cause
+ // R[alert_cause_58]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW1C),
+ .RESVAL (1'h0)
+ ) u_alert_cause_58 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_58_we),
+ .wd (alert_cause_58_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[58].de),
+ .d (hw2reg.alert_cause[58].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[58].q),
+
+ // to register interface (read)
+ .qs (alert_cause_58_qs)
+ );
+
+
// Subregister 0 of Multireg loc_alert_regwen
// R[loc_alert_regwen_0]: V(False)
prim_subreg #(
@@ -12132,7 +12266,7 @@
- logic [321:0] addr_hit;
+ logic [325:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -12199,264 +12333,268 @@
addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_55_OFFSET);
addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_56_OFFSET);
addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET);
- addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
- addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
- addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
- addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
- addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
- addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
- addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
- addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
- addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
- addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
- addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
- addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
- addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
- addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
- addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
- addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
- addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
- addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
- addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
- addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
- addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
- addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
- addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
- addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
- addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
- addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
- addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
- addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
- addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
- addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
- addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
- addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
- addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
- addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
- addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
- addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
- addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
- addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
- addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
- addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
- addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
- addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
- addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
- addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
- addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
- addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
- addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
- addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
- addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
- addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
- addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
- addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
- addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
- addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
- addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
- addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
- addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
- addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
- addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
- addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
- addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
- addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
- addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
- addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
- addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
- addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
- addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
- addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
- addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
- addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
- addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
- addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
- addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
- addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
- addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
- addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
- addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
- addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
- addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
- addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
- addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
- addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
- addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
- addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
- addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
- addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
- addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
- addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
- addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
- addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
- addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
- addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
- addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
- addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
- addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
- addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
- addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
- addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
- addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
- addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
- addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
- addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
- addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
- addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
- addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
- addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
- addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
- addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
- addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
- addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
- addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
- addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
- addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
- addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
- addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
- addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
- addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
- addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
- addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
- addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
- addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
- addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
- addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
- addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
- addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
- addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
- addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
- addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
- addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
- addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
- addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
- addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
- addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
- addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
- addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
- addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
- addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
- addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
- addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
- addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
- addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
- addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
- addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
- addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
- addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
- addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
- addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
- addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
- addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
- addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
- addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
- addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
- addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
- addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
- addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
- addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
- addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
- addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
- addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
- addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
- addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
- addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
- addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
- addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
- addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
- addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
- addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
- addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
- addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
- addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
- addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
- addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
- addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
- addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
- addr_hit[238] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
- addr_hit[239] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
- addr_hit[240] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
- addr_hit[241] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
- addr_hit[242] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
- addr_hit[243] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
- addr_hit[244] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
- addr_hit[245] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
- addr_hit[246] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
- addr_hit[247] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
- addr_hit[248] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
- addr_hit[249] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
- addr_hit[250] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
- addr_hit[251] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
- addr_hit[252] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
- addr_hit[253] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
- addr_hit[254] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
- addr_hit[255] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
- addr_hit[256] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
- addr_hit[257] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
- addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
- addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
- addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
- addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
- addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
- addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
- addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
- addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
- addr_hit[266] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
- addr_hit[267] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
- addr_hit[268] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
- addr_hit[269] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
- addr_hit[270] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
- addr_hit[271] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[272] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[273] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[274] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[275] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[276] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[277] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
- addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
- addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
- addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
- addr_hit[282] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
- addr_hit[283] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
- addr_hit[284] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
- addr_hit[285] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
- addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
- addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
- addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
- addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
- addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
- addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
- addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
- addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
- addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
- addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
- addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
- addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
- addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
- addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
- addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
- addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
- addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
- addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
- addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
- addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
- addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
- addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET);
+ addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
+ addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
+ addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
+ addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
+ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
+ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
+ addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
+ addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
+ addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
+ addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
+ addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
+ addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
+ addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
+ addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
+ addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
+ addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
+ addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
+ addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
+ addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
+ addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
+ addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
+ addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
+ addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
+ addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
+ addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
+ addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
+ addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
+ addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
+ addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
+ addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
+ addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
+ addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
+ addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
+ addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
+ addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
+ addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
+ addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
+ addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
+ addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
+ addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
+ addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
+ addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
+ addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
+ addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
+ addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
+ addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
+ addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
+ addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
+ addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
+ addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
+ addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
+ addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
+ addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
+ addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
+ addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
+ addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
+ addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
+ addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
+ addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
+ addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
+ addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
+ addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
+ addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
+ addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
+ addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
+ addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
+ addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
+ addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
+ addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
+ addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
+ addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
+ addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
+ addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
+ addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
+ addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
+ addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
+ addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
+ addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
+ addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
+ addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
+ addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
+ addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
+ addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
+ addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
+ addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
+ addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
+ addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
+ addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
+ addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
+ addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
+ addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
+ addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
+ addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
+ addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
+ addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
+ addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
+ addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
+ addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
+ addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
+ addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
+ addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
+ addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
+ addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
+ addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
+ addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
+ addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
+ addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
+ addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
+ addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
+ addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
+ addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
+ addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
+ addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
+ addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
+ addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
+ addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
+ addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
+ addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
+ addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+ addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+ addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+ addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+ addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+ addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+ addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+ addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+ addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+ addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+ addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+ addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+ addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+ addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+ addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+ addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+ addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+ addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+ addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+ addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+ addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+ addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+ addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+ addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+ addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+ addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+ addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+ addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+ addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+ addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+ addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+ addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+ addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+ addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+ addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+ addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+ addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+ addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+ addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+ addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+ addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+ addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
+ addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
+ addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
+ addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
+ addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
+ addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
+ addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
+ addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
+ addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
+ addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
+ addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
+ addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
+ addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
+ addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
+ addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
+ addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
+ addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
+ addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
+ addr_hit[242] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+ addr_hit[243] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+ addr_hit[244] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+ addr_hit[245] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+ addr_hit[246] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+ addr_hit[247] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
+ addr_hit[248] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
+ addr_hit[249] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
+ addr_hit[250] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
+ addr_hit[251] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
+ addr_hit[252] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
+ addr_hit[253] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
+ addr_hit[254] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
+ addr_hit[255] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
+ addr_hit[256] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
+ addr_hit[257] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
+ addr_hit[258] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
+ addr_hit[259] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
+ addr_hit[260] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
+ addr_hit[261] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
+ addr_hit[262] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
+ addr_hit[263] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+ addr_hit[264] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+ addr_hit[265] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+ addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+ addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+ addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
+ addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
+ addr_hit[270] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+ addr_hit[271] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
+ addr_hit[272] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+ addr_hit[273] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
+ addr_hit[274] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[275] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[276] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[277] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[278] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[279] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[280] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[281] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[282] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[283] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[284] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+ addr_hit[285] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
+ addr_hit[286] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+ addr_hit[287] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
+ addr_hit[288] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[289] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[290] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[291] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[292] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[293] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+ addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
+ addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+ addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
+ addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+ addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
+ addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+ addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
+ addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
+ addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
+ addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
+ addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
+ addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
+ addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
+ addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
+ addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -12785,7 +12923,11 @@
(addr_hit[318] & (|(ALERT_HANDLER_PERMIT[318] & ~reg_be))) |
(addr_hit[319] & (|(ALERT_HANDLER_PERMIT[319] & ~reg_be))) |
(addr_hit[320] & (|(ALERT_HANDLER_PERMIT[320] & ~reg_be))) |
- (addr_hit[321] & (|(ALERT_HANDLER_PERMIT[321] & ~reg_be)))));
+ (addr_hit[321] & (|(ALERT_HANDLER_PERMIT[321] & ~reg_be))) |
+ (addr_hit[322] & (|(ALERT_HANDLER_PERMIT[322] & ~reg_be))) |
+ (addr_hit[323] & (|(ALERT_HANDLER_PERMIT[323] & ~reg_be))) |
+ (addr_hit[324] & (|(ALERT_HANDLER_PERMIT[324] & ~reg_be))) |
+ (addr_hit[325] & (|(ALERT_HANDLER_PERMIT[325] & ~reg_be)))));
end
assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
@@ -12999,747 +13141,761 @@
assign alert_regwen_57_we = addr_hit[63] & reg_we & !reg_error;
assign alert_regwen_57_wd = reg_wdata[0];
- assign alert_en_shadowed_0_re = addr_hit[64] & reg_re & !reg_error;
- assign alert_en_shadowed_0_we = addr_hit[64] & reg_we & !reg_error;
+ assign alert_regwen_58_we = addr_hit[64] & reg_we & !reg_error;
+
+ assign alert_regwen_58_wd = reg_wdata[0];
+ assign alert_en_shadowed_0_re = addr_hit[65] & reg_re & !reg_error;
+ assign alert_en_shadowed_0_we = addr_hit[65] & reg_we & !reg_error;
assign alert_en_shadowed_0_wd = reg_wdata[0];
- assign alert_en_shadowed_1_re = addr_hit[65] & reg_re & !reg_error;
- assign alert_en_shadowed_1_we = addr_hit[65] & reg_we & !reg_error;
+ assign alert_en_shadowed_1_re = addr_hit[66] & reg_re & !reg_error;
+ assign alert_en_shadowed_1_we = addr_hit[66] & reg_we & !reg_error;
assign alert_en_shadowed_1_wd = reg_wdata[0];
- assign alert_en_shadowed_2_re = addr_hit[66] & reg_re & !reg_error;
- assign alert_en_shadowed_2_we = addr_hit[66] & reg_we & !reg_error;
+ assign alert_en_shadowed_2_re = addr_hit[67] & reg_re & !reg_error;
+ assign alert_en_shadowed_2_we = addr_hit[67] & reg_we & !reg_error;
assign alert_en_shadowed_2_wd = reg_wdata[0];
- assign alert_en_shadowed_3_re = addr_hit[67] & reg_re & !reg_error;
- assign alert_en_shadowed_3_we = addr_hit[67] & reg_we & !reg_error;
+ assign alert_en_shadowed_3_re = addr_hit[68] & reg_re & !reg_error;
+ assign alert_en_shadowed_3_we = addr_hit[68] & reg_we & !reg_error;
assign alert_en_shadowed_3_wd = reg_wdata[0];
- assign alert_en_shadowed_4_re = addr_hit[68] & reg_re & !reg_error;
- assign alert_en_shadowed_4_we = addr_hit[68] & reg_we & !reg_error;
+ assign alert_en_shadowed_4_re = addr_hit[69] & reg_re & !reg_error;
+ assign alert_en_shadowed_4_we = addr_hit[69] & reg_we & !reg_error;
assign alert_en_shadowed_4_wd = reg_wdata[0];
- assign alert_en_shadowed_5_re = addr_hit[69] & reg_re & !reg_error;
- assign alert_en_shadowed_5_we = addr_hit[69] & reg_we & !reg_error;
+ assign alert_en_shadowed_5_re = addr_hit[70] & reg_re & !reg_error;
+ assign alert_en_shadowed_5_we = addr_hit[70] & reg_we & !reg_error;
assign alert_en_shadowed_5_wd = reg_wdata[0];
- assign alert_en_shadowed_6_re = addr_hit[70] & reg_re & !reg_error;
- assign alert_en_shadowed_6_we = addr_hit[70] & reg_we & !reg_error;
+ assign alert_en_shadowed_6_re = addr_hit[71] & reg_re & !reg_error;
+ assign alert_en_shadowed_6_we = addr_hit[71] & reg_we & !reg_error;
assign alert_en_shadowed_6_wd = reg_wdata[0];
- assign alert_en_shadowed_7_re = addr_hit[71] & reg_re & !reg_error;
- assign alert_en_shadowed_7_we = addr_hit[71] & reg_we & !reg_error;
+ assign alert_en_shadowed_7_re = addr_hit[72] & reg_re & !reg_error;
+ assign alert_en_shadowed_7_we = addr_hit[72] & reg_we & !reg_error;
assign alert_en_shadowed_7_wd = reg_wdata[0];
- assign alert_en_shadowed_8_re = addr_hit[72] & reg_re & !reg_error;
- assign alert_en_shadowed_8_we = addr_hit[72] & reg_we & !reg_error;
+ assign alert_en_shadowed_8_re = addr_hit[73] & reg_re & !reg_error;
+ assign alert_en_shadowed_8_we = addr_hit[73] & reg_we & !reg_error;
assign alert_en_shadowed_8_wd = reg_wdata[0];
- assign alert_en_shadowed_9_re = addr_hit[73] & reg_re & !reg_error;
- assign alert_en_shadowed_9_we = addr_hit[73] & reg_we & !reg_error;
+ assign alert_en_shadowed_9_re = addr_hit[74] & reg_re & !reg_error;
+ assign alert_en_shadowed_9_we = addr_hit[74] & reg_we & !reg_error;
assign alert_en_shadowed_9_wd = reg_wdata[0];
- assign alert_en_shadowed_10_re = addr_hit[74] & reg_re & !reg_error;
- assign alert_en_shadowed_10_we = addr_hit[74] & reg_we & !reg_error;
+ assign alert_en_shadowed_10_re = addr_hit[75] & reg_re & !reg_error;
+ assign alert_en_shadowed_10_we = addr_hit[75] & reg_we & !reg_error;
assign alert_en_shadowed_10_wd = reg_wdata[0];
- assign alert_en_shadowed_11_re = addr_hit[75] & reg_re & !reg_error;
- assign alert_en_shadowed_11_we = addr_hit[75] & reg_we & !reg_error;
+ assign alert_en_shadowed_11_re = addr_hit[76] & reg_re & !reg_error;
+ assign alert_en_shadowed_11_we = addr_hit[76] & reg_we & !reg_error;
assign alert_en_shadowed_11_wd = reg_wdata[0];
- assign alert_en_shadowed_12_re = addr_hit[76] & reg_re & !reg_error;
- assign alert_en_shadowed_12_we = addr_hit[76] & reg_we & !reg_error;
+ assign alert_en_shadowed_12_re = addr_hit[77] & reg_re & !reg_error;
+ assign alert_en_shadowed_12_we = addr_hit[77] & reg_we & !reg_error;
assign alert_en_shadowed_12_wd = reg_wdata[0];
- assign alert_en_shadowed_13_re = addr_hit[77] & reg_re & !reg_error;
- assign alert_en_shadowed_13_we = addr_hit[77] & reg_we & !reg_error;
+ assign alert_en_shadowed_13_re = addr_hit[78] & reg_re & !reg_error;
+ assign alert_en_shadowed_13_we = addr_hit[78] & reg_we & !reg_error;
assign alert_en_shadowed_13_wd = reg_wdata[0];
- assign alert_en_shadowed_14_re = addr_hit[78] & reg_re & !reg_error;
- assign alert_en_shadowed_14_we = addr_hit[78] & reg_we & !reg_error;
+ assign alert_en_shadowed_14_re = addr_hit[79] & reg_re & !reg_error;
+ assign alert_en_shadowed_14_we = addr_hit[79] & reg_we & !reg_error;
assign alert_en_shadowed_14_wd = reg_wdata[0];
- assign alert_en_shadowed_15_re = addr_hit[79] & reg_re & !reg_error;
- assign alert_en_shadowed_15_we = addr_hit[79] & reg_we & !reg_error;
+ assign alert_en_shadowed_15_re = addr_hit[80] & reg_re & !reg_error;
+ assign alert_en_shadowed_15_we = addr_hit[80] & reg_we & !reg_error;
assign alert_en_shadowed_15_wd = reg_wdata[0];
- assign alert_en_shadowed_16_re = addr_hit[80] & reg_re & !reg_error;
- assign alert_en_shadowed_16_we = addr_hit[80] & reg_we & !reg_error;
+ assign alert_en_shadowed_16_re = addr_hit[81] & reg_re & !reg_error;
+ assign alert_en_shadowed_16_we = addr_hit[81] & reg_we & !reg_error;
assign alert_en_shadowed_16_wd = reg_wdata[0];
- assign alert_en_shadowed_17_re = addr_hit[81] & reg_re & !reg_error;
- assign alert_en_shadowed_17_we = addr_hit[81] & reg_we & !reg_error;
+ assign alert_en_shadowed_17_re = addr_hit[82] & reg_re & !reg_error;
+ assign alert_en_shadowed_17_we = addr_hit[82] & reg_we & !reg_error;
assign alert_en_shadowed_17_wd = reg_wdata[0];
- assign alert_en_shadowed_18_re = addr_hit[82] & reg_re & !reg_error;
- assign alert_en_shadowed_18_we = addr_hit[82] & reg_we & !reg_error;
+ assign alert_en_shadowed_18_re = addr_hit[83] & reg_re & !reg_error;
+ assign alert_en_shadowed_18_we = addr_hit[83] & reg_we & !reg_error;
assign alert_en_shadowed_18_wd = reg_wdata[0];
- assign alert_en_shadowed_19_re = addr_hit[83] & reg_re & !reg_error;
- assign alert_en_shadowed_19_we = addr_hit[83] & reg_we & !reg_error;
+ assign alert_en_shadowed_19_re = addr_hit[84] & reg_re & !reg_error;
+ assign alert_en_shadowed_19_we = addr_hit[84] & reg_we & !reg_error;
assign alert_en_shadowed_19_wd = reg_wdata[0];
- assign alert_en_shadowed_20_re = addr_hit[84] & reg_re & !reg_error;
- assign alert_en_shadowed_20_we = addr_hit[84] & reg_we & !reg_error;
+ assign alert_en_shadowed_20_re = addr_hit[85] & reg_re & !reg_error;
+ assign alert_en_shadowed_20_we = addr_hit[85] & reg_we & !reg_error;
assign alert_en_shadowed_20_wd = reg_wdata[0];
- assign alert_en_shadowed_21_re = addr_hit[85] & reg_re & !reg_error;
- assign alert_en_shadowed_21_we = addr_hit[85] & reg_we & !reg_error;
+ assign alert_en_shadowed_21_re = addr_hit[86] & reg_re & !reg_error;
+ assign alert_en_shadowed_21_we = addr_hit[86] & reg_we & !reg_error;
assign alert_en_shadowed_21_wd = reg_wdata[0];
- assign alert_en_shadowed_22_re = addr_hit[86] & reg_re & !reg_error;
- assign alert_en_shadowed_22_we = addr_hit[86] & reg_we & !reg_error;
+ assign alert_en_shadowed_22_re = addr_hit[87] & reg_re & !reg_error;
+ assign alert_en_shadowed_22_we = addr_hit[87] & reg_we & !reg_error;
assign alert_en_shadowed_22_wd = reg_wdata[0];
- assign alert_en_shadowed_23_re = addr_hit[87] & reg_re & !reg_error;
- assign alert_en_shadowed_23_we = addr_hit[87] & reg_we & !reg_error;
+ assign alert_en_shadowed_23_re = addr_hit[88] & reg_re & !reg_error;
+ assign alert_en_shadowed_23_we = addr_hit[88] & reg_we & !reg_error;
assign alert_en_shadowed_23_wd = reg_wdata[0];
- assign alert_en_shadowed_24_re = addr_hit[88] & reg_re & !reg_error;
- assign alert_en_shadowed_24_we = addr_hit[88] & reg_we & !reg_error;
+ assign alert_en_shadowed_24_re = addr_hit[89] & reg_re & !reg_error;
+ assign alert_en_shadowed_24_we = addr_hit[89] & reg_we & !reg_error;
assign alert_en_shadowed_24_wd = reg_wdata[0];
- assign alert_en_shadowed_25_re = addr_hit[89] & reg_re & !reg_error;
- assign alert_en_shadowed_25_we = addr_hit[89] & reg_we & !reg_error;
+ assign alert_en_shadowed_25_re = addr_hit[90] & reg_re & !reg_error;
+ assign alert_en_shadowed_25_we = addr_hit[90] & reg_we & !reg_error;
assign alert_en_shadowed_25_wd = reg_wdata[0];
- assign alert_en_shadowed_26_re = addr_hit[90] & reg_re & !reg_error;
- assign alert_en_shadowed_26_we = addr_hit[90] & reg_we & !reg_error;
+ assign alert_en_shadowed_26_re = addr_hit[91] & reg_re & !reg_error;
+ assign alert_en_shadowed_26_we = addr_hit[91] & reg_we & !reg_error;
assign alert_en_shadowed_26_wd = reg_wdata[0];
- assign alert_en_shadowed_27_re = addr_hit[91] & reg_re & !reg_error;
- assign alert_en_shadowed_27_we = addr_hit[91] & reg_we & !reg_error;
+ assign alert_en_shadowed_27_re = addr_hit[92] & reg_re & !reg_error;
+ assign alert_en_shadowed_27_we = addr_hit[92] & reg_we & !reg_error;
assign alert_en_shadowed_27_wd = reg_wdata[0];
- assign alert_en_shadowed_28_re = addr_hit[92] & reg_re & !reg_error;
- assign alert_en_shadowed_28_we = addr_hit[92] & reg_we & !reg_error;
+ assign alert_en_shadowed_28_re = addr_hit[93] & reg_re & !reg_error;
+ assign alert_en_shadowed_28_we = addr_hit[93] & reg_we & !reg_error;
assign alert_en_shadowed_28_wd = reg_wdata[0];
- assign alert_en_shadowed_29_re = addr_hit[93] & reg_re & !reg_error;
- assign alert_en_shadowed_29_we = addr_hit[93] & reg_we & !reg_error;
+ assign alert_en_shadowed_29_re = addr_hit[94] & reg_re & !reg_error;
+ assign alert_en_shadowed_29_we = addr_hit[94] & reg_we & !reg_error;
assign alert_en_shadowed_29_wd = reg_wdata[0];
- assign alert_en_shadowed_30_re = addr_hit[94] & reg_re & !reg_error;
- assign alert_en_shadowed_30_we = addr_hit[94] & reg_we & !reg_error;
+ assign alert_en_shadowed_30_re = addr_hit[95] & reg_re & !reg_error;
+ assign alert_en_shadowed_30_we = addr_hit[95] & reg_we & !reg_error;
assign alert_en_shadowed_30_wd = reg_wdata[0];
- assign alert_en_shadowed_31_re = addr_hit[95] & reg_re & !reg_error;
- assign alert_en_shadowed_31_we = addr_hit[95] & reg_we & !reg_error;
+ assign alert_en_shadowed_31_re = addr_hit[96] & reg_re & !reg_error;
+ assign alert_en_shadowed_31_we = addr_hit[96] & reg_we & !reg_error;
assign alert_en_shadowed_31_wd = reg_wdata[0];
- assign alert_en_shadowed_32_re = addr_hit[96] & reg_re & !reg_error;
- assign alert_en_shadowed_32_we = addr_hit[96] & reg_we & !reg_error;
+ assign alert_en_shadowed_32_re = addr_hit[97] & reg_re & !reg_error;
+ assign alert_en_shadowed_32_we = addr_hit[97] & reg_we & !reg_error;
assign alert_en_shadowed_32_wd = reg_wdata[0];
- assign alert_en_shadowed_33_re = addr_hit[97] & reg_re & !reg_error;
- assign alert_en_shadowed_33_we = addr_hit[97] & reg_we & !reg_error;
+ assign alert_en_shadowed_33_re = addr_hit[98] & reg_re & !reg_error;
+ assign alert_en_shadowed_33_we = addr_hit[98] & reg_we & !reg_error;
assign alert_en_shadowed_33_wd = reg_wdata[0];
- assign alert_en_shadowed_34_re = addr_hit[98] & reg_re & !reg_error;
- assign alert_en_shadowed_34_we = addr_hit[98] & reg_we & !reg_error;
+ assign alert_en_shadowed_34_re = addr_hit[99] & reg_re & !reg_error;
+ assign alert_en_shadowed_34_we = addr_hit[99] & reg_we & !reg_error;
assign alert_en_shadowed_34_wd = reg_wdata[0];
- assign alert_en_shadowed_35_re = addr_hit[99] & reg_re & !reg_error;
- assign alert_en_shadowed_35_we = addr_hit[99] & reg_we & !reg_error;
+ assign alert_en_shadowed_35_re = addr_hit[100] & reg_re & !reg_error;
+ assign alert_en_shadowed_35_we = addr_hit[100] & reg_we & !reg_error;
assign alert_en_shadowed_35_wd = reg_wdata[0];
- assign alert_en_shadowed_36_re = addr_hit[100] & reg_re & !reg_error;
- assign alert_en_shadowed_36_we = addr_hit[100] & reg_we & !reg_error;
+ assign alert_en_shadowed_36_re = addr_hit[101] & reg_re & !reg_error;
+ assign alert_en_shadowed_36_we = addr_hit[101] & reg_we & !reg_error;
assign alert_en_shadowed_36_wd = reg_wdata[0];
- assign alert_en_shadowed_37_re = addr_hit[101] & reg_re & !reg_error;
- assign alert_en_shadowed_37_we = addr_hit[101] & reg_we & !reg_error;
+ assign alert_en_shadowed_37_re = addr_hit[102] & reg_re & !reg_error;
+ assign alert_en_shadowed_37_we = addr_hit[102] & reg_we & !reg_error;
assign alert_en_shadowed_37_wd = reg_wdata[0];
- assign alert_en_shadowed_38_re = addr_hit[102] & reg_re & !reg_error;
- assign alert_en_shadowed_38_we = addr_hit[102] & reg_we & !reg_error;
+ assign alert_en_shadowed_38_re = addr_hit[103] & reg_re & !reg_error;
+ assign alert_en_shadowed_38_we = addr_hit[103] & reg_we & !reg_error;
assign alert_en_shadowed_38_wd = reg_wdata[0];
- assign alert_en_shadowed_39_re = addr_hit[103] & reg_re & !reg_error;
- assign alert_en_shadowed_39_we = addr_hit[103] & reg_we & !reg_error;
+ assign alert_en_shadowed_39_re = addr_hit[104] & reg_re & !reg_error;
+ assign alert_en_shadowed_39_we = addr_hit[104] & reg_we & !reg_error;
assign alert_en_shadowed_39_wd = reg_wdata[0];
- assign alert_en_shadowed_40_re = addr_hit[104] & reg_re & !reg_error;
- assign alert_en_shadowed_40_we = addr_hit[104] & reg_we & !reg_error;
+ assign alert_en_shadowed_40_re = addr_hit[105] & reg_re & !reg_error;
+ assign alert_en_shadowed_40_we = addr_hit[105] & reg_we & !reg_error;
assign alert_en_shadowed_40_wd = reg_wdata[0];
- assign alert_en_shadowed_41_re = addr_hit[105] & reg_re & !reg_error;
- assign alert_en_shadowed_41_we = addr_hit[105] & reg_we & !reg_error;
+ assign alert_en_shadowed_41_re = addr_hit[106] & reg_re & !reg_error;
+ assign alert_en_shadowed_41_we = addr_hit[106] & reg_we & !reg_error;
assign alert_en_shadowed_41_wd = reg_wdata[0];
- assign alert_en_shadowed_42_re = addr_hit[106] & reg_re & !reg_error;
- assign alert_en_shadowed_42_we = addr_hit[106] & reg_we & !reg_error;
+ assign alert_en_shadowed_42_re = addr_hit[107] & reg_re & !reg_error;
+ assign alert_en_shadowed_42_we = addr_hit[107] & reg_we & !reg_error;
assign alert_en_shadowed_42_wd = reg_wdata[0];
- assign alert_en_shadowed_43_re = addr_hit[107] & reg_re & !reg_error;
- assign alert_en_shadowed_43_we = addr_hit[107] & reg_we & !reg_error;
+ assign alert_en_shadowed_43_re = addr_hit[108] & reg_re & !reg_error;
+ assign alert_en_shadowed_43_we = addr_hit[108] & reg_we & !reg_error;
assign alert_en_shadowed_43_wd = reg_wdata[0];
- assign alert_en_shadowed_44_re = addr_hit[108] & reg_re & !reg_error;
- assign alert_en_shadowed_44_we = addr_hit[108] & reg_we & !reg_error;
+ assign alert_en_shadowed_44_re = addr_hit[109] & reg_re & !reg_error;
+ assign alert_en_shadowed_44_we = addr_hit[109] & reg_we & !reg_error;
assign alert_en_shadowed_44_wd = reg_wdata[0];
- assign alert_en_shadowed_45_re = addr_hit[109] & reg_re & !reg_error;
- assign alert_en_shadowed_45_we = addr_hit[109] & reg_we & !reg_error;
+ assign alert_en_shadowed_45_re = addr_hit[110] & reg_re & !reg_error;
+ assign alert_en_shadowed_45_we = addr_hit[110] & reg_we & !reg_error;
assign alert_en_shadowed_45_wd = reg_wdata[0];
- assign alert_en_shadowed_46_re = addr_hit[110] & reg_re & !reg_error;
- assign alert_en_shadowed_46_we = addr_hit[110] & reg_we & !reg_error;
+ assign alert_en_shadowed_46_re = addr_hit[111] & reg_re & !reg_error;
+ assign alert_en_shadowed_46_we = addr_hit[111] & reg_we & !reg_error;
assign alert_en_shadowed_46_wd = reg_wdata[0];
- assign alert_en_shadowed_47_re = addr_hit[111] & reg_re & !reg_error;
- assign alert_en_shadowed_47_we = addr_hit[111] & reg_we & !reg_error;
+ assign alert_en_shadowed_47_re = addr_hit[112] & reg_re & !reg_error;
+ assign alert_en_shadowed_47_we = addr_hit[112] & reg_we & !reg_error;
assign alert_en_shadowed_47_wd = reg_wdata[0];
- assign alert_en_shadowed_48_re = addr_hit[112] & reg_re & !reg_error;
- assign alert_en_shadowed_48_we = addr_hit[112] & reg_we & !reg_error;
+ assign alert_en_shadowed_48_re = addr_hit[113] & reg_re & !reg_error;
+ assign alert_en_shadowed_48_we = addr_hit[113] & reg_we & !reg_error;
assign alert_en_shadowed_48_wd = reg_wdata[0];
- assign alert_en_shadowed_49_re = addr_hit[113] & reg_re & !reg_error;
- assign alert_en_shadowed_49_we = addr_hit[113] & reg_we & !reg_error;
+ assign alert_en_shadowed_49_re = addr_hit[114] & reg_re & !reg_error;
+ assign alert_en_shadowed_49_we = addr_hit[114] & reg_we & !reg_error;
assign alert_en_shadowed_49_wd = reg_wdata[0];
- assign alert_en_shadowed_50_re = addr_hit[114] & reg_re & !reg_error;
- assign alert_en_shadowed_50_we = addr_hit[114] & reg_we & !reg_error;
+ assign alert_en_shadowed_50_re = addr_hit[115] & reg_re & !reg_error;
+ assign alert_en_shadowed_50_we = addr_hit[115] & reg_we & !reg_error;
assign alert_en_shadowed_50_wd = reg_wdata[0];
- assign alert_en_shadowed_51_re = addr_hit[115] & reg_re & !reg_error;
- assign alert_en_shadowed_51_we = addr_hit[115] & reg_we & !reg_error;
+ assign alert_en_shadowed_51_re = addr_hit[116] & reg_re & !reg_error;
+ assign alert_en_shadowed_51_we = addr_hit[116] & reg_we & !reg_error;
assign alert_en_shadowed_51_wd = reg_wdata[0];
- assign alert_en_shadowed_52_re = addr_hit[116] & reg_re & !reg_error;
- assign alert_en_shadowed_52_we = addr_hit[116] & reg_we & !reg_error;
+ assign alert_en_shadowed_52_re = addr_hit[117] & reg_re & !reg_error;
+ assign alert_en_shadowed_52_we = addr_hit[117] & reg_we & !reg_error;
assign alert_en_shadowed_52_wd = reg_wdata[0];
- assign alert_en_shadowed_53_re = addr_hit[117] & reg_re & !reg_error;
- assign alert_en_shadowed_53_we = addr_hit[117] & reg_we & !reg_error;
+ assign alert_en_shadowed_53_re = addr_hit[118] & reg_re & !reg_error;
+ assign alert_en_shadowed_53_we = addr_hit[118] & reg_we & !reg_error;
assign alert_en_shadowed_53_wd = reg_wdata[0];
- assign alert_en_shadowed_54_re = addr_hit[118] & reg_re & !reg_error;
- assign alert_en_shadowed_54_we = addr_hit[118] & reg_we & !reg_error;
+ assign alert_en_shadowed_54_re = addr_hit[119] & reg_re & !reg_error;
+ assign alert_en_shadowed_54_we = addr_hit[119] & reg_we & !reg_error;
assign alert_en_shadowed_54_wd = reg_wdata[0];
- assign alert_en_shadowed_55_re = addr_hit[119] & reg_re & !reg_error;
- assign alert_en_shadowed_55_we = addr_hit[119] & reg_we & !reg_error;
+ assign alert_en_shadowed_55_re = addr_hit[120] & reg_re & !reg_error;
+ assign alert_en_shadowed_55_we = addr_hit[120] & reg_we & !reg_error;
assign alert_en_shadowed_55_wd = reg_wdata[0];
- assign alert_en_shadowed_56_re = addr_hit[120] & reg_re & !reg_error;
- assign alert_en_shadowed_56_we = addr_hit[120] & reg_we & !reg_error;
+ assign alert_en_shadowed_56_re = addr_hit[121] & reg_re & !reg_error;
+ assign alert_en_shadowed_56_we = addr_hit[121] & reg_we & !reg_error;
assign alert_en_shadowed_56_wd = reg_wdata[0];
- assign alert_en_shadowed_57_re = addr_hit[121] & reg_re & !reg_error;
- assign alert_en_shadowed_57_we = addr_hit[121] & reg_we & !reg_error;
+ assign alert_en_shadowed_57_re = addr_hit[122] & reg_re & !reg_error;
+ assign alert_en_shadowed_57_we = addr_hit[122] & reg_we & !reg_error;
assign alert_en_shadowed_57_wd = reg_wdata[0];
- assign alert_class_shadowed_0_re = addr_hit[122] & reg_re & !reg_error;
- assign alert_class_shadowed_0_we = addr_hit[122] & reg_we & !reg_error;
+ assign alert_en_shadowed_58_re = addr_hit[123] & reg_re & !reg_error;
+ assign alert_en_shadowed_58_we = addr_hit[123] & reg_we & !reg_error;
+
+ assign alert_en_shadowed_58_wd = reg_wdata[0];
+ assign alert_class_shadowed_0_re = addr_hit[124] & reg_re & !reg_error;
+ assign alert_class_shadowed_0_we = addr_hit[124] & reg_we & !reg_error;
assign alert_class_shadowed_0_wd = reg_wdata[1:0];
- assign alert_class_shadowed_1_re = addr_hit[123] & reg_re & !reg_error;
- assign alert_class_shadowed_1_we = addr_hit[123] & reg_we & !reg_error;
+ assign alert_class_shadowed_1_re = addr_hit[125] & reg_re & !reg_error;
+ assign alert_class_shadowed_1_we = addr_hit[125] & reg_we & !reg_error;
assign alert_class_shadowed_1_wd = reg_wdata[1:0];
- assign alert_class_shadowed_2_re = addr_hit[124] & reg_re & !reg_error;
- assign alert_class_shadowed_2_we = addr_hit[124] & reg_we & !reg_error;
+ assign alert_class_shadowed_2_re = addr_hit[126] & reg_re & !reg_error;
+ assign alert_class_shadowed_2_we = addr_hit[126] & reg_we & !reg_error;
assign alert_class_shadowed_2_wd = reg_wdata[1:0];
- assign alert_class_shadowed_3_re = addr_hit[125] & reg_re & !reg_error;
- assign alert_class_shadowed_3_we = addr_hit[125] & reg_we & !reg_error;
+ assign alert_class_shadowed_3_re = addr_hit[127] & reg_re & !reg_error;
+ assign alert_class_shadowed_3_we = addr_hit[127] & reg_we & !reg_error;
assign alert_class_shadowed_3_wd = reg_wdata[1:0];
- assign alert_class_shadowed_4_re = addr_hit[126] & reg_re & !reg_error;
- assign alert_class_shadowed_4_we = addr_hit[126] & reg_we & !reg_error;
+ assign alert_class_shadowed_4_re = addr_hit[128] & reg_re & !reg_error;
+ assign alert_class_shadowed_4_we = addr_hit[128] & reg_we & !reg_error;
assign alert_class_shadowed_4_wd = reg_wdata[1:0];
- assign alert_class_shadowed_5_re = addr_hit[127] & reg_re & !reg_error;
- assign alert_class_shadowed_5_we = addr_hit[127] & reg_we & !reg_error;
+ assign alert_class_shadowed_5_re = addr_hit[129] & reg_re & !reg_error;
+ assign alert_class_shadowed_5_we = addr_hit[129] & reg_we & !reg_error;
assign alert_class_shadowed_5_wd = reg_wdata[1:0];
- assign alert_class_shadowed_6_re = addr_hit[128] & reg_re & !reg_error;
- assign alert_class_shadowed_6_we = addr_hit[128] & reg_we & !reg_error;
+ assign alert_class_shadowed_6_re = addr_hit[130] & reg_re & !reg_error;
+ assign alert_class_shadowed_6_we = addr_hit[130] & reg_we & !reg_error;
assign alert_class_shadowed_6_wd = reg_wdata[1:0];
- assign alert_class_shadowed_7_re = addr_hit[129] & reg_re & !reg_error;
- assign alert_class_shadowed_7_we = addr_hit[129] & reg_we & !reg_error;
+ assign alert_class_shadowed_7_re = addr_hit[131] & reg_re & !reg_error;
+ assign alert_class_shadowed_7_we = addr_hit[131] & reg_we & !reg_error;
assign alert_class_shadowed_7_wd = reg_wdata[1:0];
- assign alert_class_shadowed_8_re = addr_hit[130] & reg_re & !reg_error;
- assign alert_class_shadowed_8_we = addr_hit[130] & reg_we & !reg_error;
+ assign alert_class_shadowed_8_re = addr_hit[132] & reg_re & !reg_error;
+ assign alert_class_shadowed_8_we = addr_hit[132] & reg_we & !reg_error;
assign alert_class_shadowed_8_wd = reg_wdata[1:0];
- assign alert_class_shadowed_9_re = addr_hit[131] & reg_re & !reg_error;
- assign alert_class_shadowed_9_we = addr_hit[131] & reg_we & !reg_error;
+ assign alert_class_shadowed_9_re = addr_hit[133] & reg_re & !reg_error;
+ assign alert_class_shadowed_9_we = addr_hit[133] & reg_we & !reg_error;
assign alert_class_shadowed_9_wd = reg_wdata[1:0];
- assign alert_class_shadowed_10_re = addr_hit[132] & reg_re & !reg_error;
- assign alert_class_shadowed_10_we = addr_hit[132] & reg_we & !reg_error;
+ assign alert_class_shadowed_10_re = addr_hit[134] & reg_re & !reg_error;
+ assign alert_class_shadowed_10_we = addr_hit[134] & reg_we & !reg_error;
assign alert_class_shadowed_10_wd = reg_wdata[1:0];
- assign alert_class_shadowed_11_re = addr_hit[133] & reg_re & !reg_error;
- assign alert_class_shadowed_11_we = addr_hit[133] & reg_we & !reg_error;
+ assign alert_class_shadowed_11_re = addr_hit[135] & reg_re & !reg_error;
+ assign alert_class_shadowed_11_we = addr_hit[135] & reg_we & !reg_error;
assign alert_class_shadowed_11_wd = reg_wdata[1:0];
- assign alert_class_shadowed_12_re = addr_hit[134] & reg_re & !reg_error;
- assign alert_class_shadowed_12_we = addr_hit[134] & reg_we & !reg_error;
+ assign alert_class_shadowed_12_re = addr_hit[136] & reg_re & !reg_error;
+ assign alert_class_shadowed_12_we = addr_hit[136] & reg_we & !reg_error;
assign alert_class_shadowed_12_wd = reg_wdata[1:0];
- assign alert_class_shadowed_13_re = addr_hit[135] & reg_re & !reg_error;
- assign alert_class_shadowed_13_we = addr_hit[135] & reg_we & !reg_error;
+ assign alert_class_shadowed_13_re = addr_hit[137] & reg_re & !reg_error;
+ assign alert_class_shadowed_13_we = addr_hit[137] & reg_we & !reg_error;
assign alert_class_shadowed_13_wd = reg_wdata[1:0];
- assign alert_class_shadowed_14_re = addr_hit[136] & reg_re & !reg_error;
- assign alert_class_shadowed_14_we = addr_hit[136] & reg_we & !reg_error;
+ assign alert_class_shadowed_14_re = addr_hit[138] & reg_re & !reg_error;
+ assign alert_class_shadowed_14_we = addr_hit[138] & reg_we & !reg_error;
assign alert_class_shadowed_14_wd = reg_wdata[1:0];
- assign alert_class_shadowed_15_re = addr_hit[137] & reg_re & !reg_error;
- assign alert_class_shadowed_15_we = addr_hit[137] & reg_we & !reg_error;
+ assign alert_class_shadowed_15_re = addr_hit[139] & reg_re & !reg_error;
+ assign alert_class_shadowed_15_we = addr_hit[139] & reg_we & !reg_error;
assign alert_class_shadowed_15_wd = reg_wdata[1:0];
- assign alert_class_shadowed_16_re = addr_hit[138] & reg_re & !reg_error;
- assign alert_class_shadowed_16_we = addr_hit[138] & reg_we & !reg_error;
+ assign alert_class_shadowed_16_re = addr_hit[140] & reg_re & !reg_error;
+ assign alert_class_shadowed_16_we = addr_hit[140] & reg_we & !reg_error;
assign alert_class_shadowed_16_wd = reg_wdata[1:0];
- assign alert_class_shadowed_17_re = addr_hit[139] & reg_re & !reg_error;
- assign alert_class_shadowed_17_we = addr_hit[139] & reg_we & !reg_error;
+ assign alert_class_shadowed_17_re = addr_hit[141] & reg_re & !reg_error;
+ assign alert_class_shadowed_17_we = addr_hit[141] & reg_we & !reg_error;
assign alert_class_shadowed_17_wd = reg_wdata[1:0];
- assign alert_class_shadowed_18_re = addr_hit[140] & reg_re & !reg_error;
- assign alert_class_shadowed_18_we = addr_hit[140] & reg_we & !reg_error;
+ assign alert_class_shadowed_18_re = addr_hit[142] & reg_re & !reg_error;
+ assign alert_class_shadowed_18_we = addr_hit[142] & reg_we & !reg_error;
assign alert_class_shadowed_18_wd = reg_wdata[1:0];
- assign alert_class_shadowed_19_re = addr_hit[141] & reg_re & !reg_error;
- assign alert_class_shadowed_19_we = addr_hit[141] & reg_we & !reg_error;
+ assign alert_class_shadowed_19_re = addr_hit[143] & reg_re & !reg_error;
+ assign alert_class_shadowed_19_we = addr_hit[143] & reg_we & !reg_error;
assign alert_class_shadowed_19_wd = reg_wdata[1:0];
- assign alert_class_shadowed_20_re = addr_hit[142] & reg_re & !reg_error;
- assign alert_class_shadowed_20_we = addr_hit[142] & reg_we & !reg_error;
+ assign alert_class_shadowed_20_re = addr_hit[144] & reg_re & !reg_error;
+ assign alert_class_shadowed_20_we = addr_hit[144] & reg_we & !reg_error;
assign alert_class_shadowed_20_wd = reg_wdata[1:0];
- assign alert_class_shadowed_21_re = addr_hit[143] & reg_re & !reg_error;
- assign alert_class_shadowed_21_we = addr_hit[143] & reg_we & !reg_error;
+ assign alert_class_shadowed_21_re = addr_hit[145] & reg_re & !reg_error;
+ assign alert_class_shadowed_21_we = addr_hit[145] & reg_we & !reg_error;
assign alert_class_shadowed_21_wd = reg_wdata[1:0];
- assign alert_class_shadowed_22_re = addr_hit[144] & reg_re & !reg_error;
- assign alert_class_shadowed_22_we = addr_hit[144] & reg_we & !reg_error;
+ assign alert_class_shadowed_22_re = addr_hit[146] & reg_re & !reg_error;
+ assign alert_class_shadowed_22_we = addr_hit[146] & reg_we & !reg_error;
assign alert_class_shadowed_22_wd = reg_wdata[1:0];
- assign alert_class_shadowed_23_re = addr_hit[145] & reg_re & !reg_error;
- assign alert_class_shadowed_23_we = addr_hit[145] & reg_we & !reg_error;
+ assign alert_class_shadowed_23_re = addr_hit[147] & reg_re & !reg_error;
+ assign alert_class_shadowed_23_we = addr_hit[147] & reg_we & !reg_error;
assign alert_class_shadowed_23_wd = reg_wdata[1:0];
- assign alert_class_shadowed_24_re = addr_hit[146] & reg_re & !reg_error;
- assign alert_class_shadowed_24_we = addr_hit[146] & reg_we & !reg_error;
+ assign alert_class_shadowed_24_re = addr_hit[148] & reg_re & !reg_error;
+ assign alert_class_shadowed_24_we = addr_hit[148] & reg_we & !reg_error;
assign alert_class_shadowed_24_wd = reg_wdata[1:0];
- assign alert_class_shadowed_25_re = addr_hit[147] & reg_re & !reg_error;
- assign alert_class_shadowed_25_we = addr_hit[147] & reg_we & !reg_error;
+ assign alert_class_shadowed_25_re = addr_hit[149] & reg_re & !reg_error;
+ assign alert_class_shadowed_25_we = addr_hit[149] & reg_we & !reg_error;
assign alert_class_shadowed_25_wd = reg_wdata[1:0];
- assign alert_class_shadowed_26_re = addr_hit[148] & reg_re & !reg_error;
- assign alert_class_shadowed_26_we = addr_hit[148] & reg_we & !reg_error;
+ assign alert_class_shadowed_26_re = addr_hit[150] & reg_re & !reg_error;
+ assign alert_class_shadowed_26_we = addr_hit[150] & reg_we & !reg_error;
assign alert_class_shadowed_26_wd = reg_wdata[1:0];
- assign alert_class_shadowed_27_re = addr_hit[149] & reg_re & !reg_error;
- assign alert_class_shadowed_27_we = addr_hit[149] & reg_we & !reg_error;
+ assign alert_class_shadowed_27_re = addr_hit[151] & reg_re & !reg_error;
+ assign alert_class_shadowed_27_we = addr_hit[151] & reg_we & !reg_error;
assign alert_class_shadowed_27_wd = reg_wdata[1:0];
- assign alert_class_shadowed_28_re = addr_hit[150] & reg_re & !reg_error;
- assign alert_class_shadowed_28_we = addr_hit[150] & reg_we & !reg_error;
+ assign alert_class_shadowed_28_re = addr_hit[152] & reg_re & !reg_error;
+ assign alert_class_shadowed_28_we = addr_hit[152] & reg_we & !reg_error;
assign alert_class_shadowed_28_wd = reg_wdata[1:0];
- assign alert_class_shadowed_29_re = addr_hit[151] & reg_re & !reg_error;
- assign alert_class_shadowed_29_we = addr_hit[151] & reg_we & !reg_error;
+ assign alert_class_shadowed_29_re = addr_hit[153] & reg_re & !reg_error;
+ assign alert_class_shadowed_29_we = addr_hit[153] & reg_we & !reg_error;
assign alert_class_shadowed_29_wd = reg_wdata[1:0];
- assign alert_class_shadowed_30_re = addr_hit[152] & reg_re & !reg_error;
- assign alert_class_shadowed_30_we = addr_hit[152] & reg_we & !reg_error;
+ assign alert_class_shadowed_30_re = addr_hit[154] & reg_re & !reg_error;
+ assign alert_class_shadowed_30_we = addr_hit[154] & reg_we & !reg_error;
assign alert_class_shadowed_30_wd = reg_wdata[1:0];
- assign alert_class_shadowed_31_re = addr_hit[153] & reg_re & !reg_error;
- assign alert_class_shadowed_31_we = addr_hit[153] & reg_we & !reg_error;
+ assign alert_class_shadowed_31_re = addr_hit[155] & reg_re & !reg_error;
+ assign alert_class_shadowed_31_we = addr_hit[155] & reg_we & !reg_error;
assign alert_class_shadowed_31_wd = reg_wdata[1:0];
- assign alert_class_shadowed_32_re = addr_hit[154] & reg_re & !reg_error;
- assign alert_class_shadowed_32_we = addr_hit[154] & reg_we & !reg_error;
+ assign alert_class_shadowed_32_re = addr_hit[156] & reg_re & !reg_error;
+ assign alert_class_shadowed_32_we = addr_hit[156] & reg_we & !reg_error;
assign alert_class_shadowed_32_wd = reg_wdata[1:0];
- assign alert_class_shadowed_33_re = addr_hit[155] & reg_re & !reg_error;
- assign alert_class_shadowed_33_we = addr_hit[155] & reg_we & !reg_error;
+ assign alert_class_shadowed_33_re = addr_hit[157] & reg_re & !reg_error;
+ assign alert_class_shadowed_33_we = addr_hit[157] & reg_we & !reg_error;
assign alert_class_shadowed_33_wd = reg_wdata[1:0];
- assign alert_class_shadowed_34_re = addr_hit[156] & reg_re & !reg_error;
- assign alert_class_shadowed_34_we = addr_hit[156] & reg_we & !reg_error;
+ assign alert_class_shadowed_34_re = addr_hit[158] & reg_re & !reg_error;
+ assign alert_class_shadowed_34_we = addr_hit[158] & reg_we & !reg_error;
assign alert_class_shadowed_34_wd = reg_wdata[1:0];
- assign alert_class_shadowed_35_re = addr_hit[157] & reg_re & !reg_error;
- assign alert_class_shadowed_35_we = addr_hit[157] & reg_we & !reg_error;
+ assign alert_class_shadowed_35_re = addr_hit[159] & reg_re & !reg_error;
+ assign alert_class_shadowed_35_we = addr_hit[159] & reg_we & !reg_error;
assign alert_class_shadowed_35_wd = reg_wdata[1:0];
- assign alert_class_shadowed_36_re = addr_hit[158] & reg_re & !reg_error;
- assign alert_class_shadowed_36_we = addr_hit[158] & reg_we & !reg_error;
+ assign alert_class_shadowed_36_re = addr_hit[160] & reg_re & !reg_error;
+ assign alert_class_shadowed_36_we = addr_hit[160] & reg_we & !reg_error;
assign alert_class_shadowed_36_wd = reg_wdata[1:0];
- assign alert_class_shadowed_37_re = addr_hit[159] & reg_re & !reg_error;
- assign alert_class_shadowed_37_we = addr_hit[159] & reg_we & !reg_error;
+ assign alert_class_shadowed_37_re = addr_hit[161] & reg_re & !reg_error;
+ assign alert_class_shadowed_37_we = addr_hit[161] & reg_we & !reg_error;
assign alert_class_shadowed_37_wd = reg_wdata[1:0];
- assign alert_class_shadowed_38_re = addr_hit[160] & reg_re & !reg_error;
- assign alert_class_shadowed_38_we = addr_hit[160] & reg_we & !reg_error;
+ assign alert_class_shadowed_38_re = addr_hit[162] & reg_re & !reg_error;
+ assign alert_class_shadowed_38_we = addr_hit[162] & reg_we & !reg_error;
assign alert_class_shadowed_38_wd = reg_wdata[1:0];
- assign alert_class_shadowed_39_re = addr_hit[161] & reg_re & !reg_error;
- assign alert_class_shadowed_39_we = addr_hit[161] & reg_we & !reg_error;
+ assign alert_class_shadowed_39_re = addr_hit[163] & reg_re & !reg_error;
+ assign alert_class_shadowed_39_we = addr_hit[163] & reg_we & !reg_error;
assign alert_class_shadowed_39_wd = reg_wdata[1:0];
- assign alert_class_shadowed_40_re = addr_hit[162] & reg_re & !reg_error;
- assign alert_class_shadowed_40_we = addr_hit[162] & reg_we & !reg_error;
+ assign alert_class_shadowed_40_re = addr_hit[164] & reg_re & !reg_error;
+ assign alert_class_shadowed_40_we = addr_hit[164] & reg_we & !reg_error;
assign alert_class_shadowed_40_wd = reg_wdata[1:0];
- assign alert_class_shadowed_41_re = addr_hit[163] & reg_re & !reg_error;
- assign alert_class_shadowed_41_we = addr_hit[163] & reg_we & !reg_error;
+ assign alert_class_shadowed_41_re = addr_hit[165] & reg_re & !reg_error;
+ assign alert_class_shadowed_41_we = addr_hit[165] & reg_we & !reg_error;
assign alert_class_shadowed_41_wd = reg_wdata[1:0];
- assign alert_class_shadowed_42_re = addr_hit[164] & reg_re & !reg_error;
- assign alert_class_shadowed_42_we = addr_hit[164] & reg_we & !reg_error;
+ assign alert_class_shadowed_42_re = addr_hit[166] & reg_re & !reg_error;
+ assign alert_class_shadowed_42_we = addr_hit[166] & reg_we & !reg_error;
assign alert_class_shadowed_42_wd = reg_wdata[1:0];
- assign alert_class_shadowed_43_re = addr_hit[165] & reg_re & !reg_error;
- assign alert_class_shadowed_43_we = addr_hit[165] & reg_we & !reg_error;
+ assign alert_class_shadowed_43_re = addr_hit[167] & reg_re & !reg_error;
+ assign alert_class_shadowed_43_we = addr_hit[167] & reg_we & !reg_error;
assign alert_class_shadowed_43_wd = reg_wdata[1:0];
- assign alert_class_shadowed_44_re = addr_hit[166] & reg_re & !reg_error;
- assign alert_class_shadowed_44_we = addr_hit[166] & reg_we & !reg_error;
+ assign alert_class_shadowed_44_re = addr_hit[168] & reg_re & !reg_error;
+ assign alert_class_shadowed_44_we = addr_hit[168] & reg_we & !reg_error;
assign alert_class_shadowed_44_wd = reg_wdata[1:0];
- assign alert_class_shadowed_45_re = addr_hit[167] & reg_re & !reg_error;
- assign alert_class_shadowed_45_we = addr_hit[167] & reg_we & !reg_error;
+ assign alert_class_shadowed_45_re = addr_hit[169] & reg_re & !reg_error;
+ assign alert_class_shadowed_45_we = addr_hit[169] & reg_we & !reg_error;
assign alert_class_shadowed_45_wd = reg_wdata[1:0];
- assign alert_class_shadowed_46_re = addr_hit[168] & reg_re & !reg_error;
- assign alert_class_shadowed_46_we = addr_hit[168] & reg_we & !reg_error;
+ assign alert_class_shadowed_46_re = addr_hit[170] & reg_re & !reg_error;
+ assign alert_class_shadowed_46_we = addr_hit[170] & reg_we & !reg_error;
assign alert_class_shadowed_46_wd = reg_wdata[1:0];
- assign alert_class_shadowed_47_re = addr_hit[169] & reg_re & !reg_error;
- assign alert_class_shadowed_47_we = addr_hit[169] & reg_we & !reg_error;
+ assign alert_class_shadowed_47_re = addr_hit[171] & reg_re & !reg_error;
+ assign alert_class_shadowed_47_we = addr_hit[171] & reg_we & !reg_error;
assign alert_class_shadowed_47_wd = reg_wdata[1:0];
- assign alert_class_shadowed_48_re = addr_hit[170] & reg_re & !reg_error;
- assign alert_class_shadowed_48_we = addr_hit[170] & reg_we & !reg_error;
+ assign alert_class_shadowed_48_re = addr_hit[172] & reg_re & !reg_error;
+ assign alert_class_shadowed_48_we = addr_hit[172] & reg_we & !reg_error;
assign alert_class_shadowed_48_wd = reg_wdata[1:0];
- assign alert_class_shadowed_49_re = addr_hit[171] & reg_re & !reg_error;
- assign alert_class_shadowed_49_we = addr_hit[171] & reg_we & !reg_error;
+ assign alert_class_shadowed_49_re = addr_hit[173] & reg_re & !reg_error;
+ assign alert_class_shadowed_49_we = addr_hit[173] & reg_we & !reg_error;
assign alert_class_shadowed_49_wd = reg_wdata[1:0];
- assign alert_class_shadowed_50_re = addr_hit[172] & reg_re & !reg_error;
- assign alert_class_shadowed_50_we = addr_hit[172] & reg_we & !reg_error;
+ assign alert_class_shadowed_50_re = addr_hit[174] & reg_re & !reg_error;
+ assign alert_class_shadowed_50_we = addr_hit[174] & reg_we & !reg_error;
assign alert_class_shadowed_50_wd = reg_wdata[1:0];
- assign alert_class_shadowed_51_re = addr_hit[173] & reg_re & !reg_error;
- assign alert_class_shadowed_51_we = addr_hit[173] & reg_we & !reg_error;
+ assign alert_class_shadowed_51_re = addr_hit[175] & reg_re & !reg_error;
+ assign alert_class_shadowed_51_we = addr_hit[175] & reg_we & !reg_error;
assign alert_class_shadowed_51_wd = reg_wdata[1:0];
- assign alert_class_shadowed_52_re = addr_hit[174] & reg_re & !reg_error;
- assign alert_class_shadowed_52_we = addr_hit[174] & reg_we & !reg_error;
+ assign alert_class_shadowed_52_re = addr_hit[176] & reg_re & !reg_error;
+ assign alert_class_shadowed_52_we = addr_hit[176] & reg_we & !reg_error;
assign alert_class_shadowed_52_wd = reg_wdata[1:0];
- assign alert_class_shadowed_53_re = addr_hit[175] & reg_re & !reg_error;
- assign alert_class_shadowed_53_we = addr_hit[175] & reg_we & !reg_error;
+ assign alert_class_shadowed_53_re = addr_hit[177] & reg_re & !reg_error;
+ assign alert_class_shadowed_53_we = addr_hit[177] & reg_we & !reg_error;
assign alert_class_shadowed_53_wd = reg_wdata[1:0];
- assign alert_class_shadowed_54_re = addr_hit[176] & reg_re & !reg_error;
- assign alert_class_shadowed_54_we = addr_hit[176] & reg_we & !reg_error;
+ assign alert_class_shadowed_54_re = addr_hit[178] & reg_re & !reg_error;
+ assign alert_class_shadowed_54_we = addr_hit[178] & reg_we & !reg_error;
assign alert_class_shadowed_54_wd = reg_wdata[1:0];
- assign alert_class_shadowed_55_re = addr_hit[177] & reg_re & !reg_error;
- assign alert_class_shadowed_55_we = addr_hit[177] & reg_we & !reg_error;
+ assign alert_class_shadowed_55_re = addr_hit[179] & reg_re & !reg_error;
+ assign alert_class_shadowed_55_we = addr_hit[179] & reg_we & !reg_error;
assign alert_class_shadowed_55_wd = reg_wdata[1:0];
- assign alert_class_shadowed_56_re = addr_hit[178] & reg_re & !reg_error;
- assign alert_class_shadowed_56_we = addr_hit[178] & reg_we & !reg_error;
+ assign alert_class_shadowed_56_re = addr_hit[180] & reg_re & !reg_error;
+ assign alert_class_shadowed_56_we = addr_hit[180] & reg_we & !reg_error;
assign alert_class_shadowed_56_wd = reg_wdata[1:0];
- assign alert_class_shadowed_57_re = addr_hit[179] & reg_re & !reg_error;
- assign alert_class_shadowed_57_we = addr_hit[179] & reg_we & !reg_error;
+ assign alert_class_shadowed_57_re = addr_hit[181] & reg_re & !reg_error;
+ assign alert_class_shadowed_57_we = addr_hit[181] & reg_we & !reg_error;
assign alert_class_shadowed_57_wd = reg_wdata[1:0];
- assign alert_cause_0_we = addr_hit[180] & reg_we & !reg_error;
+ assign alert_class_shadowed_58_re = addr_hit[182] & reg_re & !reg_error;
+ assign alert_class_shadowed_58_we = addr_hit[182] & reg_we & !reg_error;
+
+ assign alert_class_shadowed_58_wd = reg_wdata[1:0];
+ assign alert_cause_0_we = addr_hit[183] & reg_we & !reg_error;
assign alert_cause_0_wd = reg_wdata[0];
- assign alert_cause_1_we = addr_hit[181] & reg_we & !reg_error;
+ assign alert_cause_1_we = addr_hit[184] & reg_we & !reg_error;
assign alert_cause_1_wd = reg_wdata[0];
- assign alert_cause_2_we = addr_hit[182] & reg_we & !reg_error;
+ assign alert_cause_2_we = addr_hit[185] & reg_we & !reg_error;
assign alert_cause_2_wd = reg_wdata[0];
- assign alert_cause_3_we = addr_hit[183] & reg_we & !reg_error;
+ assign alert_cause_3_we = addr_hit[186] & reg_we & !reg_error;
assign alert_cause_3_wd = reg_wdata[0];
- assign alert_cause_4_we = addr_hit[184] & reg_we & !reg_error;
+ assign alert_cause_4_we = addr_hit[187] & reg_we & !reg_error;
assign alert_cause_4_wd = reg_wdata[0];
- assign alert_cause_5_we = addr_hit[185] & reg_we & !reg_error;
+ assign alert_cause_5_we = addr_hit[188] & reg_we & !reg_error;
assign alert_cause_5_wd = reg_wdata[0];
- assign alert_cause_6_we = addr_hit[186] & reg_we & !reg_error;
+ assign alert_cause_6_we = addr_hit[189] & reg_we & !reg_error;
assign alert_cause_6_wd = reg_wdata[0];
- assign alert_cause_7_we = addr_hit[187] & reg_we & !reg_error;
+ assign alert_cause_7_we = addr_hit[190] & reg_we & !reg_error;
assign alert_cause_7_wd = reg_wdata[0];
- assign alert_cause_8_we = addr_hit[188] & reg_we & !reg_error;
+ assign alert_cause_8_we = addr_hit[191] & reg_we & !reg_error;
assign alert_cause_8_wd = reg_wdata[0];
- assign alert_cause_9_we = addr_hit[189] & reg_we & !reg_error;
+ assign alert_cause_9_we = addr_hit[192] & reg_we & !reg_error;
assign alert_cause_9_wd = reg_wdata[0];
- assign alert_cause_10_we = addr_hit[190] & reg_we & !reg_error;
+ assign alert_cause_10_we = addr_hit[193] & reg_we & !reg_error;
assign alert_cause_10_wd = reg_wdata[0];
- assign alert_cause_11_we = addr_hit[191] & reg_we & !reg_error;
+ assign alert_cause_11_we = addr_hit[194] & reg_we & !reg_error;
assign alert_cause_11_wd = reg_wdata[0];
- assign alert_cause_12_we = addr_hit[192] & reg_we & !reg_error;
+ assign alert_cause_12_we = addr_hit[195] & reg_we & !reg_error;
assign alert_cause_12_wd = reg_wdata[0];
- assign alert_cause_13_we = addr_hit[193] & reg_we & !reg_error;
+ assign alert_cause_13_we = addr_hit[196] & reg_we & !reg_error;
assign alert_cause_13_wd = reg_wdata[0];
- assign alert_cause_14_we = addr_hit[194] & reg_we & !reg_error;
+ assign alert_cause_14_we = addr_hit[197] & reg_we & !reg_error;
assign alert_cause_14_wd = reg_wdata[0];
- assign alert_cause_15_we = addr_hit[195] & reg_we & !reg_error;
+ assign alert_cause_15_we = addr_hit[198] & reg_we & !reg_error;
assign alert_cause_15_wd = reg_wdata[0];
- assign alert_cause_16_we = addr_hit[196] & reg_we & !reg_error;
+ assign alert_cause_16_we = addr_hit[199] & reg_we & !reg_error;
assign alert_cause_16_wd = reg_wdata[0];
- assign alert_cause_17_we = addr_hit[197] & reg_we & !reg_error;
+ assign alert_cause_17_we = addr_hit[200] & reg_we & !reg_error;
assign alert_cause_17_wd = reg_wdata[0];
- assign alert_cause_18_we = addr_hit[198] & reg_we & !reg_error;
+ assign alert_cause_18_we = addr_hit[201] & reg_we & !reg_error;
assign alert_cause_18_wd = reg_wdata[0];
- assign alert_cause_19_we = addr_hit[199] & reg_we & !reg_error;
+ assign alert_cause_19_we = addr_hit[202] & reg_we & !reg_error;
assign alert_cause_19_wd = reg_wdata[0];
- assign alert_cause_20_we = addr_hit[200] & reg_we & !reg_error;
+ assign alert_cause_20_we = addr_hit[203] & reg_we & !reg_error;
assign alert_cause_20_wd = reg_wdata[0];
- assign alert_cause_21_we = addr_hit[201] & reg_we & !reg_error;
+ assign alert_cause_21_we = addr_hit[204] & reg_we & !reg_error;
assign alert_cause_21_wd = reg_wdata[0];
- assign alert_cause_22_we = addr_hit[202] & reg_we & !reg_error;
+ assign alert_cause_22_we = addr_hit[205] & reg_we & !reg_error;
assign alert_cause_22_wd = reg_wdata[0];
- assign alert_cause_23_we = addr_hit[203] & reg_we & !reg_error;
+ assign alert_cause_23_we = addr_hit[206] & reg_we & !reg_error;
assign alert_cause_23_wd = reg_wdata[0];
- assign alert_cause_24_we = addr_hit[204] & reg_we & !reg_error;
+ assign alert_cause_24_we = addr_hit[207] & reg_we & !reg_error;
assign alert_cause_24_wd = reg_wdata[0];
- assign alert_cause_25_we = addr_hit[205] & reg_we & !reg_error;
+ assign alert_cause_25_we = addr_hit[208] & reg_we & !reg_error;
assign alert_cause_25_wd = reg_wdata[0];
- assign alert_cause_26_we = addr_hit[206] & reg_we & !reg_error;
+ assign alert_cause_26_we = addr_hit[209] & reg_we & !reg_error;
assign alert_cause_26_wd = reg_wdata[0];
- assign alert_cause_27_we = addr_hit[207] & reg_we & !reg_error;
+ assign alert_cause_27_we = addr_hit[210] & reg_we & !reg_error;
assign alert_cause_27_wd = reg_wdata[0];
- assign alert_cause_28_we = addr_hit[208] & reg_we & !reg_error;
+ assign alert_cause_28_we = addr_hit[211] & reg_we & !reg_error;
assign alert_cause_28_wd = reg_wdata[0];
- assign alert_cause_29_we = addr_hit[209] & reg_we & !reg_error;
+ assign alert_cause_29_we = addr_hit[212] & reg_we & !reg_error;
assign alert_cause_29_wd = reg_wdata[0];
- assign alert_cause_30_we = addr_hit[210] & reg_we & !reg_error;
+ assign alert_cause_30_we = addr_hit[213] & reg_we & !reg_error;
assign alert_cause_30_wd = reg_wdata[0];
- assign alert_cause_31_we = addr_hit[211] & reg_we & !reg_error;
+ assign alert_cause_31_we = addr_hit[214] & reg_we & !reg_error;
assign alert_cause_31_wd = reg_wdata[0];
- assign alert_cause_32_we = addr_hit[212] & reg_we & !reg_error;
+ assign alert_cause_32_we = addr_hit[215] & reg_we & !reg_error;
assign alert_cause_32_wd = reg_wdata[0];
- assign alert_cause_33_we = addr_hit[213] & reg_we & !reg_error;
+ assign alert_cause_33_we = addr_hit[216] & reg_we & !reg_error;
assign alert_cause_33_wd = reg_wdata[0];
- assign alert_cause_34_we = addr_hit[214] & reg_we & !reg_error;
+ assign alert_cause_34_we = addr_hit[217] & reg_we & !reg_error;
assign alert_cause_34_wd = reg_wdata[0];
- assign alert_cause_35_we = addr_hit[215] & reg_we & !reg_error;
+ assign alert_cause_35_we = addr_hit[218] & reg_we & !reg_error;
assign alert_cause_35_wd = reg_wdata[0];
- assign alert_cause_36_we = addr_hit[216] & reg_we & !reg_error;
+ assign alert_cause_36_we = addr_hit[219] & reg_we & !reg_error;
assign alert_cause_36_wd = reg_wdata[0];
- assign alert_cause_37_we = addr_hit[217] & reg_we & !reg_error;
+ assign alert_cause_37_we = addr_hit[220] & reg_we & !reg_error;
assign alert_cause_37_wd = reg_wdata[0];
- assign alert_cause_38_we = addr_hit[218] & reg_we & !reg_error;
+ assign alert_cause_38_we = addr_hit[221] & reg_we & !reg_error;
assign alert_cause_38_wd = reg_wdata[0];
- assign alert_cause_39_we = addr_hit[219] & reg_we & !reg_error;
+ assign alert_cause_39_we = addr_hit[222] & reg_we & !reg_error;
assign alert_cause_39_wd = reg_wdata[0];
- assign alert_cause_40_we = addr_hit[220] & reg_we & !reg_error;
+ assign alert_cause_40_we = addr_hit[223] & reg_we & !reg_error;
assign alert_cause_40_wd = reg_wdata[0];
- assign alert_cause_41_we = addr_hit[221] & reg_we & !reg_error;
+ assign alert_cause_41_we = addr_hit[224] & reg_we & !reg_error;
assign alert_cause_41_wd = reg_wdata[0];
- assign alert_cause_42_we = addr_hit[222] & reg_we & !reg_error;
+ assign alert_cause_42_we = addr_hit[225] & reg_we & !reg_error;
assign alert_cause_42_wd = reg_wdata[0];
- assign alert_cause_43_we = addr_hit[223] & reg_we & !reg_error;
+ assign alert_cause_43_we = addr_hit[226] & reg_we & !reg_error;
assign alert_cause_43_wd = reg_wdata[0];
- assign alert_cause_44_we = addr_hit[224] & reg_we & !reg_error;
+ assign alert_cause_44_we = addr_hit[227] & reg_we & !reg_error;
assign alert_cause_44_wd = reg_wdata[0];
- assign alert_cause_45_we = addr_hit[225] & reg_we & !reg_error;
+ assign alert_cause_45_we = addr_hit[228] & reg_we & !reg_error;
assign alert_cause_45_wd = reg_wdata[0];
- assign alert_cause_46_we = addr_hit[226] & reg_we & !reg_error;
+ assign alert_cause_46_we = addr_hit[229] & reg_we & !reg_error;
assign alert_cause_46_wd = reg_wdata[0];
- assign alert_cause_47_we = addr_hit[227] & reg_we & !reg_error;
+ assign alert_cause_47_we = addr_hit[230] & reg_we & !reg_error;
assign alert_cause_47_wd = reg_wdata[0];
- assign alert_cause_48_we = addr_hit[228] & reg_we & !reg_error;
+ assign alert_cause_48_we = addr_hit[231] & reg_we & !reg_error;
assign alert_cause_48_wd = reg_wdata[0];
- assign alert_cause_49_we = addr_hit[229] & reg_we & !reg_error;
+ assign alert_cause_49_we = addr_hit[232] & reg_we & !reg_error;
assign alert_cause_49_wd = reg_wdata[0];
- assign alert_cause_50_we = addr_hit[230] & reg_we & !reg_error;
+ assign alert_cause_50_we = addr_hit[233] & reg_we & !reg_error;
assign alert_cause_50_wd = reg_wdata[0];
- assign alert_cause_51_we = addr_hit[231] & reg_we & !reg_error;
+ assign alert_cause_51_we = addr_hit[234] & reg_we & !reg_error;
assign alert_cause_51_wd = reg_wdata[0];
- assign alert_cause_52_we = addr_hit[232] & reg_we & !reg_error;
+ assign alert_cause_52_we = addr_hit[235] & reg_we & !reg_error;
assign alert_cause_52_wd = reg_wdata[0];
- assign alert_cause_53_we = addr_hit[233] & reg_we & !reg_error;
+ assign alert_cause_53_we = addr_hit[236] & reg_we & !reg_error;
assign alert_cause_53_wd = reg_wdata[0];
- assign alert_cause_54_we = addr_hit[234] & reg_we & !reg_error;
+ assign alert_cause_54_we = addr_hit[237] & reg_we & !reg_error;
assign alert_cause_54_wd = reg_wdata[0];
- assign alert_cause_55_we = addr_hit[235] & reg_we & !reg_error;
+ assign alert_cause_55_we = addr_hit[238] & reg_we & !reg_error;
assign alert_cause_55_wd = reg_wdata[0];
- assign alert_cause_56_we = addr_hit[236] & reg_we & !reg_error;
+ assign alert_cause_56_we = addr_hit[239] & reg_we & !reg_error;
assign alert_cause_56_wd = reg_wdata[0];
- assign alert_cause_57_we = addr_hit[237] & reg_we & !reg_error;
+ assign alert_cause_57_we = addr_hit[240] & reg_we & !reg_error;
assign alert_cause_57_wd = reg_wdata[0];
- assign loc_alert_regwen_0_we = addr_hit[238] & reg_we & !reg_error;
+ assign alert_cause_58_we = addr_hit[241] & reg_we & !reg_error;
+
+ assign alert_cause_58_wd = reg_wdata[0];
+ assign loc_alert_regwen_0_we = addr_hit[242] & reg_we & !reg_error;
assign loc_alert_regwen_0_wd = reg_wdata[0];
- assign loc_alert_regwen_1_we = addr_hit[239] & reg_we & !reg_error;
+ assign loc_alert_regwen_1_we = addr_hit[243] & reg_we & !reg_error;
assign loc_alert_regwen_1_wd = reg_wdata[0];
- assign loc_alert_regwen_2_we = addr_hit[240] & reg_we & !reg_error;
+ assign loc_alert_regwen_2_we = addr_hit[244] & reg_we & !reg_error;
assign loc_alert_regwen_2_wd = reg_wdata[0];
- assign loc_alert_regwen_3_we = addr_hit[241] & reg_we & !reg_error;
+ assign loc_alert_regwen_3_we = addr_hit[245] & reg_we & !reg_error;
assign loc_alert_regwen_3_wd = reg_wdata[0];
- assign loc_alert_regwen_4_we = addr_hit[242] & reg_we & !reg_error;
+ assign loc_alert_regwen_4_we = addr_hit[246] & reg_we & !reg_error;
assign loc_alert_regwen_4_wd = reg_wdata[0];
- assign loc_alert_regwen_5_we = addr_hit[243] & reg_we & !reg_error;
+ assign loc_alert_regwen_5_we = addr_hit[247] & reg_we & !reg_error;
assign loc_alert_regwen_5_wd = reg_wdata[0];
- assign loc_alert_regwen_6_we = addr_hit[244] & reg_we & !reg_error;
+ assign loc_alert_regwen_6_we = addr_hit[248] & reg_we & !reg_error;
assign loc_alert_regwen_6_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_0_re = addr_hit[245] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_0_we = addr_hit[245] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_0_re = addr_hit[249] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_0_we = addr_hit[249] & reg_we & !reg_error;
assign loc_alert_en_shadowed_0_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_1_re = addr_hit[246] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_1_we = addr_hit[246] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_1_re = addr_hit[250] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_1_we = addr_hit[250] & reg_we & !reg_error;
assign loc_alert_en_shadowed_1_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_2_re = addr_hit[247] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_2_we = addr_hit[247] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_2_re = addr_hit[251] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_2_we = addr_hit[251] & reg_we & !reg_error;
assign loc_alert_en_shadowed_2_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_3_re = addr_hit[248] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_3_we = addr_hit[248] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_3_re = addr_hit[252] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_3_we = addr_hit[252] & reg_we & !reg_error;
assign loc_alert_en_shadowed_3_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_4_re = addr_hit[249] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_4_we = addr_hit[249] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_4_re = addr_hit[253] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_4_we = addr_hit[253] & reg_we & !reg_error;
assign loc_alert_en_shadowed_4_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_5_re = addr_hit[250] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_5_we = addr_hit[250] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_5_re = addr_hit[254] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_5_we = addr_hit[254] & reg_we & !reg_error;
assign loc_alert_en_shadowed_5_wd = reg_wdata[0];
- assign loc_alert_en_shadowed_6_re = addr_hit[251] & reg_re & !reg_error;
- assign loc_alert_en_shadowed_6_we = addr_hit[251] & reg_we & !reg_error;
+ assign loc_alert_en_shadowed_6_re = addr_hit[255] & reg_re & !reg_error;
+ assign loc_alert_en_shadowed_6_we = addr_hit[255] & reg_we & !reg_error;
assign loc_alert_en_shadowed_6_wd = reg_wdata[0];
- assign loc_alert_class_shadowed_0_re = addr_hit[252] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_0_we = addr_hit[252] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_0_re = addr_hit[256] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_0_we = addr_hit[256] & reg_we & !reg_error;
assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_1_re = addr_hit[253] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_1_we = addr_hit[253] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_1_re = addr_hit[257] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_1_we = addr_hit[257] & reg_we & !reg_error;
assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_2_re = addr_hit[254] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_2_we = addr_hit[254] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_2_re = addr_hit[258] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_2_we = addr_hit[258] & reg_we & !reg_error;
assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_3_re = addr_hit[255] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_3_we = addr_hit[255] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_3_re = addr_hit[259] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_3_we = addr_hit[259] & reg_we & !reg_error;
assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_4_re = addr_hit[256] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_4_we = addr_hit[256] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_4_re = addr_hit[260] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_4_we = addr_hit[260] & reg_we & !reg_error;
assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_5_re = addr_hit[257] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_5_we = addr_hit[257] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_5_re = addr_hit[261] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_5_we = addr_hit[261] & reg_we & !reg_error;
assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0];
- assign loc_alert_class_shadowed_6_re = addr_hit[258] & reg_re & !reg_error;
- assign loc_alert_class_shadowed_6_we = addr_hit[258] & reg_we & !reg_error;
+ assign loc_alert_class_shadowed_6_re = addr_hit[262] & reg_re & !reg_error;
+ assign loc_alert_class_shadowed_6_we = addr_hit[262] & reg_we & !reg_error;
assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0];
- assign loc_alert_cause_0_we = addr_hit[259] & reg_we & !reg_error;
+ assign loc_alert_cause_0_we = addr_hit[263] & reg_we & !reg_error;
assign loc_alert_cause_0_wd = reg_wdata[0];
- assign loc_alert_cause_1_we = addr_hit[260] & reg_we & !reg_error;
+ assign loc_alert_cause_1_we = addr_hit[264] & reg_we & !reg_error;
assign loc_alert_cause_1_wd = reg_wdata[0];
- assign loc_alert_cause_2_we = addr_hit[261] & reg_we & !reg_error;
+ assign loc_alert_cause_2_we = addr_hit[265] & reg_we & !reg_error;
assign loc_alert_cause_2_wd = reg_wdata[0];
- assign loc_alert_cause_3_we = addr_hit[262] & reg_we & !reg_error;
+ assign loc_alert_cause_3_we = addr_hit[266] & reg_we & !reg_error;
assign loc_alert_cause_3_wd = reg_wdata[0];
- assign loc_alert_cause_4_we = addr_hit[263] & reg_we & !reg_error;
+ assign loc_alert_cause_4_we = addr_hit[267] & reg_we & !reg_error;
assign loc_alert_cause_4_wd = reg_wdata[0];
- assign loc_alert_cause_5_we = addr_hit[264] & reg_we & !reg_error;
+ assign loc_alert_cause_5_we = addr_hit[268] & reg_we & !reg_error;
assign loc_alert_cause_5_wd = reg_wdata[0];
- assign loc_alert_cause_6_we = addr_hit[265] & reg_we & !reg_error;
+ assign loc_alert_cause_6_we = addr_hit[269] & reg_we & !reg_error;
assign loc_alert_cause_6_wd = reg_wdata[0];
- assign classa_regwen_we = addr_hit[266] & reg_we & !reg_error;
+ assign classa_regwen_we = addr_hit[270] & reg_we & !reg_error;
assign classa_regwen_wd = reg_wdata[0];
- assign classa_ctrl_shadowed_re = addr_hit[267] & reg_re & !reg_error;
- assign classa_ctrl_shadowed_we = addr_hit[267] & reg_we & !reg_error;
+ assign classa_ctrl_shadowed_re = addr_hit[271] & reg_re & !reg_error;
+ assign classa_ctrl_shadowed_we = addr_hit[271] & reg_we & !reg_error;
assign classa_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -13760,49 +13916,49 @@
assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classa_clr_regwen_we = addr_hit[268] & reg_we & !reg_error;
+ assign classa_clr_regwen_we = addr_hit[272] & reg_we & !reg_error;
assign classa_clr_regwen_wd = reg_wdata[0];
- assign classa_clr_shadowed_re = addr_hit[269] & reg_re & !reg_error;
- assign classa_clr_shadowed_we = addr_hit[269] & reg_we & !reg_error;
+ assign classa_clr_shadowed_re = addr_hit[273] & reg_re & !reg_error;
+ assign classa_clr_shadowed_we = addr_hit[273] & reg_we & !reg_error;
assign classa_clr_shadowed_wd = reg_wdata[0];
- assign classa_accum_cnt_re = addr_hit[270] & reg_re & !reg_error;
- assign classa_accum_thresh_shadowed_re = addr_hit[271] & reg_re & !reg_error;
- assign classa_accum_thresh_shadowed_we = addr_hit[271] & reg_we & !reg_error;
+ assign classa_accum_cnt_re = addr_hit[274] & reg_re & !reg_error;
+ assign classa_accum_thresh_shadowed_re = addr_hit[275] & reg_re & !reg_error;
+ assign classa_accum_thresh_shadowed_we = addr_hit[275] & reg_we & !reg_error;
assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classa_timeout_cyc_shadowed_re = addr_hit[272] & reg_re & !reg_error;
- assign classa_timeout_cyc_shadowed_we = addr_hit[272] & reg_we & !reg_error;
+ assign classa_timeout_cyc_shadowed_re = addr_hit[276] & reg_re & !reg_error;
+ assign classa_timeout_cyc_shadowed_we = addr_hit[276] & reg_we & !reg_error;
assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_crashdump_trigger_shadowed_re = addr_hit[273] & reg_re & !reg_error;
- assign classa_crashdump_trigger_shadowed_we = addr_hit[273] & reg_we & !reg_error;
+ assign classa_crashdump_trigger_shadowed_re = addr_hit[277] & reg_re & !reg_error;
+ assign classa_crashdump_trigger_shadowed_we = addr_hit[277] & reg_we & !reg_error;
assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classa_phase0_cyc_shadowed_re = addr_hit[274] & reg_re & !reg_error;
- assign classa_phase0_cyc_shadowed_we = addr_hit[274] & reg_we & !reg_error;
+ assign classa_phase0_cyc_shadowed_re = addr_hit[278] & reg_re & !reg_error;
+ assign classa_phase0_cyc_shadowed_we = addr_hit[278] & reg_we & !reg_error;
assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_phase1_cyc_shadowed_re = addr_hit[275] & reg_re & !reg_error;
- assign classa_phase1_cyc_shadowed_we = addr_hit[275] & reg_we & !reg_error;
+ assign classa_phase1_cyc_shadowed_re = addr_hit[279] & reg_re & !reg_error;
+ assign classa_phase1_cyc_shadowed_we = addr_hit[279] & reg_we & !reg_error;
assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_phase2_cyc_shadowed_re = addr_hit[276] & reg_re & !reg_error;
- assign classa_phase2_cyc_shadowed_we = addr_hit[276] & reg_we & !reg_error;
+ assign classa_phase2_cyc_shadowed_re = addr_hit[280] & reg_re & !reg_error;
+ assign classa_phase2_cyc_shadowed_we = addr_hit[280] & reg_we & !reg_error;
assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_phase3_cyc_shadowed_re = addr_hit[277] & reg_re & !reg_error;
- assign classa_phase3_cyc_shadowed_we = addr_hit[277] & reg_we & !reg_error;
+ assign classa_phase3_cyc_shadowed_re = addr_hit[281] & reg_re & !reg_error;
+ assign classa_phase3_cyc_shadowed_we = addr_hit[281] & reg_we & !reg_error;
assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classa_esc_cnt_re = addr_hit[278] & reg_re & !reg_error;
- assign classa_state_re = addr_hit[279] & reg_re & !reg_error;
- assign classb_regwen_we = addr_hit[280] & reg_we & !reg_error;
+ assign classa_esc_cnt_re = addr_hit[282] & reg_re & !reg_error;
+ assign classa_state_re = addr_hit[283] & reg_re & !reg_error;
+ assign classb_regwen_we = addr_hit[284] & reg_we & !reg_error;
assign classb_regwen_wd = reg_wdata[0];
- assign classb_ctrl_shadowed_re = addr_hit[281] & reg_re & !reg_error;
- assign classb_ctrl_shadowed_we = addr_hit[281] & reg_we & !reg_error;
+ assign classb_ctrl_shadowed_re = addr_hit[285] & reg_re & !reg_error;
+ assign classb_ctrl_shadowed_we = addr_hit[285] & reg_we & !reg_error;
assign classb_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -13823,49 +13979,49 @@
assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classb_clr_regwen_we = addr_hit[282] & reg_we & !reg_error;
+ assign classb_clr_regwen_we = addr_hit[286] & reg_we & !reg_error;
assign classb_clr_regwen_wd = reg_wdata[0];
- assign classb_clr_shadowed_re = addr_hit[283] & reg_re & !reg_error;
- assign classb_clr_shadowed_we = addr_hit[283] & reg_we & !reg_error;
+ assign classb_clr_shadowed_re = addr_hit[287] & reg_re & !reg_error;
+ assign classb_clr_shadowed_we = addr_hit[287] & reg_we & !reg_error;
assign classb_clr_shadowed_wd = reg_wdata[0];
- assign classb_accum_cnt_re = addr_hit[284] & reg_re & !reg_error;
- assign classb_accum_thresh_shadowed_re = addr_hit[285] & reg_re & !reg_error;
- assign classb_accum_thresh_shadowed_we = addr_hit[285] & reg_we & !reg_error;
+ assign classb_accum_cnt_re = addr_hit[288] & reg_re & !reg_error;
+ assign classb_accum_thresh_shadowed_re = addr_hit[289] & reg_re & !reg_error;
+ assign classb_accum_thresh_shadowed_we = addr_hit[289] & reg_we & !reg_error;
assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classb_timeout_cyc_shadowed_re = addr_hit[286] & reg_re & !reg_error;
- assign classb_timeout_cyc_shadowed_we = addr_hit[286] & reg_we & !reg_error;
+ assign classb_timeout_cyc_shadowed_re = addr_hit[290] & reg_re & !reg_error;
+ assign classb_timeout_cyc_shadowed_we = addr_hit[290] & reg_we & !reg_error;
assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_crashdump_trigger_shadowed_re = addr_hit[287] & reg_re & !reg_error;
- assign classb_crashdump_trigger_shadowed_we = addr_hit[287] & reg_we & !reg_error;
+ assign classb_crashdump_trigger_shadowed_re = addr_hit[291] & reg_re & !reg_error;
+ assign classb_crashdump_trigger_shadowed_we = addr_hit[291] & reg_we & !reg_error;
assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classb_phase0_cyc_shadowed_re = addr_hit[288] & reg_re & !reg_error;
- assign classb_phase0_cyc_shadowed_we = addr_hit[288] & reg_we & !reg_error;
+ assign classb_phase0_cyc_shadowed_re = addr_hit[292] & reg_re & !reg_error;
+ assign classb_phase0_cyc_shadowed_we = addr_hit[292] & reg_we & !reg_error;
assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_phase1_cyc_shadowed_re = addr_hit[289] & reg_re & !reg_error;
- assign classb_phase1_cyc_shadowed_we = addr_hit[289] & reg_we & !reg_error;
+ assign classb_phase1_cyc_shadowed_re = addr_hit[293] & reg_re & !reg_error;
+ assign classb_phase1_cyc_shadowed_we = addr_hit[293] & reg_we & !reg_error;
assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_phase2_cyc_shadowed_re = addr_hit[290] & reg_re & !reg_error;
- assign classb_phase2_cyc_shadowed_we = addr_hit[290] & reg_we & !reg_error;
+ assign classb_phase2_cyc_shadowed_re = addr_hit[294] & reg_re & !reg_error;
+ assign classb_phase2_cyc_shadowed_we = addr_hit[294] & reg_we & !reg_error;
assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_phase3_cyc_shadowed_re = addr_hit[291] & reg_re & !reg_error;
- assign classb_phase3_cyc_shadowed_we = addr_hit[291] & reg_we & !reg_error;
+ assign classb_phase3_cyc_shadowed_re = addr_hit[295] & reg_re & !reg_error;
+ assign classb_phase3_cyc_shadowed_we = addr_hit[295] & reg_we & !reg_error;
assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classb_esc_cnt_re = addr_hit[292] & reg_re & !reg_error;
- assign classb_state_re = addr_hit[293] & reg_re & !reg_error;
- assign classc_regwen_we = addr_hit[294] & reg_we & !reg_error;
+ assign classb_esc_cnt_re = addr_hit[296] & reg_re & !reg_error;
+ assign classb_state_re = addr_hit[297] & reg_re & !reg_error;
+ assign classc_regwen_we = addr_hit[298] & reg_we & !reg_error;
assign classc_regwen_wd = reg_wdata[0];
- assign classc_ctrl_shadowed_re = addr_hit[295] & reg_re & !reg_error;
- assign classc_ctrl_shadowed_we = addr_hit[295] & reg_we & !reg_error;
+ assign classc_ctrl_shadowed_re = addr_hit[299] & reg_re & !reg_error;
+ assign classc_ctrl_shadowed_we = addr_hit[299] & reg_we & !reg_error;
assign classc_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -13886,49 +14042,49 @@
assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classc_clr_regwen_we = addr_hit[296] & reg_we & !reg_error;
+ assign classc_clr_regwen_we = addr_hit[300] & reg_we & !reg_error;
assign classc_clr_regwen_wd = reg_wdata[0];
- assign classc_clr_shadowed_re = addr_hit[297] & reg_re & !reg_error;
- assign classc_clr_shadowed_we = addr_hit[297] & reg_we & !reg_error;
+ assign classc_clr_shadowed_re = addr_hit[301] & reg_re & !reg_error;
+ assign classc_clr_shadowed_we = addr_hit[301] & reg_we & !reg_error;
assign classc_clr_shadowed_wd = reg_wdata[0];
- assign classc_accum_cnt_re = addr_hit[298] & reg_re & !reg_error;
- assign classc_accum_thresh_shadowed_re = addr_hit[299] & reg_re & !reg_error;
- assign classc_accum_thresh_shadowed_we = addr_hit[299] & reg_we & !reg_error;
+ assign classc_accum_cnt_re = addr_hit[302] & reg_re & !reg_error;
+ assign classc_accum_thresh_shadowed_re = addr_hit[303] & reg_re & !reg_error;
+ assign classc_accum_thresh_shadowed_we = addr_hit[303] & reg_we & !reg_error;
assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classc_timeout_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error;
- assign classc_timeout_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error;
+ assign classc_timeout_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error;
+ assign classc_timeout_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error;
assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_crashdump_trigger_shadowed_re = addr_hit[301] & reg_re & !reg_error;
- assign classc_crashdump_trigger_shadowed_we = addr_hit[301] & reg_we & !reg_error;
+ assign classc_crashdump_trigger_shadowed_re = addr_hit[305] & reg_re & !reg_error;
+ assign classc_crashdump_trigger_shadowed_we = addr_hit[305] & reg_we & !reg_error;
assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classc_phase0_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error;
- assign classc_phase0_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error;
+ assign classc_phase0_cyc_shadowed_re = addr_hit[306] & reg_re & !reg_error;
+ assign classc_phase0_cyc_shadowed_we = addr_hit[306] & reg_we & !reg_error;
assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_phase1_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error;
- assign classc_phase1_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error;
+ assign classc_phase1_cyc_shadowed_re = addr_hit[307] & reg_re & !reg_error;
+ assign classc_phase1_cyc_shadowed_we = addr_hit[307] & reg_we & !reg_error;
assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_phase2_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error;
- assign classc_phase2_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error;
+ assign classc_phase2_cyc_shadowed_re = addr_hit[308] & reg_re & !reg_error;
+ assign classc_phase2_cyc_shadowed_we = addr_hit[308] & reg_we & !reg_error;
assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_phase3_cyc_shadowed_re = addr_hit[305] & reg_re & !reg_error;
- assign classc_phase3_cyc_shadowed_we = addr_hit[305] & reg_we & !reg_error;
+ assign classc_phase3_cyc_shadowed_re = addr_hit[309] & reg_re & !reg_error;
+ assign classc_phase3_cyc_shadowed_we = addr_hit[309] & reg_we & !reg_error;
assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classc_esc_cnt_re = addr_hit[306] & reg_re & !reg_error;
- assign classc_state_re = addr_hit[307] & reg_re & !reg_error;
- assign classd_regwen_we = addr_hit[308] & reg_we & !reg_error;
+ assign classc_esc_cnt_re = addr_hit[310] & reg_re & !reg_error;
+ assign classc_state_re = addr_hit[311] & reg_re & !reg_error;
+ assign classd_regwen_we = addr_hit[312] & reg_we & !reg_error;
assign classd_regwen_wd = reg_wdata[0];
- assign classd_ctrl_shadowed_re = addr_hit[309] & reg_re & !reg_error;
- assign classd_ctrl_shadowed_we = addr_hit[309] & reg_we & !reg_error;
+ assign classd_ctrl_shadowed_re = addr_hit[313] & reg_re & !reg_error;
+ assign classd_ctrl_shadowed_we = addr_hit[313] & reg_we & !reg_error;
assign classd_ctrl_shadowed_en_wd = reg_wdata[0];
@@ -13949,44 +14105,44 @@
assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
- assign classd_clr_regwen_we = addr_hit[310] & reg_we & !reg_error;
+ assign classd_clr_regwen_we = addr_hit[314] & reg_we & !reg_error;
assign classd_clr_regwen_wd = reg_wdata[0];
- assign classd_clr_shadowed_re = addr_hit[311] & reg_re & !reg_error;
- assign classd_clr_shadowed_we = addr_hit[311] & reg_we & !reg_error;
+ assign classd_clr_shadowed_re = addr_hit[315] & reg_re & !reg_error;
+ assign classd_clr_shadowed_we = addr_hit[315] & reg_we & !reg_error;
assign classd_clr_shadowed_wd = reg_wdata[0];
- assign classd_accum_cnt_re = addr_hit[312] & reg_re & !reg_error;
- assign classd_accum_thresh_shadowed_re = addr_hit[313] & reg_re & !reg_error;
- assign classd_accum_thresh_shadowed_we = addr_hit[313] & reg_we & !reg_error;
+ assign classd_accum_cnt_re = addr_hit[316] & reg_re & !reg_error;
+ assign classd_accum_thresh_shadowed_re = addr_hit[317] & reg_re & !reg_error;
+ assign classd_accum_thresh_shadowed_we = addr_hit[317] & reg_we & !reg_error;
assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0];
- assign classd_timeout_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error;
- assign classd_timeout_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error;
+ assign classd_timeout_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error;
+ assign classd_timeout_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error;
assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_crashdump_trigger_shadowed_re = addr_hit[315] & reg_re & !reg_error;
- assign classd_crashdump_trigger_shadowed_we = addr_hit[315] & reg_we & !reg_error;
+ assign classd_crashdump_trigger_shadowed_re = addr_hit[319] & reg_re & !reg_error;
+ assign classd_crashdump_trigger_shadowed_we = addr_hit[319] & reg_we & !reg_error;
assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
- assign classd_phase0_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error;
- assign classd_phase0_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error;
+ assign classd_phase0_cyc_shadowed_re = addr_hit[320] & reg_re & !reg_error;
+ assign classd_phase0_cyc_shadowed_we = addr_hit[320] & reg_we & !reg_error;
assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_phase1_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error;
- assign classd_phase1_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error;
+ assign classd_phase1_cyc_shadowed_re = addr_hit[321] & reg_re & !reg_error;
+ assign classd_phase1_cyc_shadowed_we = addr_hit[321] & reg_we & !reg_error;
assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_phase2_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error;
- assign classd_phase2_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error;
+ assign classd_phase2_cyc_shadowed_re = addr_hit[322] & reg_re & !reg_error;
+ assign classd_phase2_cyc_shadowed_we = addr_hit[322] & reg_we & !reg_error;
assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_phase3_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error;
- assign classd_phase3_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error;
+ assign classd_phase3_cyc_shadowed_re = addr_hit[323] & reg_re & !reg_error;
+ assign classd_phase3_cyc_shadowed_we = addr_hit[323] & reg_we & !reg_error;
assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0];
- assign classd_esc_cnt_re = addr_hit[320] & reg_re & !reg_error;
- assign classd_state_re = addr_hit[321] & reg_re & !reg_error;
+ assign classd_esc_cnt_re = addr_hit[324] & reg_re & !reg_error;
+ assign classd_state_re = addr_hit[325] & reg_re & !reg_error;
// Read data return
always_comb begin
@@ -14258,818 +14414,834 @@
end
addr_hit[64]: begin
- reg_rdata_next[0] = alert_en_shadowed_0_qs;
+ reg_rdata_next[0] = alert_regwen_58_qs;
end
addr_hit[65]: begin
- reg_rdata_next[0] = alert_en_shadowed_1_qs;
+ reg_rdata_next[0] = alert_en_shadowed_0_qs;
end
addr_hit[66]: begin
- reg_rdata_next[0] = alert_en_shadowed_2_qs;
+ reg_rdata_next[0] = alert_en_shadowed_1_qs;
end
addr_hit[67]: begin
- reg_rdata_next[0] = alert_en_shadowed_3_qs;
+ reg_rdata_next[0] = alert_en_shadowed_2_qs;
end
addr_hit[68]: begin
- reg_rdata_next[0] = alert_en_shadowed_4_qs;
+ reg_rdata_next[0] = alert_en_shadowed_3_qs;
end
addr_hit[69]: begin
- reg_rdata_next[0] = alert_en_shadowed_5_qs;
+ reg_rdata_next[0] = alert_en_shadowed_4_qs;
end
addr_hit[70]: begin
- reg_rdata_next[0] = alert_en_shadowed_6_qs;
+ reg_rdata_next[0] = alert_en_shadowed_5_qs;
end
addr_hit[71]: begin
- reg_rdata_next[0] = alert_en_shadowed_7_qs;
+ reg_rdata_next[0] = alert_en_shadowed_6_qs;
end
addr_hit[72]: begin
- reg_rdata_next[0] = alert_en_shadowed_8_qs;
+ reg_rdata_next[0] = alert_en_shadowed_7_qs;
end
addr_hit[73]: begin
- reg_rdata_next[0] = alert_en_shadowed_9_qs;
+ reg_rdata_next[0] = alert_en_shadowed_8_qs;
end
addr_hit[74]: begin
- reg_rdata_next[0] = alert_en_shadowed_10_qs;
+ reg_rdata_next[0] = alert_en_shadowed_9_qs;
end
addr_hit[75]: begin
- reg_rdata_next[0] = alert_en_shadowed_11_qs;
+ reg_rdata_next[0] = alert_en_shadowed_10_qs;
end
addr_hit[76]: begin
- reg_rdata_next[0] = alert_en_shadowed_12_qs;
+ reg_rdata_next[0] = alert_en_shadowed_11_qs;
end
addr_hit[77]: begin
- reg_rdata_next[0] = alert_en_shadowed_13_qs;
+ reg_rdata_next[0] = alert_en_shadowed_12_qs;
end
addr_hit[78]: begin
- reg_rdata_next[0] = alert_en_shadowed_14_qs;
+ reg_rdata_next[0] = alert_en_shadowed_13_qs;
end
addr_hit[79]: begin
- reg_rdata_next[0] = alert_en_shadowed_15_qs;
+ reg_rdata_next[0] = alert_en_shadowed_14_qs;
end
addr_hit[80]: begin
- reg_rdata_next[0] = alert_en_shadowed_16_qs;
+ reg_rdata_next[0] = alert_en_shadowed_15_qs;
end
addr_hit[81]: begin
- reg_rdata_next[0] = alert_en_shadowed_17_qs;
+ reg_rdata_next[0] = alert_en_shadowed_16_qs;
end
addr_hit[82]: begin
- reg_rdata_next[0] = alert_en_shadowed_18_qs;
+ reg_rdata_next[0] = alert_en_shadowed_17_qs;
end
addr_hit[83]: begin
- reg_rdata_next[0] = alert_en_shadowed_19_qs;
+ reg_rdata_next[0] = alert_en_shadowed_18_qs;
end
addr_hit[84]: begin
- reg_rdata_next[0] = alert_en_shadowed_20_qs;
+ reg_rdata_next[0] = alert_en_shadowed_19_qs;
end
addr_hit[85]: begin
- reg_rdata_next[0] = alert_en_shadowed_21_qs;
+ reg_rdata_next[0] = alert_en_shadowed_20_qs;
end
addr_hit[86]: begin
- reg_rdata_next[0] = alert_en_shadowed_22_qs;
+ reg_rdata_next[0] = alert_en_shadowed_21_qs;
end
addr_hit[87]: begin
- reg_rdata_next[0] = alert_en_shadowed_23_qs;
+ reg_rdata_next[0] = alert_en_shadowed_22_qs;
end
addr_hit[88]: begin
- reg_rdata_next[0] = alert_en_shadowed_24_qs;
+ reg_rdata_next[0] = alert_en_shadowed_23_qs;
end
addr_hit[89]: begin
- reg_rdata_next[0] = alert_en_shadowed_25_qs;
+ reg_rdata_next[0] = alert_en_shadowed_24_qs;
end
addr_hit[90]: begin
- reg_rdata_next[0] = alert_en_shadowed_26_qs;
+ reg_rdata_next[0] = alert_en_shadowed_25_qs;
end
addr_hit[91]: begin
- reg_rdata_next[0] = alert_en_shadowed_27_qs;
+ reg_rdata_next[0] = alert_en_shadowed_26_qs;
end
addr_hit[92]: begin
- reg_rdata_next[0] = alert_en_shadowed_28_qs;
+ reg_rdata_next[0] = alert_en_shadowed_27_qs;
end
addr_hit[93]: begin
- reg_rdata_next[0] = alert_en_shadowed_29_qs;
+ reg_rdata_next[0] = alert_en_shadowed_28_qs;
end
addr_hit[94]: begin
- reg_rdata_next[0] = alert_en_shadowed_30_qs;
+ reg_rdata_next[0] = alert_en_shadowed_29_qs;
end
addr_hit[95]: begin
- reg_rdata_next[0] = alert_en_shadowed_31_qs;
+ reg_rdata_next[0] = alert_en_shadowed_30_qs;
end
addr_hit[96]: begin
- reg_rdata_next[0] = alert_en_shadowed_32_qs;
+ reg_rdata_next[0] = alert_en_shadowed_31_qs;
end
addr_hit[97]: begin
- reg_rdata_next[0] = alert_en_shadowed_33_qs;
+ reg_rdata_next[0] = alert_en_shadowed_32_qs;
end
addr_hit[98]: begin
- reg_rdata_next[0] = alert_en_shadowed_34_qs;
+ reg_rdata_next[0] = alert_en_shadowed_33_qs;
end
addr_hit[99]: begin
- reg_rdata_next[0] = alert_en_shadowed_35_qs;
+ reg_rdata_next[0] = alert_en_shadowed_34_qs;
end
addr_hit[100]: begin
- reg_rdata_next[0] = alert_en_shadowed_36_qs;
+ reg_rdata_next[0] = alert_en_shadowed_35_qs;
end
addr_hit[101]: begin
- reg_rdata_next[0] = alert_en_shadowed_37_qs;
+ reg_rdata_next[0] = alert_en_shadowed_36_qs;
end
addr_hit[102]: begin
- reg_rdata_next[0] = alert_en_shadowed_38_qs;
+ reg_rdata_next[0] = alert_en_shadowed_37_qs;
end
addr_hit[103]: begin
- reg_rdata_next[0] = alert_en_shadowed_39_qs;
+ reg_rdata_next[0] = alert_en_shadowed_38_qs;
end
addr_hit[104]: begin
- reg_rdata_next[0] = alert_en_shadowed_40_qs;
+ reg_rdata_next[0] = alert_en_shadowed_39_qs;
end
addr_hit[105]: begin
- reg_rdata_next[0] = alert_en_shadowed_41_qs;
+ reg_rdata_next[0] = alert_en_shadowed_40_qs;
end
addr_hit[106]: begin
- reg_rdata_next[0] = alert_en_shadowed_42_qs;
+ reg_rdata_next[0] = alert_en_shadowed_41_qs;
end
addr_hit[107]: begin
- reg_rdata_next[0] = alert_en_shadowed_43_qs;
+ reg_rdata_next[0] = alert_en_shadowed_42_qs;
end
addr_hit[108]: begin
- reg_rdata_next[0] = alert_en_shadowed_44_qs;
+ reg_rdata_next[0] = alert_en_shadowed_43_qs;
end
addr_hit[109]: begin
- reg_rdata_next[0] = alert_en_shadowed_45_qs;
+ reg_rdata_next[0] = alert_en_shadowed_44_qs;
end
addr_hit[110]: begin
- reg_rdata_next[0] = alert_en_shadowed_46_qs;
+ reg_rdata_next[0] = alert_en_shadowed_45_qs;
end
addr_hit[111]: begin
- reg_rdata_next[0] = alert_en_shadowed_47_qs;
+ reg_rdata_next[0] = alert_en_shadowed_46_qs;
end
addr_hit[112]: begin
- reg_rdata_next[0] = alert_en_shadowed_48_qs;
+ reg_rdata_next[0] = alert_en_shadowed_47_qs;
end
addr_hit[113]: begin
- reg_rdata_next[0] = alert_en_shadowed_49_qs;
+ reg_rdata_next[0] = alert_en_shadowed_48_qs;
end
addr_hit[114]: begin
- reg_rdata_next[0] = alert_en_shadowed_50_qs;
+ reg_rdata_next[0] = alert_en_shadowed_49_qs;
end
addr_hit[115]: begin
- reg_rdata_next[0] = alert_en_shadowed_51_qs;
+ reg_rdata_next[0] = alert_en_shadowed_50_qs;
end
addr_hit[116]: begin
- reg_rdata_next[0] = alert_en_shadowed_52_qs;
+ reg_rdata_next[0] = alert_en_shadowed_51_qs;
end
addr_hit[117]: begin
- reg_rdata_next[0] = alert_en_shadowed_53_qs;
+ reg_rdata_next[0] = alert_en_shadowed_52_qs;
end
addr_hit[118]: begin
- reg_rdata_next[0] = alert_en_shadowed_54_qs;
+ reg_rdata_next[0] = alert_en_shadowed_53_qs;
end
addr_hit[119]: begin
- reg_rdata_next[0] = alert_en_shadowed_55_qs;
+ reg_rdata_next[0] = alert_en_shadowed_54_qs;
end
addr_hit[120]: begin
- reg_rdata_next[0] = alert_en_shadowed_56_qs;
+ reg_rdata_next[0] = alert_en_shadowed_55_qs;
end
addr_hit[121]: begin
- reg_rdata_next[0] = alert_en_shadowed_57_qs;
+ reg_rdata_next[0] = alert_en_shadowed_56_qs;
end
addr_hit[122]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
+ reg_rdata_next[0] = alert_en_shadowed_57_qs;
end
addr_hit[123]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
+ reg_rdata_next[0] = alert_en_shadowed_58_qs;
end
addr_hit[124]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
end
addr_hit[125]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
end
addr_hit[126]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
end
addr_hit[127]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
end
addr_hit[128]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
end
addr_hit[129]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
end
addr_hit[130]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
end
addr_hit[131]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
end
addr_hit[132]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
end
addr_hit[133]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
end
addr_hit[134]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
end
addr_hit[135]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
end
addr_hit[136]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
end
addr_hit[137]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
end
addr_hit[138]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
end
addr_hit[139]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
end
addr_hit[140]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
end
addr_hit[141]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
end
addr_hit[142]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
end
addr_hit[143]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
end
addr_hit[144]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
end
addr_hit[145]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
end
addr_hit[146]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
end
addr_hit[147]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
end
addr_hit[148]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
end
addr_hit[149]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
end
addr_hit[150]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
end
addr_hit[151]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
end
addr_hit[152]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
end
addr_hit[153]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
end
addr_hit[154]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
end
addr_hit[155]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
end
addr_hit[156]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
end
addr_hit[157]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
end
addr_hit[158]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
end
addr_hit[159]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
end
addr_hit[160]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
end
addr_hit[161]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
end
addr_hit[162]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
end
addr_hit[163]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
end
addr_hit[164]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
end
addr_hit[165]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
end
addr_hit[166]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
end
addr_hit[167]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
end
addr_hit[168]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
end
addr_hit[169]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
end
addr_hit[170]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
end
addr_hit[171]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
end
addr_hit[172]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
end
addr_hit[173]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
end
addr_hit[174]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
end
addr_hit[175]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
end
addr_hit[176]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
end
addr_hit[177]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
end
addr_hit[178]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
end
addr_hit[179]: begin
- reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
end
addr_hit[180]: begin
- reg_rdata_next[0] = alert_cause_0_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
end
addr_hit[181]: begin
- reg_rdata_next[0] = alert_cause_1_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
end
addr_hit[182]: begin
- reg_rdata_next[0] = alert_cause_2_qs;
+ reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
end
addr_hit[183]: begin
- reg_rdata_next[0] = alert_cause_3_qs;
+ reg_rdata_next[0] = alert_cause_0_qs;
end
addr_hit[184]: begin
- reg_rdata_next[0] = alert_cause_4_qs;
+ reg_rdata_next[0] = alert_cause_1_qs;
end
addr_hit[185]: begin
- reg_rdata_next[0] = alert_cause_5_qs;
+ reg_rdata_next[0] = alert_cause_2_qs;
end
addr_hit[186]: begin
- reg_rdata_next[0] = alert_cause_6_qs;
+ reg_rdata_next[0] = alert_cause_3_qs;
end
addr_hit[187]: begin
- reg_rdata_next[0] = alert_cause_7_qs;
+ reg_rdata_next[0] = alert_cause_4_qs;
end
addr_hit[188]: begin
- reg_rdata_next[0] = alert_cause_8_qs;
+ reg_rdata_next[0] = alert_cause_5_qs;
end
addr_hit[189]: begin
- reg_rdata_next[0] = alert_cause_9_qs;
+ reg_rdata_next[0] = alert_cause_6_qs;
end
addr_hit[190]: begin
- reg_rdata_next[0] = alert_cause_10_qs;
+ reg_rdata_next[0] = alert_cause_7_qs;
end
addr_hit[191]: begin
- reg_rdata_next[0] = alert_cause_11_qs;
+ reg_rdata_next[0] = alert_cause_8_qs;
end
addr_hit[192]: begin
- reg_rdata_next[0] = alert_cause_12_qs;
+ reg_rdata_next[0] = alert_cause_9_qs;
end
addr_hit[193]: begin
- reg_rdata_next[0] = alert_cause_13_qs;
+ reg_rdata_next[0] = alert_cause_10_qs;
end
addr_hit[194]: begin
- reg_rdata_next[0] = alert_cause_14_qs;
+ reg_rdata_next[0] = alert_cause_11_qs;
end
addr_hit[195]: begin
- reg_rdata_next[0] = alert_cause_15_qs;
+ reg_rdata_next[0] = alert_cause_12_qs;
end
addr_hit[196]: begin
- reg_rdata_next[0] = alert_cause_16_qs;
+ reg_rdata_next[0] = alert_cause_13_qs;
end
addr_hit[197]: begin
- reg_rdata_next[0] = alert_cause_17_qs;
+ reg_rdata_next[0] = alert_cause_14_qs;
end
addr_hit[198]: begin
- reg_rdata_next[0] = alert_cause_18_qs;
+ reg_rdata_next[0] = alert_cause_15_qs;
end
addr_hit[199]: begin
- reg_rdata_next[0] = alert_cause_19_qs;
+ reg_rdata_next[0] = alert_cause_16_qs;
end
addr_hit[200]: begin
- reg_rdata_next[0] = alert_cause_20_qs;
+ reg_rdata_next[0] = alert_cause_17_qs;
end
addr_hit[201]: begin
- reg_rdata_next[0] = alert_cause_21_qs;
+ reg_rdata_next[0] = alert_cause_18_qs;
end
addr_hit[202]: begin
- reg_rdata_next[0] = alert_cause_22_qs;
+ reg_rdata_next[0] = alert_cause_19_qs;
end
addr_hit[203]: begin
- reg_rdata_next[0] = alert_cause_23_qs;
+ reg_rdata_next[0] = alert_cause_20_qs;
end
addr_hit[204]: begin
- reg_rdata_next[0] = alert_cause_24_qs;
+ reg_rdata_next[0] = alert_cause_21_qs;
end
addr_hit[205]: begin
- reg_rdata_next[0] = alert_cause_25_qs;
+ reg_rdata_next[0] = alert_cause_22_qs;
end
addr_hit[206]: begin
- reg_rdata_next[0] = alert_cause_26_qs;
+ reg_rdata_next[0] = alert_cause_23_qs;
end
addr_hit[207]: begin
- reg_rdata_next[0] = alert_cause_27_qs;
+ reg_rdata_next[0] = alert_cause_24_qs;
end
addr_hit[208]: begin
- reg_rdata_next[0] = alert_cause_28_qs;
+ reg_rdata_next[0] = alert_cause_25_qs;
end
addr_hit[209]: begin
- reg_rdata_next[0] = alert_cause_29_qs;
+ reg_rdata_next[0] = alert_cause_26_qs;
end
addr_hit[210]: begin
- reg_rdata_next[0] = alert_cause_30_qs;
+ reg_rdata_next[0] = alert_cause_27_qs;
end
addr_hit[211]: begin
- reg_rdata_next[0] = alert_cause_31_qs;
+ reg_rdata_next[0] = alert_cause_28_qs;
end
addr_hit[212]: begin
- reg_rdata_next[0] = alert_cause_32_qs;
+ reg_rdata_next[0] = alert_cause_29_qs;
end
addr_hit[213]: begin
- reg_rdata_next[0] = alert_cause_33_qs;
+ reg_rdata_next[0] = alert_cause_30_qs;
end
addr_hit[214]: begin
- reg_rdata_next[0] = alert_cause_34_qs;
+ reg_rdata_next[0] = alert_cause_31_qs;
end
addr_hit[215]: begin
- reg_rdata_next[0] = alert_cause_35_qs;
+ reg_rdata_next[0] = alert_cause_32_qs;
end
addr_hit[216]: begin
- reg_rdata_next[0] = alert_cause_36_qs;
+ reg_rdata_next[0] = alert_cause_33_qs;
end
addr_hit[217]: begin
- reg_rdata_next[0] = alert_cause_37_qs;
+ reg_rdata_next[0] = alert_cause_34_qs;
end
addr_hit[218]: begin
- reg_rdata_next[0] = alert_cause_38_qs;
+ reg_rdata_next[0] = alert_cause_35_qs;
end
addr_hit[219]: begin
- reg_rdata_next[0] = alert_cause_39_qs;
+ reg_rdata_next[0] = alert_cause_36_qs;
end
addr_hit[220]: begin
- reg_rdata_next[0] = alert_cause_40_qs;
+ reg_rdata_next[0] = alert_cause_37_qs;
end
addr_hit[221]: begin
- reg_rdata_next[0] = alert_cause_41_qs;
+ reg_rdata_next[0] = alert_cause_38_qs;
end
addr_hit[222]: begin
- reg_rdata_next[0] = alert_cause_42_qs;
+ reg_rdata_next[0] = alert_cause_39_qs;
end
addr_hit[223]: begin
- reg_rdata_next[0] = alert_cause_43_qs;
+ reg_rdata_next[0] = alert_cause_40_qs;
end
addr_hit[224]: begin
- reg_rdata_next[0] = alert_cause_44_qs;
+ reg_rdata_next[0] = alert_cause_41_qs;
end
addr_hit[225]: begin
- reg_rdata_next[0] = alert_cause_45_qs;
+ reg_rdata_next[0] = alert_cause_42_qs;
end
addr_hit[226]: begin
- reg_rdata_next[0] = alert_cause_46_qs;
+ reg_rdata_next[0] = alert_cause_43_qs;
end
addr_hit[227]: begin
- reg_rdata_next[0] = alert_cause_47_qs;
+ reg_rdata_next[0] = alert_cause_44_qs;
end
addr_hit[228]: begin
- reg_rdata_next[0] = alert_cause_48_qs;
+ reg_rdata_next[0] = alert_cause_45_qs;
end
addr_hit[229]: begin
- reg_rdata_next[0] = alert_cause_49_qs;
+ reg_rdata_next[0] = alert_cause_46_qs;
end
addr_hit[230]: begin
- reg_rdata_next[0] = alert_cause_50_qs;
+ reg_rdata_next[0] = alert_cause_47_qs;
end
addr_hit[231]: begin
- reg_rdata_next[0] = alert_cause_51_qs;
+ reg_rdata_next[0] = alert_cause_48_qs;
end
addr_hit[232]: begin
- reg_rdata_next[0] = alert_cause_52_qs;
+ reg_rdata_next[0] = alert_cause_49_qs;
end
addr_hit[233]: begin
- reg_rdata_next[0] = alert_cause_53_qs;
+ reg_rdata_next[0] = alert_cause_50_qs;
end
addr_hit[234]: begin
- reg_rdata_next[0] = alert_cause_54_qs;
+ reg_rdata_next[0] = alert_cause_51_qs;
end
addr_hit[235]: begin
- reg_rdata_next[0] = alert_cause_55_qs;
+ reg_rdata_next[0] = alert_cause_52_qs;
end
addr_hit[236]: begin
- reg_rdata_next[0] = alert_cause_56_qs;
+ reg_rdata_next[0] = alert_cause_53_qs;
end
addr_hit[237]: begin
- reg_rdata_next[0] = alert_cause_57_qs;
+ reg_rdata_next[0] = alert_cause_54_qs;
end
addr_hit[238]: begin
- reg_rdata_next[0] = loc_alert_regwen_0_qs;
+ reg_rdata_next[0] = alert_cause_55_qs;
end
addr_hit[239]: begin
- reg_rdata_next[0] = loc_alert_regwen_1_qs;
+ reg_rdata_next[0] = alert_cause_56_qs;
end
addr_hit[240]: begin
- reg_rdata_next[0] = loc_alert_regwen_2_qs;
+ reg_rdata_next[0] = alert_cause_57_qs;
end
addr_hit[241]: begin
- reg_rdata_next[0] = loc_alert_regwen_3_qs;
+ reg_rdata_next[0] = alert_cause_58_qs;
end
addr_hit[242]: begin
- reg_rdata_next[0] = loc_alert_regwen_4_qs;
+ reg_rdata_next[0] = loc_alert_regwen_0_qs;
end
addr_hit[243]: begin
- reg_rdata_next[0] = loc_alert_regwen_5_qs;
+ reg_rdata_next[0] = loc_alert_regwen_1_qs;
end
addr_hit[244]: begin
- reg_rdata_next[0] = loc_alert_regwen_6_qs;
+ reg_rdata_next[0] = loc_alert_regwen_2_qs;
end
addr_hit[245]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
+ reg_rdata_next[0] = loc_alert_regwen_3_qs;
end
addr_hit[246]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
+ reg_rdata_next[0] = loc_alert_regwen_4_qs;
end
addr_hit[247]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
+ reg_rdata_next[0] = loc_alert_regwen_5_qs;
end
addr_hit[248]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
+ reg_rdata_next[0] = loc_alert_regwen_6_qs;
end
addr_hit[249]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
end
addr_hit[250]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
end
addr_hit[251]: begin
- reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
end
addr_hit[252]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
end
addr_hit[253]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
end
addr_hit[254]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
end
addr_hit[255]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
+ reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
end
addr_hit[256]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
end
addr_hit[257]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
end
addr_hit[258]: begin
- reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
end
addr_hit[259]: begin
- reg_rdata_next[0] = loc_alert_cause_0_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
end
addr_hit[260]: begin
- reg_rdata_next[0] = loc_alert_cause_1_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
end
addr_hit[261]: begin
- reg_rdata_next[0] = loc_alert_cause_2_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
end
addr_hit[262]: begin
- reg_rdata_next[0] = loc_alert_cause_3_qs;
+ reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
end
addr_hit[263]: begin
- reg_rdata_next[0] = loc_alert_cause_4_qs;
+ reg_rdata_next[0] = loc_alert_cause_0_qs;
end
addr_hit[264]: begin
- reg_rdata_next[0] = loc_alert_cause_5_qs;
+ reg_rdata_next[0] = loc_alert_cause_1_qs;
end
addr_hit[265]: begin
- reg_rdata_next[0] = loc_alert_cause_6_qs;
+ reg_rdata_next[0] = loc_alert_cause_2_qs;
end
addr_hit[266]: begin
- reg_rdata_next[0] = classa_regwen_qs;
+ reg_rdata_next[0] = loc_alert_cause_3_qs;
end
addr_hit[267]: begin
+ reg_rdata_next[0] = loc_alert_cause_4_qs;
+ end
+
+ addr_hit[268]: begin
+ reg_rdata_next[0] = loc_alert_cause_5_qs;
+ end
+
+ addr_hit[269]: begin
+ reg_rdata_next[0] = loc_alert_cause_6_qs;
+ end
+
+ addr_hit[270]: begin
+ reg_rdata_next[0] = classa_regwen_qs;
+ end
+
+ addr_hit[271]: begin
reg_rdata_next[0] = classa_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs;
@@ -15082,59 +15254,59 @@
reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs;
end
- addr_hit[268]: begin
+ addr_hit[272]: begin
reg_rdata_next[0] = classa_clr_regwen_qs;
end
- addr_hit[269]: begin
+ addr_hit[273]: begin
reg_rdata_next[0] = classa_clr_shadowed_qs;
end
- addr_hit[270]: begin
+ addr_hit[274]: begin
reg_rdata_next[15:0] = classa_accum_cnt_qs;
end
- addr_hit[271]: begin
+ addr_hit[275]: begin
reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs;
end
- addr_hit[272]: begin
+ addr_hit[276]: begin
reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs;
end
- addr_hit[273]: begin
+ addr_hit[277]: begin
reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs;
end
- addr_hit[274]: begin
+ addr_hit[278]: begin
reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs;
end
- addr_hit[275]: begin
+ addr_hit[279]: begin
reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs;
end
- addr_hit[276]: begin
+ addr_hit[280]: begin
reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs;
end
- addr_hit[277]: begin
+ addr_hit[281]: begin
reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs;
end
- addr_hit[278]: begin
+ addr_hit[282]: begin
reg_rdata_next[31:0] = classa_esc_cnt_qs;
end
- addr_hit[279]: begin
+ addr_hit[283]: begin
reg_rdata_next[2:0] = classa_state_qs;
end
- addr_hit[280]: begin
+ addr_hit[284]: begin
reg_rdata_next[0] = classb_regwen_qs;
end
- addr_hit[281]: begin
+ addr_hit[285]: begin
reg_rdata_next[0] = classb_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs;
@@ -15147,59 +15319,59 @@
reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs;
end
- addr_hit[282]: begin
+ addr_hit[286]: begin
reg_rdata_next[0] = classb_clr_regwen_qs;
end
- addr_hit[283]: begin
+ addr_hit[287]: begin
reg_rdata_next[0] = classb_clr_shadowed_qs;
end
- addr_hit[284]: begin
+ addr_hit[288]: begin
reg_rdata_next[15:0] = classb_accum_cnt_qs;
end
- addr_hit[285]: begin
+ addr_hit[289]: begin
reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs;
end
- addr_hit[286]: begin
+ addr_hit[290]: begin
reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs;
end
- addr_hit[287]: begin
+ addr_hit[291]: begin
reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs;
end
- addr_hit[288]: begin
+ addr_hit[292]: begin
reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs;
end
- addr_hit[289]: begin
+ addr_hit[293]: begin
reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs;
end
- addr_hit[290]: begin
+ addr_hit[294]: begin
reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs;
end
- addr_hit[291]: begin
+ addr_hit[295]: begin
reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs;
end
- addr_hit[292]: begin
+ addr_hit[296]: begin
reg_rdata_next[31:0] = classb_esc_cnt_qs;
end
- addr_hit[293]: begin
+ addr_hit[297]: begin
reg_rdata_next[2:0] = classb_state_qs;
end
- addr_hit[294]: begin
+ addr_hit[298]: begin
reg_rdata_next[0] = classc_regwen_qs;
end
- addr_hit[295]: begin
+ addr_hit[299]: begin
reg_rdata_next[0] = classc_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs;
@@ -15212,59 +15384,59 @@
reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs;
end
- addr_hit[296]: begin
+ addr_hit[300]: begin
reg_rdata_next[0] = classc_clr_regwen_qs;
end
- addr_hit[297]: begin
+ addr_hit[301]: begin
reg_rdata_next[0] = classc_clr_shadowed_qs;
end
- addr_hit[298]: begin
+ addr_hit[302]: begin
reg_rdata_next[15:0] = classc_accum_cnt_qs;
end
- addr_hit[299]: begin
+ addr_hit[303]: begin
reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs;
end
- addr_hit[300]: begin
+ addr_hit[304]: begin
reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs;
end
- addr_hit[301]: begin
+ addr_hit[305]: begin
reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs;
end
- addr_hit[302]: begin
+ addr_hit[306]: begin
reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs;
end
- addr_hit[303]: begin
+ addr_hit[307]: begin
reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs;
end
- addr_hit[304]: begin
+ addr_hit[308]: begin
reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs;
end
- addr_hit[305]: begin
+ addr_hit[309]: begin
reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs;
end
- addr_hit[306]: begin
+ addr_hit[310]: begin
reg_rdata_next[31:0] = classc_esc_cnt_qs;
end
- addr_hit[307]: begin
+ addr_hit[311]: begin
reg_rdata_next[2:0] = classc_state_qs;
end
- addr_hit[308]: begin
+ addr_hit[312]: begin
reg_rdata_next[0] = classd_regwen_qs;
end
- addr_hit[309]: begin
+ addr_hit[313]: begin
reg_rdata_next[0] = classd_ctrl_shadowed_en_qs;
reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs;
reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs;
@@ -15277,51 +15449,51 @@
reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs;
end
- addr_hit[310]: begin
+ addr_hit[314]: begin
reg_rdata_next[0] = classd_clr_regwen_qs;
end
- addr_hit[311]: begin
+ addr_hit[315]: begin
reg_rdata_next[0] = classd_clr_shadowed_qs;
end
- addr_hit[312]: begin
+ addr_hit[316]: begin
reg_rdata_next[15:0] = classd_accum_cnt_qs;
end
- addr_hit[313]: begin
+ addr_hit[317]: begin
reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs;
end
- addr_hit[314]: begin
+ addr_hit[318]: begin
reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs;
end
- addr_hit[315]: begin
+ addr_hit[319]: begin
reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs;
end
- addr_hit[316]: begin
+ addr_hit[320]: begin
reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs;
end
- addr_hit[317]: begin
+ addr_hit[321]: begin
reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs;
end
- addr_hit[318]: begin
+ addr_hit[322]: begin
reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs;
end
- addr_hit[319]: begin
+ addr_hit[323]: begin
reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs;
end
- addr_hit[320]: begin
+ addr_hit[324]: begin
reg_rdata_next[31:0] = classd_esc_cnt_qs;
end
- addr_hit[321]: begin
+ addr_hit[325]: begin
reg_rdata_next[2:0] = classd_state_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index a5d996d..b30bab3 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -2171,7 +2171,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
kmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:39]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:39]),
.EnMasking(KmacEnMasking),
.ReuseShare(KmacReuseShare),
.SecCmdDelay(SecKmacCmdDelay),
@@ -2183,9 +2183,10 @@
.intr_kmac_done_o (intr_kmac_kmac_done),
.intr_fifo_empty_o (intr_kmac_fifo_empty),
.intr_kmac_err_o (intr_kmac_kmac_err),
- // [39]: fatal_fault
- .alert_tx_o ( alert_tx[39:39] ),
- .alert_rx_i ( alert_rx[39:39] ),
+ // [39]: fatal_fault_err
+ // [40]: recov_operation_err
+ .alert_tx_o ( alert_tx[40:39] ),
+ .alert_rx_i ( alert_rx[40:39] ),
// Inter-module signals
.keymgr_key_i(keymgr_kmac_key),
@@ -2201,11 +2202,12 @@
// Clock and reset connections
.clk_i (clkmgr_aon_clocks.clk_main_kmac),
.clk_edn_i (clkmgr_aon_clocks.clk_main_kmac),
+ .rst_shadowed_ni (rstmgr_aon_resets.rst_sys_shadowed_n[rstmgr_pkg::Domain0Sel]),
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
otbn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:40]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[42:41]),
.Stub(OtbnStub),
.RegFile(OtbnRegFile),
.RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed),
@@ -2215,10 +2217,10 @@
// Interrupt
.intr_done_o (intr_otbn_done),
- // [40]: fatal
- // [41]: recov
- .alert_tx_o ( alert_tx[41:40] ),
- .alert_rx_i ( alert_rx[41:40] ),
+ // [41]: fatal
+ // [42]: recov
+ .alert_tx_o ( alert_tx[42:41] ),
+ .alert_rx_i ( alert_rx[42:41] ),
// Inter-module signals
.otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
@@ -2244,7 +2246,7 @@
.rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
keymgr #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:43]),
.KmacEnMasking(KeymgrKmacEnMasking),
.RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
.RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
@@ -2263,10 +2265,10 @@
// Interrupt
.intr_op_done_o (intr_keymgr_op_done),
- // [42]: fatal_fault_err
- // [43]: recov_operation_err
- .alert_tx_o ( alert_tx[43:42] ),
- .alert_rx_i ( alert_rx[43:42] ),
+ // [43]: fatal_fault_err
+ // [44]: recov_operation_err
+ .alert_tx_o ( alert_tx[44:43] ),
+ .alert_rx_i ( alert_rx[44:43] ),
// Inter-module signals
.edn_o(edn0_edn_req[0]),
@@ -2294,7 +2296,7 @@
.rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
csrng #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[45:44]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
.RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
.RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
.SBoxImpl(CsrngSBoxImpl)
@@ -2305,10 +2307,10 @@
.intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
.intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
.intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
- // [44]: recov_alert
- // [45]: fatal_alert
- .alert_tx_o ( alert_tx[45:44] ),
- .alert_rx_i ( alert_rx[45:44] ),
+ // [45]: recov_alert
+ // [46]: fatal_alert
+ .alert_tx_o ( alert_tx[46:45] ),
+ .alert_rx_i ( alert_rx[46:45] ),
// Inter-module signals
.csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2327,7 +2329,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
entropy_src #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[47:46]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
.Stub(EntropySrcStub)
) u_entropy_src (
@@ -2336,10 +2338,10 @@
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
.intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
.intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [46]: recov_alert
- // [47]: fatal_alert
- .alert_tx_o ( alert_tx[47:46] ),
- .alert_rx_i ( alert_rx[47:46] ),
+ // [47]: recov_alert
+ // [48]: fatal_alert
+ .alert_tx_o ( alert_tx[48:47] ),
+ .alert_rx_i ( alert_rx[48:47] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2361,16 +2363,16 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:48])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49])
) u_edn0 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
- // [48]: recov_alert
- // [49]: fatal_alert
- .alert_tx_o ( alert_tx[49:48] ),
- .alert_rx_i ( alert_rx[49:48] ),
+ // [49]: recov_alert
+ // [50]: fatal_alert
+ .alert_tx_o ( alert_tx[50:49] ),
+ .alert_rx_i ( alert_rx[50:49] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2385,16 +2387,16 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[51:50])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51])
) u_edn1 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
- // [50]: recov_alert
- // [51]: fatal_alert
- .alert_tx_o ( alert_tx[51:50] ),
- .alert_rx_i ( alert_rx[51:50] ),
+ // [51]: recov_alert
+ // [52]: fatal_alert
+ .alert_tx_o ( alert_tx[52:51] ),
+ .alert_rx_i ( alert_rx[52:51] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2409,7 +2411,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:52]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]),
.RndCnstSramKey(RndCnstSramCtrlMainSramKey),
.RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
.RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
@@ -2417,9 +2419,9 @@
.MemSizeRam(131072),
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [52]: fatal_error
- .alert_tx_o ( alert_tx[52:52] ),
- .alert_rx_i ( alert_rx[52:52] ),
+ // [53]: fatal_error
+ .alert_tx_o ( alert_tx[53:53] ),
+ .alert_rx_i ( alert_rx[53:53] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2440,15 +2442,15 @@
.rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
rom_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:54]),
.BootRomInitFile(RomCtrlBootRomInitFile),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey),
.SecDisableScrambling(SecRomCtrlDisableScrambling)
) u_rom_ctrl (
- // [53]: fatal
- .alert_tx_o ( alert_tx[53:53] ),
- .alert_rx_i ( alert_rx[53:53] ),
+ // [54]: fatal
+ .alert_tx_o ( alert_tx[54:54] ),
+ .alert_rx_i ( alert_rx[54:54] ),
// Inter-module signals
.rom_cfg_i(ast_rom_cfg),
@@ -2466,7 +2468,7 @@
.rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
rv_core_ibex #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:54]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:55]),
.RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed),
.RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm),
.PMPEnable(RvCoreIbexPMPEnable),
@@ -2489,12 +2491,12 @@
.DmExceptionAddr(RvCoreIbexDmExceptionAddr),
.PipeLine(RvCoreIbexPipeLine)
) u_rv_core_ibex (
- // [54]: fatal_sw_err
- // [55]: recov_sw_err
- // [56]: fatal_hw_err
- // [57]: recov_hw_err
- .alert_tx_o ( alert_tx[57:54] ),
- .alert_rx_i ( alert_rx[57:54] ),
+ // [55]: fatal_sw_err
+ // [56]: recov_sw_err
+ // [57]: fatal_hw_err
+ // [58]: recov_hw_err
+ .alert_tx_o ( alert_tx[58:55] ),
+ .alert_rx_i ( alert_rx[58:55] ),
// Inter-module signals
.rst_cpu_n_o(rv_core_ibex_rst_cpu_n),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index c97f436..7486f01 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -207,7 +207,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[58] = {
+ top_earlgrey_alert_for_peripheral[59] = {
[kTopEarlgreyAlertIdUart0FatalFault] = kTopEarlgreyAlertPeripheralUart0,
[kTopEarlgreyAlertIdUart1FatalFault] = kTopEarlgreyAlertPeripheralUart1,
[kTopEarlgreyAlertIdUart2FatalFault] = kTopEarlgreyAlertPeripheralUart2,
@@ -247,7 +247,8 @@
[kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdHmacFatalFault] = kTopEarlgreyAlertPeripheralHmac,
- [kTopEarlgreyAlertIdKmacFatalFault] = kTopEarlgreyAlertPeripheralKmac,
+ [kTopEarlgreyAlertIdKmacFatalFaultErr] = kTopEarlgreyAlertPeripheralKmac,
+ [kTopEarlgreyAlertIdKmacRecovOperationErr] = kTopEarlgreyAlertPeripheralKmac,
[kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn,
[kTopEarlgreyAlertIdOtbnRecov] = kTopEarlgreyAlertPeripheralOtbn,
[kTopEarlgreyAlertIdKeymgrFatalFaultErr] = kTopEarlgreyAlertPeripheralKeymgr,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index bd825c2..49116a8 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1319,26 +1319,27 @@
kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 36, /**< aes_recov_ctrl_update_err */
kTopEarlgreyAlertIdAesFatalFault = 37, /**< aes_fatal_fault */
kTopEarlgreyAlertIdHmacFatalFault = 38, /**< hmac_fatal_fault */
- kTopEarlgreyAlertIdKmacFatalFault = 39, /**< kmac_fatal_fault */
- kTopEarlgreyAlertIdOtbnFatal = 40, /**< otbn_fatal */
- kTopEarlgreyAlertIdOtbnRecov = 41, /**< otbn_recov */
- kTopEarlgreyAlertIdKeymgrFatalFaultErr = 42, /**< keymgr_fatal_fault_err */
- kTopEarlgreyAlertIdKeymgrRecovOperationErr = 43, /**< keymgr_recov_operation_err */
- kTopEarlgreyAlertIdCsrngRecovAlert = 44, /**< csrng_recov_alert */
- kTopEarlgreyAlertIdCsrngFatalAlert = 45, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdEntropySrcRecovAlert = 46, /**< entropy_src_recov_alert */
- kTopEarlgreyAlertIdEntropySrcFatalAlert = 47, /**< entropy_src_fatal_alert */
- kTopEarlgreyAlertIdEdn0RecovAlert = 48, /**< edn0_recov_alert */
- kTopEarlgreyAlertIdEdn0FatalAlert = 49, /**< edn0_fatal_alert */
- kTopEarlgreyAlertIdEdn1RecovAlert = 50, /**< edn1_recov_alert */
- kTopEarlgreyAlertIdEdn1FatalAlert = 51, /**< edn1_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalError = 52, /**< sram_ctrl_main_fatal_error */
- kTopEarlgreyAlertIdRomCtrlFatal = 53, /**< rom_ctrl_fatal */
- kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 54, /**< rv_core_ibex_fatal_sw_err */
- kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 55, /**< rv_core_ibex_recov_sw_err */
- kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 56, /**< rv_core_ibex_fatal_hw_err */
- kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 57, /**< rv_core_ibex_recov_hw_err */
- kTopEarlgreyAlertIdLast = 57, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdKmacFatalFaultErr = 39, /**< kmac_fatal_fault_err */
+ kTopEarlgreyAlertIdKmacRecovOperationErr = 40, /**< kmac_recov_operation_err */
+ kTopEarlgreyAlertIdOtbnFatal = 41, /**< otbn_fatal */
+ kTopEarlgreyAlertIdOtbnRecov = 42, /**< otbn_recov */
+ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 43, /**< keymgr_fatal_fault_err */
+ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 44, /**< keymgr_recov_operation_err */
+ kTopEarlgreyAlertIdCsrngRecovAlert = 45, /**< csrng_recov_alert */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 46, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 47, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 48, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdEdn0RecovAlert = 49, /**< edn0_recov_alert */
+ kTopEarlgreyAlertIdEdn0FatalAlert = 50, /**< edn0_fatal_alert */
+ kTopEarlgreyAlertIdEdn1RecovAlert = 51, /**< edn1_recov_alert */
+ kTopEarlgreyAlertIdEdn1FatalAlert = 52, /**< edn1_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalError = 53, /**< sram_ctrl_main_fatal_error */
+ kTopEarlgreyAlertIdRomCtrlFatal = 54, /**< rom_ctrl_fatal */
+ kTopEarlgreyAlertIdRvCoreIbexFatalSwErr = 55, /**< rv_core_ibex_fatal_sw_err */
+ kTopEarlgreyAlertIdRvCoreIbexRecovSwErr = 56, /**< rv_core_ibex_recov_sw_err */
+ kTopEarlgreyAlertIdRvCoreIbexFatalHwErr = 57, /**< rv_core_ibex_fatal_hw_err */
+ kTopEarlgreyAlertIdRvCoreIbexRecovHwErr = 58, /**< rv_core_ibex_recov_hw_err */
+ kTopEarlgreyAlertIdLast = 58, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1348,7 +1349,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[58];
+ top_earlgrey_alert_for_peripheral[59];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
diff --git a/sw/device/lib/dif/autogen/dif_kmac_autogen.c b/sw/device/lib/dif/autogen/dif_kmac_autogen.c
index 4b534bd..c1fd9c3 100644
--- a/sw/device/lib/dif/autogen/dif_kmac_autogen.c
+++ b/sw/device/lib/dif/autogen/dif_kmac_autogen.c
@@ -29,8 +29,11 @@
bitfield_bit32_index_t alert_idx;
switch (alert) {
- case kDifKmacAlertFatalFault:
- alert_idx = KMAC_ALERT_TEST_FATAL_FAULT_BIT;
+ case kDifKmacAlertFatalFaultErr:
+ alert_idx = KMAC_ALERT_TEST_FATAL_FAULT_ERR_BIT;
+ break;
+ case kDifKmacAlertRecovOperationErr:
+ alert_idx = KMAC_ALERT_TEST_RECOV_OPERATION_ERR_BIT;
break;
default:
return kDifBadArg;
diff --git a/sw/device/lib/dif/autogen/dif_kmac_autogen.h b/sw/device/lib/dif/autogen/dif_kmac_autogen.h
index 588dc7c..948ebf0 100644
--- a/sw/device/lib/dif/autogen/dif_kmac_autogen.h
+++ b/sw/device/lib/dif/autogen/dif_kmac_autogen.h
@@ -54,9 +54,14 @@
typedef enum dif_kmac_alert {
/**
* This fatal alert is triggered when a fatal TL-UL bus integrity fault is
- * detected.
+ * detected or the shadow registers storage error occurs.
*/
- kDifKmacAlertFatalFault = 0,
+ kDifKmacAlertFatalFaultErr = 0,
+ /**
+ * Alert for KMAC operation error. It occurs when the shadow registers have
+ * update errors.
+ */
+ kDifKmacAlertRecovOperationErr = 1,
} dif_kmac_alert_t;
/**
diff --git a/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc
index b48e903..6c1fef0 100644
--- a/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc
@@ -38,7 +38,8 @@
class AlertForceTest : public KmacTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_kmac_alert_force(nullptr, kDifKmacAlertFatalFault), kDifBadArg);
+ EXPECT_EQ(dif_kmac_alert_force(nullptr, kDifKmacAlertFatalFaultErr),
+ kDifBadArg);
}
TEST_F(AlertForceTest, BadAlert) {
@@ -49,8 +50,14 @@
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(KMAC_ALERT_TEST_REG_OFFSET,
- {{KMAC_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_kmac_alert_force(&kmac_, kDifKmacAlertFatalFault), kDifOk);
+ {{KMAC_ALERT_TEST_FATAL_FAULT_ERR_BIT, true}});
+ EXPECT_EQ(dif_kmac_alert_force(&kmac_, kDifKmacAlertFatalFaultErr), kDifOk);
+
+ // Force last alert.
+ EXPECT_WRITE32(KMAC_ALERT_TEST_REG_OFFSET,
+ {{KMAC_ALERT_TEST_RECOV_OPERATION_ERR_BIT, true}});
+ EXPECT_EQ(dif_kmac_alert_force(&kmac_, kDifKmacAlertRecovOperationErr),
+ kDifOk);
}
class IrqGetStateTest : public KmacTest {};
diff --git a/sw/device/lib/dif/dif_kmac.c b/sw/device/lib/dif/dif_kmac.c
index 4b3178c..34608bf 100644
--- a/sw/device/lib/dif/dif_kmac.c
+++ b/sw/device/lib/dif/dif_kmac.c
@@ -149,14 +149,14 @@
bool entropy_ready = false;
switch (config.entropy_mode) {
case kDifKmacEntropyModeIdle:
- entropy_mode_value = KMAC_CFG_ENTROPY_MODE_VALUE_IDLE_MODE;
+ entropy_mode_value = KMAC_CFG_SHADOWED_ENTROPY_MODE_VALUE_IDLE_MODE;
break;
case kDifKmacEntropyModeEdn:
- entropy_mode_value = KMAC_CFG_ENTROPY_MODE_VALUE_EDN_MODE;
+ entropy_mode_value = KMAC_CFG_SHADOWED_ENTROPY_MODE_VALUE_EDN_MODE;
entropy_ready = true;
break;
case kDifKmacEntropyModeSoftware:
- entropy_mode_value = KMAC_CFG_ENTROPY_MODE_VALUE_SW_MODE;
+ entropy_mode_value = KMAC_CFG_SHADOWED_ENTROPY_MODE_VALUE_SW_MODE;
break;
default:
return kDifBadArg;
@@ -169,19 +169,22 @@
// Write configuration register.
uint32_t cfg_reg = 0;
- cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_MSG_ENDIANNESS_BIT,
+ cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_MSG_ENDIANNESS_BIT,
config.message_big_endian);
- cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_STATE_ENDIANNESS_BIT,
- config.output_big_endian);
- cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_ENTROPY_MODE_FIELD,
- entropy_mode_value);
- cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_ENTROPY_FAST_PROCESS_BIT,
- config.entropy_fast_process);
cfg_reg =
- bitfield_bit32_write(cfg_reg, KMAC_CFG_SIDELOAD_BIT, config.sideload);
+ bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_STATE_ENDIANNESS_BIT,
+ config.output_big_endian);
+ cfg_reg = bitfield_field32_write(
+ cfg_reg, KMAC_CFG_SHADOWED_ENTROPY_MODE_FIELD, entropy_mode_value);
cfg_reg =
- bitfield_bit32_write(cfg_reg, KMAC_CFG_ENTROPY_READY_BIT, entropy_ready);
- mmio_region_write32(kmac->base_addr, KMAC_CFG_REG_OFFSET, cfg_reg);
+ bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_ENTROPY_FAST_PROCESS_BIT,
+ config.entropy_fast_process);
+ cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_SIDELOAD_BIT,
+ config.sideload);
+ cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_ENTROPY_READY_BIT,
+ entropy_ready);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
// Write entropy period register.
uint32_t entropy_period_reg = 0;
@@ -232,25 +235,25 @@
uint32_t kstrength;
switch (mode) {
case kDifKmacModeSha3Len224:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L224;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L224;
operation_state->offset = 0;
operation_state->r = calculate_rate_bits(224) / 32;
operation_state->d = 224 / 32;
break;
case kDifKmacModeSha3Len256:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L256;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L256;
operation_state->offset = 0;
operation_state->r = calculate_rate_bits(256) / 32;
operation_state->d = 256 / 32;
break;
case kDifKmacModeSha3Len384:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L384;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L384;
operation_state->offset = 0;
operation_state->r = calculate_rate_bits(384) / 32;
operation_state->d = 384 / 32;
break;
case kDifKmacModeSha3Len512:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L512;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L512;
operation_state->offset = 0;
operation_state->r = calculate_rate_bits(512) / 32;
operation_state->d = 512 / 32;
@@ -262,12 +265,14 @@
operation_state->append_d = false;
// Configure SHA-3 mode with the given strength.
- uint32_t cfg_reg = mmio_region_read32(kmac->base_addr, KMAC_CFG_REG_OFFSET);
- cfg_reg =
- bitfield_field32_write(cfg_reg, KMAC_CFG_KSTRENGTH_FIELD, kstrength);
- cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_MODE_FIELD,
- KMAC_CFG_MODE_VALUE_SHA3);
- mmio_region_write32(kmac->base_addr, KMAC_CFG_REG_OFFSET, cfg_reg);
+ uint32_t cfg_reg =
+ mmio_region_read32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_KSTRENGTH_FIELD,
+ kstrength);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_MODE_FIELD,
+ KMAC_CFG_SHADOWED_MODE_VALUE_SHA3);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
// Issue start command.
uint32_t cmd_reg =
@@ -301,11 +306,11 @@
uint32_t kstrength;
switch (mode) {
case kDifKmacModeShakeLen128:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L128;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L128;
operation_state->r = calculate_rate_bits(128) / 32;
break;
case kDifKmacModeShakeLen256:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L256;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L256;
operation_state->r = calculate_rate_bits(256) / 32;
break;
default:
@@ -317,12 +322,14 @@
operation_state->offset = 0;
// Configure SHAKE mode with the given strength.
- uint32_t cfg_reg = mmio_region_read32(kmac->base_addr, KMAC_CFG_REG_OFFSET);
- cfg_reg =
- bitfield_field32_write(cfg_reg, KMAC_CFG_KSTRENGTH_FIELD, kstrength);
- cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_MODE_FIELD,
- KMAC_CFG_MODE_VALUE_SHAKE);
- mmio_region_write32(kmac->base_addr, KMAC_CFG_REG_OFFSET, cfg_reg);
+ uint32_t cfg_reg =
+ mmio_region_read32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_KSTRENGTH_FIELD,
+ kstrength);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_MODE_FIELD,
+ KMAC_CFG_SHADOWED_MODE_VALUE_SHAKE);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
// Issue start command.
uint32_t cmd_reg =
@@ -373,11 +380,11 @@
uint32_t kstrength;
switch (mode) {
case kDifKmacModeCshakeLen128:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L128;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L128;
operation_state->r = calculate_rate_bits(128) / 32;
break;
case kDifKmacModeCshakeLen256:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L256;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L256;
operation_state->r = calculate_rate_bits(256) / 32;
break;
default:
@@ -389,12 +396,14 @@
operation_state->offset = 0;
// Configure cSHAKE mode with the given strength.
- uint32_t cfg_reg = mmio_region_read32(kmac->base_addr, KMAC_CFG_REG_OFFSET);
- cfg_reg =
- bitfield_field32_write(cfg_reg, KMAC_CFG_KSTRENGTH_FIELD, kstrength);
- cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_MODE_FIELD,
- KMAC_CFG_MODE_VALUE_CSHAKE);
- mmio_region_write32(kmac->base_addr, KMAC_CFG_REG_OFFSET, cfg_reg);
+ uint32_t cfg_reg =
+ mmio_region_read32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_KSTRENGTH_FIELD,
+ kstrength);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_MODE_FIELD,
+ KMAC_CFG_SHADOWED_MODE_VALUE_CSHAKE);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
// Calculate PREFIX register values.
uint32_t prefix_regs[11] = {0};
@@ -464,11 +473,11 @@
uint32_t kstrength;
switch (mode) {
case kDifKmacModeCshakeLen128:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L128;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L128;
operation_state->r = calculate_rate_bits(128) / 32;
break;
case kDifKmacModeCshakeLen256:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L256;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L256;
operation_state->r = calculate_rate_bits(256) / 32;
break;
default:
@@ -512,13 +521,15 @@
}
// Configure cSHAKE mode with the given strength and enable KMAC mode.
- uint32_t cfg_reg = mmio_region_read32(kmac->base_addr, KMAC_CFG_REG_OFFSET);
- cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_KMAC_EN_BIT, true);
- cfg_reg =
- bitfield_field32_write(cfg_reg, KMAC_CFG_KSTRENGTH_FIELD, kstrength);
- cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_MODE_FIELD,
- KMAC_CFG_MODE_VALUE_CSHAKE);
- mmio_region_write32(kmac->base_addr, KMAC_CFG_REG_OFFSET, cfg_reg);
+ uint32_t cfg_reg =
+ mmio_region_read32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET);
+ cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_KMAC_EN_BIT, true);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_KSTRENGTH_FIELD,
+ kstrength);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_MODE_FIELD,
+ KMAC_CFG_SHADOWED_MODE_VALUE_CSHAKE);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
+ mmio_region_write32(kmac->base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
// Initialize prefix registers with function name ("KMAC") and empty
// customization string. The empty customization string will be overwritten if
diff --git a/sw/device/sca/sha3_serial.c b/sw/device/sca/sha3_serial.c
index 48e8bf8..c556377 100644
--- a/sw/device/sca/sha3_serial.c
+++ b/sw/device/sca/sha3_serial.c
@@ -143,11 +143,11 @@
uint32_t kstrength;
switch (mode) {
case kDifKmacModeCshakeLen128:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L128;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L128;
kmac_operation_state.r = calculate_rate_bits(128) / 32;
break;
case kDifKmacModeCshakeLen256:
- kstrength = KMAC_CFG_KSTRENGTH_VALUE_L256;
+ kstrength = KMAC_CFG_SHADOWED_KSTRENGTH_VALUE_L256;
kmac_operation_state.r = calculate_rate_bits(256) / 32;
break;
default:
@@ -195,13 +195,15 @@
}
// Configure cSHAKE mode with the given strength and enable KMAC mode.
- uint32_t cfg_reg = mmio_region_read32(kmac.base_addr, KMAC_CFG_REG_OFFSET);
- cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_KMAC_EN_BIT, true);
- cfg_reg =
- bitfield_field32_write(cfg_reg, KMAC_CFG_KSTRENGTH_FIELD, kstrength);
- cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_MODE_FIELD,
- KMAC_CFG_MODE_VALUE_CSHAKE);
- mmio_region_write32(kmac.base_addr, KMAC_CFG_REG_OFFSET, cfg_reg);
+ uint32_t cfg_reg =
+ mmio_region_read32(kmac.base_addr, KMAC_CFG_SHADOWED_REG_OFFSET);
+ cfg_reg = bitfield_bit32_write(cfg_reg, KMAC_CFG_SHADOWED_KMAC_EN_BIT, true);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_KSTRENGTH_FIELD,
+ kstrength);
+ cfg_reg = bitfield_field32_write(cfg_reg, KMAC_CFG_SHADOWED_MODE_FIELD,
+ KMAC_CFG_SHADOWED_MODE_VALUE_CSHAKE);
+ mmio_region_write32(kmac.base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
+ mmio_region_write32(kmac.base_addr, KMAC_CFG_SHADOWED_REG_OFFSET, cfg_reg);
// Initialize prefix registers with function name ("KMAC") and empty
// customization string. The empty customization string will be overwritten if
