[entropy_src/rtl] add fatal alert
ERR_CODE is RO and can be tested with a register.
Re-ran top level to make updates to interconnections.
Re-ran the reg script.
Re-ran top level again.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index 20fdf1f..a85e067 100644
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson
@@ -18,8 +18,8 @@
desc: "Asserted when entropy source bits are available."}
{ name: "es_health_test_failed"
desc: "Asserted when the alert count has been met."}
- { name: "es_fifo_err"
- desc: "Asserted when a FIFO error occurs."}
+ { name: "es_fatal_err"
+ desc: "Asserted when a FIFO error occurs, or if an illegal state machine state is reached."}
],
inter_signal_list: [
{ struct: "entropy_src_hw_if",
@@ -49,9 +49,11 @@
}
],
alert_list: [
- { name: "recov_alert_count_met",
- desc: '''This alert is triggered upon the alert health test threshold criteria not met.
- '''
+ { name: "recov_alert",
+ desc: "This alert is triggered upon the alert health test threshold criteria not met."
+ }
+ { name: "fatal_alert",
+ desc: "This alert triggers if an illegal state machine state is reached."
}
],
@@ -913,7 +915,7 @@
{
name: "ERR_CODE",
desc: "Hardware detection of error conditions status register",
- swaccess: "rw",
+ swaccess: "ro",
hwaccess: "hwo",
fields: [
{ bits: "0",
@@ -943,6 +945,24 @@
This bit will stay set until firmware clears it.
'''
}
+ { bits: "20",
+ name: "ES_ACK_SM_ERR",
+ desc: '''
+ This bit will be set to one when an illegal state has been detected for the
+ ES ack stage state machine. This error will signal a fatal alert, and also
+ an interrupt if enabled.
+ This bit will stay set until firmware clears it.
+ '''
+ }
+ { bits: "21",
+ name: "ES_MAIN_SM_ERR",
+ desc: '''
+ This bit will be set to one when an illegal state has been detected for the
+ ES main stage state machine. This error will signal a fatal alert, and also
+ an interrupt if enabled.
+ This bit will stay set until firmware clears it.
+ '''
+ }
{ bits: "28",
name: "FIFO_WRITE_ERR",
desc: '''
@@ -972,5 +992,26 @@
}
]
},
+ { name: "ERR_CODE_TEST",
+ desc: "Test error conditions register",
+ swaccess: "rw",
+ hwaccess: "hro",
+ hwqe: "true",
+ regwen: "REGWEN",
+ fields: [
+ {
+ bits: "4:0",
+ name: "ERR_CODE_TEST",
+ desc: '''
+ Setting this field will set the bit number for which an error
+ will be forced in the hardware. This bit number is that same one
+ found in the !!ERR_CODE register. The action of writing this
+ register will force an error pulse. The sole purpose of this
+ register is to test that any error properly propagates to either
+ an interrupt or an alert.
+ '''
+ },
+ ]
+ },
]
}
diff --git a/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv b/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv
index a8c4ba7..5962e9e 100644
--- a/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv
+++ b/hw/ip/entropy_src/dv/env/entropy_src_env_pkg.sv
@@ -31,8 +31,8 @@
32'h9124836c,
32'hb5a7efd9,
32'h124836cb};
- parameter string LIST_OF_ALERTS[] = {"recov_alert_count_met"};
- parameter uint NUM_ALERTS = 1;
+ parameter string LIST_OF_ALERTS[] = {"recov_alert","fatal_alert"};
+ parameter uint NUM_ALERTS = 2;
// types
typedef enum int {
diff --git a/hw/ip/entropy_src/dv/tb/tb.sv b/hw/ip/entropy_src/dv/tb/tb.sv
index 8bd3a0a..cb1ca60 100644
--- a/hw/ip/entropy_src/dv/tb/tb.sv
+++ b/hw/ip/entropy_src/dv/tb/tb.sv
@@ -16,7 +16,7 @@
wire clk, rst_n;
wire devmode, efuse_es_sw_reg_en;
wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
- wire intr_entropy_valid, intr_health_test_failed, intr_fifo_err;
+ wire intr_entropy_valid, intr_health_test_failed, intr_fatal_err;
// interfaces
clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
@@ -57,12 +57,12 @@
.intr_es_entropy_valid_o (intr_entropy_valid),
.intr_es_health_test_failed_o (intr_health_test_failed),
- .intr_es_fifo_err_o (intr_fifo_err)
+ .intr_es_fatal_err_o (intr_fatal_err)
);
assign interrupts[EntropyValid] = intr_entropy_valid;
assign interrupts[HealthTestFailed] = intr_health_test_failed;
- assign interrupts[FifoErr] = intr_fifo_err;
+ assign interrupts[FifoErr] = intr_fatal_err;
initial begin
// drive clk and rst_n from clk_if
diff --git a/hw/ip/entropy_src/rtl/entropy_src.sv b/hw/ip/entropy_src/rtl/entropy_src.sv
index 82f1bfe..362fced 100644
--- a/hw/ip/entropy_src/rtl/entropy_src.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src.sv
@@ -7,8 +7,11 @@
`include "prim_assert.sv"
-module entropy_src import entropy_src_pkg::*; #(
- parameter logic AlertAsyncOn = 1,
+module entropy_src
+ import entropy_src_pkg::*;
+ import entropy_src_reg_pkg::*;
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
parameter int EsFifoDepth = 2
) (
input logic clk_i,
@@ -34,13 +37,13 @@
input entropy_src_xht_rsp_t entropy_src_xht_i,
// Alerts
- input prim_alert_pkg::alert_rx_t alert_rx_i,
- output prim_alert_pkg::alert_tx_t alert_tx_o,
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
// Interrupts
output logic intr_es_entropy_valid_o,
output logic intr_es_health_test_failed_o,
- output logic intr_es_fifo_err_o
+ output logic intr_es_fatal_err_o
);
import entropy_src_reg_pkg::*;
@@ -48,8 +51,8 @@
entropy_src_reg2hw_t reg2hw;
entropy_src_hw2reg_t hw2reg;
- logic recov_alert_event;
- logic alert_test;
+ logic [NumAlerts-1:0] alert_test;
+ logic [NumAlerts-1:0] alert;
entropy_src_reg_top u_reg (
.clk_i,
@@ -81,27 +84,33 @@
.entropy_src_rng_o,
.entropy_src_rng_i,
- .recov_alert_event_o(recov_alert_event),
- .alert_test_o(alert_test),
+ .recov_alert_o(alert[0]),
+ .fatal_alert_o(alert[1]),
+
+ .recov_alert_test_o(alert_test[0]),
+ .fatal_alert_test_o(alert_test[1]),
.intr_es_entropy_valid_o,
.intr_es_health_test_failed_o,
- .intr_es_fifo_err_o
+ .intr_es_fatal_err_o
);
- prim_alert_sender #(
- .AsyncOn(AlertAsyncOn),
- .IsFatal(0)
- ) u_alert_sender_i (
- .clk_i ( clk_i ),
- .rst_ni ( rst_ni ),
- .alert_test_i ( alert_test ),
- .alert_req_i ( recov_alert_event),
- .alert_ack_o ( ),
- .alert_state_o ( ),
- .alert_rx_i ( alert_rx_i ),
- .alert_tx_o ( alert_tx_o )
- );
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(i)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alert[i] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
// Outputs should have a known value after reset
`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
@@ -130,6 +139,6 @@
// Interrupts
`ASSERT_KNOWN(IntrEsEntropyValidKnownO_A, intr_es_entropy_valid_o)
`ASSERT_KNOWN(IntrEsHealthTestFailedKnownO_A, intr_es_health_test_failed_o)
- `ASSERT_KNOWN(IntrEsFifoErrKnownO_A, intr_es_fifo_err_o)
+ `ASSERT_KNOWN(IntrEsFifoErrKnownO_A, intr_es_fatal_err_o)
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv
index 620b491..5c43698 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_ack_sm.sv
@@ -12,29 +12,36 @@
input logic req_i,
output logic ack_o,
input logic fifo_not_empty_i,
- output logic fifo_pop_o
+ output logic fifo_pop_o,
+ output logic ack_sm_err_o
);
- // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 3 -n 6 -s 3584999330
- // Hamming distance histogram:
- //
- // 0: --
- // 1: --
- // 2: --
- // 3: |||||||||||||||||||| (66.67%)
- // 4: |||||||||| (33.33%)
- // 5: --
- // 6: --
- //
- // Minimum Hamming distance: 3
- // Maximum Hamming distance: 4
- //
+// Encoding generated with:
+// $ ./util/design/sparse-fsm-encode.py -d 3 -m 4 -n 6 \
+// -s 1236774883 --language=sv
+//
+// Hamming distance histogram:
+//
+// 0: --
+// 1: --
+// 2: --
+// 3: |||||||||||||||||||| (66.67%)
+// 4: ||||| (16.67%)
+// 5: --
+// 6: ||||| (16.67%)
+//
+// Minimum Hamming distance: 3
+// Maximum Hamming distance: 6
+// Minimum Hamming weight: 1
+// Maximum Hamming weight: 4
+//
localparam int StateWidth = 6;
typedef enum logic [StateWidth-1:0] {
- Idle = 6'b010110, // idle
- AckImmed = 6'b111111, // ack the request immediately
- AckWait = 6'b111000 // wait until the fifo has an entry
+ Idle = 6'b010100, // idle
+ AckImmed = 6'b101100, // ack the request immediately
+ AckWait = 6'b000010, // wait until the fifo has an entry
+ Error = 6'b101011 // illegal state reached and hang
} state_e;
state_e state_d, state_q;
@@ -60,6 +67,7 @@
state_d = state_q;
ack_o = 1'b0;
fifo_pop_o = 1'b0;
+ ack_sm_err_o = 1'b0;
unique case (state_q)
Idle: begin
if (req_i) begin
@@ -82,7 +90,10 @@
state_d = Idle;
end
end
- default: state_d = Idle;
+ Error: begin
+ ack_sm_err_o = 1'b1;
+ end
+ default: state_d = Error;
endcase
end
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index 114c49b..26d13d2 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -30,12 +30,14 @@
output entropy_src_xht_req_t entropy_src_xht_o,
input entropy_src_xht_rsp_t entropy_src_xht_i,
- output logic recov_alert_event_o,
- output logic alert_test_o,
+ output logic recov_alert_test_o,
+ output logic fatal_alert_test_o,
+ output logic recov_alert_o,
+ output logic fatal_alert_o,
output logic intr_es_entropy_valid_o,
output logic intr_es_health_test_failed_o,
- output logic intr_es_fifo_err_o
+ output logic intr_es_fatal_err_o
);
import entropy_src_reg_pkg::*;
@@ -72,7 +74,7 @@
logic sw_es_rd_pulse;
logic event_es_entropy_valid;
logic event_es_health_test_failed;
- logic event_es_fifo_err;
+ logic event_es_fatal_err;
logic [15:0] es_rate;
logic es_rate_entropy_pulse;
logic es_rng_src_valid;
@@ -261,6 +263,17 @@
logic es_hw_if_req;
logic es_hw_if_ack;
logic es_hw_if_fifo_pop;
+ logic sfifo_esrng_err_sum;
+ logic sfifo_precon_err_sum;
+ logic sfifo_esfinal_err_sum;
+ logic es_ack_sm_err_sum;
+ logic es_ack_sm_err;
+ logic es_main_sm_err_sum;
+ logic es_main_sm_err;
+ logic fifo_write_err_sum;
+ logic fifo_read_err_sum;
+ logic fifo_status_err_sum;
+ logic [30:0] err_code_test_bit;
// flops
logic [15:0] es_rate_cntr_q, es_rate_cntr_d;
@@ -351,17 +364,17 @@
prim_intr_hw #(
.Width(1)
- ) u_intr_hw_es_fifo_err (
+ ) u_intr_hw_es_fatal_err (
.clk_i (clk_i),
.rst_ni (rst_ni),
- .event_intr_i (event_es_fifo_err),
- .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_fifo_err.q),
- .reg2hw_intr_test_q_i (reg2hw.intr_test.es_fifo_err.q),
- .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_fifo_err.qe),
- .reg2hw_intr_state_q_i (reg2hw.intr_state.es_fifo_err.q),
- .hw2reg_intr_state_de_o (hw2reg.intr_state.es_fifo_err.de),
- .hw2reg_intr_state_d_o (hw2reg.intr_state.es_fifo_err.d),
- .intr_o (intr_es_fifo_err_o)
+ .event_intr_i (event_es_fatal_err),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.es_fatal_err.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.es_fatal_err.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.es_fatal_err.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.es_fatal_err.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.es_fatal_err.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.es_fatal_err.d),
+ .intr_o (intr_es_fatal_err_o)
);
//--------------------------------------------
@@ -416,40 +429,84 @@
// set the interrupt sources
- assign event_es_fifo_err = es_enable && (
- (|sfifo_esrng_err) ||
- (|sfifo_precon_err) ||
- (|sfifo_esfinal_err));
+ assign event_es_fatal_err = es_enable && (
+ sfifo_esrng_err_sum ||
+ sfifo_precon_err_sum ||
+ sfifo_esfinal_err_sum ||
+ es_ack_sm_err_sum ||
+ es_main_sm_err_sum);
+
+ // set fifo errors that are single instances of source
+ assign sfifo_esrng_err_sum = (|sfifo_esrng_err) ||
+ err_code_test_bit[0];
+ assign sfifo_precon_err_sum = (|sfifo_precon_err) ||
+ err_code_test_bit[1];
+ assign sfifo_esfinal_err_sum = (|sfifo_esfinal_err) ||
+ err_code_test_bit[2];
+ assign es_ack_sm_err_sum = es_ack_sm_err ||
+ err_code_test_bit[20];
+ assign es_main_sm_err_sum = es_main_sm_err ||
+ err_code_test_bit[21];
+ assign fifo_write_err_sum =
+ sfifo_esrng_err[2] ||
+ sfifo_precon_err[2] ||
+ sfifo_esfinal_err[2] ||
+ err_code_test_bit[28];
+ assign fifo_read_err_sum =
+ sfifo_esrng_err[1] ||
+ sfifo_precon_err[1] ||
+ sfifo_esfinal_err[1] ||
+ err_code_test_bit[29];
+ assign fifo_status_err_sum =
+ sfifo_esrng_err[0] ||
+ sfifo_precon_err[0] ||
+ sfifo_esfinal_err[0] ||
+ err_code_test_bit[30];
// set the err code source bits
assign hw2reg.err_code.sfifo_esrng_err.d = 1'b1;
- assign hw2reg.err_code.sfifo_esrng_err.de = es_enable && (|sfifo_esrng_err);
+ assign hw2reg.err_code.sfifo_esrng_err.de = es_enable && sfifo_esrng_err_sum;
assign hw2reg.err_code.sfifo_precon_err.d = 1'b1;
- assign hw2reg.err_code.sfifo_precon_err.de = es_enable && (|sfifo_precon_err);
+ assign hw2reg.err_code.sfifo_precon_err.de = es_enable && sfifo_precon_err_sum;
assign hw2reg.err_code.sfifo_esfinal_err.d = 1'b1;
- assign hw2reg.err_code.sfifo_esfinal_err.de = es_enable && (|sfifo_esfinal_err);
+ assign hw2reg.err_code.sfifo_esfinal_err.de = es_enable && sfifo_esfinal_err_sum;
+
+ assign hw2reg.err_code.es_ack_sm_err.d = 1'b1;
+ assign hw2reg.err_code.es_ack_sm_err.de = es_enable && es_ack_sm_err_sum;
+
+ assign hw2reg.err_code.es_main_sm_err.d = 1'b1;
+ assign hw2reg.err_code.es_main_sm_err.de = es_enable && es_main_sm_err_sum;
// set the err code type bits
assign hw2reg.err_code.fifo_write_err.d = 1'b1;
- assign hw2reg.err_code.fifo_write_err.de = es_enable && (
- sfifo_esrng_err[2] ||
- sfifo_precon_err[2] ||
- sfifo_esfinal_err[2]);
+ assign hw2reg.err_code.fifo_write_err.de = es_enable && fifo_write_err_sum;
assign hw2reg.err_code.fifo_read_err.d = 1'b1;
- assign hw2reg.err_code.fifo_read_err.de = es_enable && (
- sfifo_esrng_err[1] ||
- sfifo_precon_err[1] ||
- sfifo_esfinal_err[1]);
+ assign hw2reg.err_code.fifo_read_err.de = es_enable && fifo_read_err_sum;
assign hw2reg.err_code.fifo_state_err.d = 1'b1;
- assign hw2reg.err_code.fifo_state_err.de = es_enable && (
- sfifo_esrng_err[0] ||
- sfifo_precon_err[0] ||
- sfifo_esfinal_err[0]);
+ assign hw2reg.err_code.fifo_state_err.de = es_enable && fifo_status_err_sum;
+
+ // Error forcing
+ for (genvar i = 0; i < 31; i = i+1) begin : gen_err_code_test_bit
+ assign err_code_test_bit[i] = (reg2hw.err_code_test.q == i) && reg2hw.err_code_test.qe;
+ end : gen_err_code_test_bit
+
+ // alert - send all interrupt sources to the alert for the fatal case
+ assign fatal_alert_o = event_es_fatal_err;
+
+ // alert test
+ assign recov_alert_test_o = {
+ reg2hw.alert_test.recov_alert.q &&
+ reg2hw.alert_test.recov_alert.qe
+ };
+ assign fatal_alert_test_o = {
+ reg2hw.alert_test.fatal_alert.q &&
+ reg2hw.alert_test.fatal_alert.qe
+ };
// set the debug status reg
@@ -1101,10 +1158,7 @@
assign alert_threshold = reg2hw.alert_threshold.q;
assign recov_alert_event = (any_fail_count >= alert_threshold) && (alert_threshold != '0);
- assign recov_alert_event_o = recov_alert_event;
-
- // alert test
- assign alert_test_o = reg2hw.alert_test.qe && reg2hw.alert_test.q;
+ assign recov_alert_o = recov_alert_event;
// repcnt fail counter
@@ -1407,7 +1461,8 @@
.main_stage_rdy_i (pfifo_cond_not_empty),
.bypass_stage_rdy_i (pfifo_bypass_not_empty),
.main_stage_pop_o (main_stage_pop),
- .bypass_stage_pop_o (bypass_stage_pop)
+ .bypass_stage_pop_o (bypass_stage_pop),
+ .main_sm_err_o (es_main_sm_err)
);
@@ -1462,7 +1517,8 @@
.req_i (es_hw_if_req),
.ack_o (es_hw_if_ack),
.fifo_not_empty_i (sfifo_esfinal_not_empty && !es_route_to_sw),
- .fifo_pop_o (es_hw_if_fifo_pop)
+ .fifo_pop_o (es_hw_if_fifo_pop),
+ .ack_sm_err_o (es_ack_sm_err)
);
//--------------------------------------------
@@ -1499,6 +1555,8 @@
//--------------------------------------------
assign hw2reg.debug_status.diag.d =
+ (|err_code_test_bit[19:3]) ||
+ (|err_code_test_bit[27:22]) ||
reg2hw.regwen.q &&
(®2hw.entropy_data.q) &&
(®2hw.fw_ov_rd_data.q);
diff --git a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
index a944777..394b54a 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_main_sm.sv
@@ -20,34 +20,41 @@
input logic main_stage_rdy_i,
input logic bypass_stage_rdy_i,
output logic main_stage_pop_o,
- output logic bypass_stage_pop_o
+ output logic bypass_stage_pop_o,
+ output logic main_sm_err_o
);
- // Encoding generated with ./sparse-fsm-encode.py -d 3 -m 6 -n 8 -s 3348095039
- // Hamming distance histogram:
- //
- // 0: --
- // 1: --
- // 2: --
- // 3: |||||| (13.33%)
- // 4: |||||||||||||||| (33.33%)
- // 5: |||||||||||||||||||| (40.00%)
- // 6: |||||| (13.33%)
- // 7: --
- // 8: --
- //
- // Minimum Hamming distance: 3
- // Maximum Hamming distance: 6
- //
+// Encoding generated with:
+// $ ./util/design/sparse-fsm-encode.py -d 3 -m 7 -n 8 \
+// -s 373118154 --language=sv
+//
+// Hamming distance histogram:
+//
+// 0: --
+// 1: --
+// 2: --
+// 3: |||||||||||||||||||| (42.86%)
+// 4: ||||||||||||||| (33.33%)
+// 5: |||| (9.52%)
+// 6: |||| (9.52%)
+// 7: || (4.76%)
+// 8: --
+//
+// Minimum Hamming distance: 3
+// Maximum Hamming distance: 7
+// Minimum Hamming weight: 2
+// Maximum Hamming weight: 6
+//
localparam int StateWidth = 8;
typedef enum logic [StateWidth-1:0] {
- Idle = 8'b00011111, // idle
- HealthTestDone = 8'b01111010, // wait for health test done pulse
- PostHealthTestChk = 8'b11111001, // wait for post health test packer not empty state
- FlowModeChk = 8'b10110100, // determine what mode the flow is in
- BypassMode = 8'b00100011, // in bypass mode
- NormalMode = 8'b11001000 // in normal mode
+ Idle = 8'b01100010, // idle
+ HealthTestDone = 8'b00011101, // wait for health test done pulse
+ PostHealthTestChk = 8'b01001100, // wait for post health test packer not empty state
+ FlowModeChk = 8'b01110111, // determine what mode the flow is in
+ BypassMode = 8'b11011001, // in bypass mode
+ NormalMode = 8'b00000111, // in normal mode
+ Error = 8'b01000001 // illegal state reached and hang
} state_e;
state_e state_d, state_q;
@@ -74,6 +81,7 @@
rst_alert_cntr_o = 1'b0;
main_stage_pop_o = 1'b0;
bypass_stage_pop_o = 1'b0;
+ main_sm_err_o = 1'b0;
unique case (state_q)
Idle: begin
if (enable_i) begin
@@ -115,7 +123,10 @@
state_d = Idle;
end
end
- default: state_d = Idle;
+ Error: begin
+ main_sm_err_o = 1'b1;
+ end
+ default: state_d = Error;
endcase
end
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index 042c932..f1b6082 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -8,7 +8,7 @@
// Param list
parameter int EsFifoDepth = 32;
- parameter int NumAlerts = 1;
+ parameter int NumAlerts = 2;
// Address width within the block
parameter int BlockAw = 8;
@@ -25,7 +25,7 @@
} es_health_test_failed;
struct packed {
logic q;
- } es_fifo_err;
+ } es_fatal_err;
} entropy_src_reg2hw_intr_state_reg_t;
typedef struct packed {
@@ -37,7 +37,7 @@
} es_health_test_failed;
struct packed {
logic q;
- } es_fifo_err;
+ } es_fatal_err;
} entropy_src_reg2hw_intr_enable_reg_t;
typedef struct packed {
@@ -52,12 +52,18 @@
struct packed {
logic q;
logic qe;
- } es_fifo_err;
+ } es_fatal_err;
} entropy_src_reg2hw_intr_test_reg_t;
typedef struct packed {
- logic q;
- logic qe;
+ struct packed {
+ logic q;
+ logic qe;
+ } recov_alert;
+ struct packed {
+ logic q;
+ logic qe;
+ } fatal_alert;
} entropy_src_reg2hw_alert_test_reg_t;
typedef struct packed {
@@ -230,6 +236,11 @@
logic [3:0] q;
} entropy_src_reg2hw_seed_reg_t;
+ typedef struct packed {
+ logic [4:0] q;
+ logic qe;
+ } entropy_src_reg2hw_err_code_test_reg_t;
+
typedef struct packed {
struct packed {
@@ -243,7 +254,7 @@
struct packed {
logic d;
logic de;
- } es_fifo_err;
+ } es_fatal_err;
} entropy_src_hw2reg_intr_state_reg_t;
typedef struct packed {
@@ -420,6 +431,14 @@
struct packed {
logic d;
logic de;
+ } es_ack_sm_err;
+ struct packed {
+ logic d;
+ logic de;
+ } es_main_sm_err;
+ struct packed {
+ logic d;
+ logic de;
} fifo_write_err;
struct packed {
logic d;
@@ -436,60 +455,61 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [449:447]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [446:444]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [443:438]
- entropy_src_reg2hw_alert_test_reg_t alert_test; // [437:436]
- entropy_src_reg2hw_regwen_reg_t regwen; // [435:435]
- entropy_src_reg2hw_conf_reg_t conf; // [434:423]
- entropy_src_reg2hw_rate_reg_t rate; // [422:407]
- entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [406:405]
- entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [404:372]
- entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [371:340]
- entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [339:308]
- entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [307:276]
- entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [275:244]
- entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [243:212]
- entropy_src_reg2hw_markov_hi_thresholds_reg_t markov_hi_thresholds; // [211:180]
- entropy_src_reg2hw_markov_lo_thresholds_reg_t markov_lo_thresholds; // [179:148]
- entropy_src_reg2hw_extht_hi_thresholds_reg_t extht_hi_thresholds; // [147:116]
- entropy_src_reg2hw_extht_lo_thresholds_reg_t extht_lo_thresholds; // [115:84]
- entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [83:80]
- entropy_src_reg2hw_fw_ov_control_reg_t fw_ov_control; // [79:77]
- entropy_src_reg2hw_fw_ov_rd_data_reg_t fw_ov_rd_data; // [76:44]
- entropy_src_reg2hw_fw_ov_wr_data_reg_t fw_ov_wr_data; // [43:11]
- entropy_src_reg2hw_pre_cond_fifo_depth_reg_t pre_cond_fifo_depth; // [10:4]
- entropy_src_reg2hw_seed_reg_t seed; // [3:0]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [457:455]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [454:452]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [451:446]
+ entropy_src_reg2hw_alert_test_reg_t alert_test; // [445:442]
+ entropy_src_reg2hw_regwen_reg_t regwen; // [441:441]
+ entropy_src_reg2hw_conf_reg_t conf; // [440:429]
+ entropy_src_reg2hw_rate_reg_t rate; // [428:413]
+ entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [412:411]
+ entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [410:378]
+ entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [377:346]
+ entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [345:314]
+ entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [313:282]
+ entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [281:250]
+ entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [249:218]
+ entropy_src_reg2hw_markov_hi_thresholds_reg_t markov_hi_thresholds; // [217:186]
+ entropy_src_reg2hw_markov_lo_thresholds_reg_t markov_lo_thresholds; // [185:154]
+ entropy_src_reg2hw_extht_hi_thresholds_reg_t extht_hi_thresholds; // [153:122]
+ entropy_src_reg2hw_extht_lo_thresholds_reg_t extht_lo_thresholds; // [121:90]
+ entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [89:86]
+ entropy_src_reg2hw_fw_ov_control_reg_t fw_ov_control; // [85:83]
+ entropy_src_reg2hw_fw_ov_rd_data_reg_t fw_ov_rd_data; // [82:50]
+ entropy_src_reg2hw_fw_ov_wr_data_reg_t fw_ov_wr_data; // [49:17]
+ entropy_src_reg2hw_pre_cond_fifo_depth_reg_t pre_cond_fifo_depth; // [16:10]
+ entropy_src_reg2hw_seed_reg_t seed; // [9:6]
+ entropy_src_reg2hw_err_code_test_reg_t err_code_test; // [5:0]
} entropy_src_reg2hw_t;
///////////////////////////////////////
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- entropy_src_hw2reg_intr_state_reg_t intr_state; // [639:634]
- entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [633:602]
- entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [601:570]
- entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [569:538]
- entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [537:506]
- entropy_src_hw2reg_extht_hi_watermarks_reg_t extht_hi_watermarks; // [505:474]
- entropy_src_hw2reg_extht_lo_watermarks_reg_t extht_lo_watermarks; // [473:442]
- entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [441:410]
- entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [409:378]
- entropy_src_hw2reg_markov_lo_watermarks_reg_t markov_lo_watermarks; // [377:346]
- entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [345:314]
- entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [313:282]
- entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [281:250]
- entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [249:218]
- entropy_src_hw2reg_markov_hi_total_fails_reg_t markov_hi_total_fails; // [217:186]
- entropy_src_hw2reg_markov_lo_total_fails_reg_t markov_lo_total_fails; // [185:154]
- entropy_src_hw2reg_extht_hi_total_fails_reg_t extht_hi_total_fails; // [153:122]
- entropy_src_hw2reg_extht_lo_total_fails_reg_t extht_lo_total_fails; // [121:90]
- entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [89:62]
- entropy_src_hw2reg_extht_fail_counts_reg_t extht_fail_counts; // [61:54]
- entropy_src_hw2reg_fw_ov_rd_data_reg_t fw_ov_rd_data; // [53:22]
- entropy_src_hw2reg_fw_ov_fifo_sts_reg_t fw_ov_fifo_sts; // [21:15]
- entropy_src_hw2reg_debug_status_reg_t debug_status; // [14:12]
- entropy_src_hw2reg_err_code_reg_t err_code; // [11:0]
+ entropy_src_hw2reg_intr_state_reg_t intr_state; // [643:638]
+ entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [637:606]
+ entropy_src_hw2reg_repcnt_hi_watermarks_reg_t repcnt_hi_watermarks; // [605:574]
+ entropy_src_hw2reg_adaptp_hi_watermarks_reg_t adaptp_hi_watermarks; // [573:542]
+ entropy_src_hw2reg_adaptp_lo_watermarks_reg_t adaptp_lo_watermarks; // [541:510]
+ entropy_src_hw2reg_extht_hi_watermarks_reg_t extht_hi_watermarks; // [509:478]
+ entropy_src_hw2reg_extht_lo_watermarks_reg_t extht_lo_watermarks; // [477:446]
+ entropy_src_hw2reg_bucket_hi_watermarks_reg_t bucket_hi_watermarks; // [445:414]
+ entropy_src_hw2reg_markov_hi_watermarks_reg_t markov_hi_watermarks; // [413:382]
+ entropy_src_hw2reg_markov_lo_watermarks_reg_t markov_lo_watermarks; // [381:350]
+ entropy_src_hw2reg_repcnt_total_fails_reg_t repcnt_total_fails; // [349:318]
+ entropy_src_hw2reg_adaptp_hi_total_fails_reg_t adaptp_hi_total_fails; // [317:286]
+ entropy_src_hw2reg_adaptp_lo_total_fails_reg_t adaptp_lo_total_fails; // [285:254]
+ entropy_src_hw2reg_bucket_total_fails_reg_t bucket_total_fails; // [253:222]
+ entropy_src_hw2reg_markov_hi_total_fails_reg_t markov_hi_total_fails; // [221:190]
+ entropy_src_hw2reg_markov_lo_total_fails_reg_t markov_lo_total_fails; // [189:158]
+ entropy_src_hw2reg_extht_hi_total_fails_reg_t extht_hi_total_fails; // [157:126]
+ entropy_src_hw2reg_extht_lo_total_fails_reg_t extht_lo_total_fails; // [125:94]
+ entropy_src_hw2reg_alert_fail_counts_reg_t alert_fail_counts; // [93:66]
+ entropy_src_hw2reg_extht_fail_counts_reg_t extht_fail_counts; // [65:58]
+ entropy_src_hw2reg_fw_ov_rd_data_reg_t fw_ov_rd_data; // [57:26]
+ entropy_src_hw2reg_fw_ov_fifo_sts_reg_t fw_ov_fifo_sts; // [25:19]
+ entropy_src_hw2reg_debug_status_reg_t debug_status; // [18:16]
+ entropy_src_hw2reg_err_code_reg_t err_code; // [15:0]
} entropy_src_hw2reg_t;
// Register Address
@@ -539,14 +559,16 @@
parameter logic [BlockAw-1:0] ENTROPY_SRC_DEBUG_STATUS_OFFSET = 8'h ac;
parameter logic [BlockAw-1:0] ENTROPY_SRC_SEED_OFFSET = 8'h b0;
parameter logic [BlockAw-1:0] ENTROPY_SRC_ERR_CODE_OFFSET = 8'h b4;
+ parameter logic [BlockAw-1:0] ENTROPY_SRC_ERR_CODE_TEST_OFFSET = 8'h b8;
// Reset values for hwext registers and their fields
parameter logic [2:0] ENTROPY_SRC_INTR_TEST_RESVAL = 3'h 0;
parameter logic [0:0] ENTROPY_SRC_INTR_TEST_ES_ENTROPY_VALID_RESVAL = 1'h 0;
parameter logic [0:0] ENTROPY_SRC_INTR_TEST_ES_HEALTH_TEST_FAILED_RESVAL = 1'h 0;
- parameter logic [0:0] ENTROPY_SRC_INTR_TEST_ES_FIFO_ERR_RESVAL = 1'h 0;
- parameter logic [0:0] ENTROPY_SRC_ALERT_TEST_RESVAL = 1'h 0;
- parameter logic [0:0] ENTROPY_SRC_ALERT_TEST_RECOV_ALERT_COUNT_MET_RESVAL = 1'h 0;
+ parameter logic [0:0] ENTROPY_SRC_INTR_TEST_ES_FATAL_ERR_RESVAL = 1'h 0;
+ parameter logic [1:0] ENTROPY_SRC_ALERT_TEST_RESVAL = 2'h 0;
+ parameter logic [0:0] ENTROPY_SRC_ALERT_TEST_RECOV_ALERT_RESVAL = 1'h 0;
+ parameter logic [0:0] ENTROPY_SRC_ALERT_TEST_FATAL_ALERT_RESVAL = 1'h 0;
parameter logic [31:0] ENTROPY_SRC_ENTROPY_DATA_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_REPCNT_HI_WATERMARKS_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_ADAPTP_HI_WATERMARKS_RESVAL = 32'h 0;
@@ -618,11 +640,12 @@
ENTROPY_SRC_PRE_COND_FIFO_DEPTH,
ENTROPY_SRC_DEBUG_STATUS,
ENTROPY_SRC_SEED,
- ENTROPY_SRC_ERR_CODE
+ ENTROPY_SRC_ERR_CODE,
+ ENTROPY_SRC_ERR_CODE_TEST
} entropy_src_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ENTROPY_SRC_PERMIT [46] = '{
+ parameter logic [3:0] ENTROPY_SRC_PERMIT [47] = '{
4'b 0001, // index[ 0] ENTROPY_SRC_INTR_STATE
4'b 0001, // index[ 1] ENTROPY_SRC_INTR_ENABLE
4'b 0001, // index[ 2] ENTROPY_SRC_INTR_TEST
@@ -668,7 +691,8 @@
4'b 0001, // index[42] ENTROPY_SRC_PRE_COND_FIFO_DEPTH
4'b 1111, // index[43] ENTROPY_SRC_DEBUG_STATUS
4'b 0001, // index[44] ENTROPY_SRC_SEED
- 4'b 1111 // index[45] ENTROPY_SRC_ERR_CODE
+ 4'b 1111, // index[45] ENTROPY_SRC_ERR_CODE
+ 4'b 0001 // index[46] ENTROPY_SRC_ERR_CODE_TEST
};
endpackage
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index 94c041f..6d97ead 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -77,26 +77,28 @@
logic intr_state_es_health_test_failed_qs;
logic intr_state_es_health_test_failed_wd;
logic intr_state_es_health_test_failed_we;
- logic intr_state_es_fifo_err_qs;
- logic intr_state_es_fifo_err_wd;
- logic intr_state_es_fifo_err_we;
+ logic intr_state_es_fatal_err_qs;
+ logic intr_state_es_fatal_err_wd;
+ logic intr_state_es_fatal_err_we;
logic intr_enable_es_entropy_valid_qs;
logic intr_enable_es_entropy_valid_wd;
logic intr_enable_es_entropy_valid_we;
logic intr_enable_es_health_test_failed_qs;
logic intr_enable_es_health_test_failed_wd;
logic intr_enable_es_health_test_failed_we;
- logic intr_enable_es_fifo_err_qs;
- logic intr_enable_es_fifo_err_wd;
- logic intr_enable_es_fifo_err_we;
+ logic intr_enable_es_fatal_err_qs;
+ logic intr_enable_es_fatal_err_wd;
+ logic intr_enable_es_fatal_err_we;
logic intr_test_es_entropy_valid_wd;
logic intr_test_es_entropy_valid_we;
logic intr_test_es_health_test_failed_wd;
logic intr_test_es_health_test_failed_we;
- logic intr_test_es_fifo_err_wd;
- logic intr_test_es_fifo_err_we;
- logic alert_test_wd;
- logic alert_test_we;
+ logic intr_test_es_fatal_err_wd;
+ logic intr_test_es_fatal_err_we;
+ logic alert_test_recov_alert_wd;
+ logic alert_test_recov_alert_we;
+ logic alert_test_fatal_alert_wd;
+ logic alert_test_fatal_alert_we;
logic regwen_qs;
logic regwen_wd;
logic regwen_we;
@@ -293,23 +295,16 @@
logic [3:0] seed_wd;
logic seed_we;
logic err_code_sfifo_esrng_err_qs;
- logic err_code_sfifo_esrng_err_wd;
- logic err_code_sfifo_esrng_err_we;
logic err_code_sfifo_precon_err_qs;
- logic err_code_sfifo_precon_err_wd;
- logic err_code_sfifo_precon_err_we;
logic err_code_sfifo_esfinal_err_qs;
- logic err_code_sfifo_esfinal_err_wd;
- logic err_code_sfifo_esfinal_err_we;
+ logic err_code_es_ack_sm_err_qs;
+ logic err_code_es_main_sm_err_qs;
logic err_code_fifo_write_err_qs;
- logic err_code_fifo_write_err_wd;
- logic err_code_fifo_write_err_we;
logic err_code_fifo_read_err_qs;
- logic err_code_fifo_read_err_wd;
- logic err_code_fifo_read_err_we;
logic err_code_fifo_state_err_qs;
- logic err_code_fifo_state_err_wd;
- logic err_code_fifo_state_err_we;
+ logic [4:0] err_code_test_qs;
+ logic [4:0] err_code_test_wd;
+ logic err_code_test_we;
// Register instances
// R[intr_state]: V(False)
@@ -366,29 +361,29 @@
);
- // F[es_fifo_err]: 2:2
+ // F[es_fatal_err]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
- ) u_intr_state_es_fifo_err (
+ ) u_intr_state_es_fatal_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_state_es_fifo_err_we),
- .wd (intr_state_es_fifo_err_wd),
+ .we (intr_state_es_fatal_err_we),
+ .wd (intr_state_es_fatal_err_wd),
// from internal hardware
- .de (hw2reg.intr_state.es_fifo_err.de),
- .d (hw2reg.intr_state.es_fifo_err.d ),
+ .de (hw2reg.intr_state.es_fatal_err.de),
+ .d (hw2reg.intr_state.es_fatal_err.d ),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.es_fifo_err.q ),
+ .q (reg2hw.intr_state.es_fatal_err.q ),
// to register interface (read)
- .qs (intr_state_es_fifo_err_qs)
+ .qs (intr_state_es_fatal_err_qs)
);
@@ -446,18 +441,18 @@
);
- // F[es_fifo_err]: 2:2
+ // F[es_fatal_err]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_intr_enable_es_fifo_err (
+ ) u_intr_enable_es_fatal_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_enable_es_fifo_err_we),
- .wd (intr_enable_es_fifo_err_wd),
+ .we (intr_enable_es_fatal_err_we),
+ .wd (intr_enable_es_fatal_err_wd),
// from internal hardware
.de (1'b0),
@@ -465,10 +460,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.es_fifo_err.q ),
+ .q (reg2hw.intr_enable.es_fatal_err.q ),
// to register interface (read)
- .qs (intr_enable_es_fifo_err_qs)
+ .qs (intr_enable_es_fatal_err_qs)
);
@@ -504,33 +499,49 @@
);
- // F[es_fifo_err]: 2:2
+ // F[es_fatal_err]: 2:2
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_es_fifo_err (
+ ) u_intr_test_es_fatal_err (
.re (1'b0),
- .we (intr_test_es_fifo_err_we),
- .wd (intr_test_es_fifo_err_wd),
+ .we (intr_test_es_fatal_err_we),
+ .wd (intr_test_es_fatal_err_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.es_fifo_err.qe),
- .q (reg2hw.intr_test.es_fifo_err.q ),
+ .qe (reg2hw.intr_test.es_fatal_err.qe),
+ .q (reg2hw.intr_test.es_fatal_err.q ),
.qs ()
);
// R[alert_test]: V(True)
+ // F[recov_alert]: 0:0
prim_subreg_ext #(
.DW (1)
- ) u_alert_test (
+ ) u_alert_test_recov_alert (
.re (1'b0),
- .we (alert_test_we),
- .wd (alert_test_wd),
+ .we (alert_test_recov_alert_we),
+ .wd (alert_test_recov_alert_wd),
.d ('0),
.qre (),
- .qe (reg2hw.alert_test.qe),
- .q (reg2hw.alert_test.q ),
+ .qe (reg2hw.alert_test.recov_alert.qe),
+ .q (reg2hw.alert_test.recov_alert.q ),
+ .qs ()
+ );
+
+
+ // F[fatal_alert]: 1:1
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test_fatal_alert (
+ .re (1'b0),
+ .we (alert_test_fatal_alert_we),
+ .wd (alert_test_fatal_alert_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.fatal_alert.qe),
+ .q (reg2hw.alert_test.fatal_alert.q ),
.qs ()
);
@@ -2193,15 +2204,14 @@
// F[sfifo_esrng_err]: 0:0
prim_subreg #(
.DW (1),
- .SWACCESS("RW"),
+ .SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_esrng_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (err_code_sfifo_esrng_err_we),
- .wd (err_code_sfifo_esrng_err_wd),
+ .we (1'b0),
+ .wd ('0 ),
// from internal hardware
.de (hw2reg.err_code.sfifo_esrng_err.de),
@@ -2219,15 +2229,14 @@
// F[sfifo_precon_err]: 1:1
prim_subreg #(
.DW (1),
- .SWACCESS("RW"),
+ .SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_precon_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (err_code_sfifo_precon_err_we),
- .wd (err_code_sfifo_precon_err_wd),
+ .we (1'b0),
+ .wd ('0 ),
// from internal hardware
.de (hw2reg.err_code.sfifo_precon_err.de),
@@ -2245,15 +2254,14 @@
// F[sfifo_esfinal_err]: 2:2
prim_subreg #(
.DW (1),
- .SWACCESS("RW"),
+ .SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_sfifo_esfinal_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (err_code_sfifo_esfinal_err_we),
- .wd (err_code_sfifo_esfinal_err_wd),
+ .we (1'b0),
+ .wd ('0 ),
// from internal hardware
.de (hw2reg.err_code.sfifo_esfinal_err.de),
@@ -2268,18 +2276,67 @@
);
+ // F[es_ack_sm_err]: 20:20
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_err_code_es_ack_sm_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.err_code.es_ack_sm_err.de),
+ .d (hw2reg.err_code.es_ack_sm_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_es_ack_sm_err_qs)
+ );
+
+
+ // F[es_main_sm_err]: 21:21
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_err_code_es_main_sm_err (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.err_code.es_main_sm_err.de),
+ .d (hw2reg.err_code.es_main_sm_err.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (err_code_es_main_sm_err_qs)
+ );
+
+
// F[fifo_write_err]: 28:28
prim_subreg #(
.DW (1),
- .SWACCESS("RW"),
+ .SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_write_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (err_code_fifo_write_err_we),
- .wd (err_code_fifo_write_err_wd),
+ .we (1'b0),
+ .wd ('0 ),
// from internal hardware
.de (hw2reg.err_code.fifo_write_err.de),
@@ -2297,15 +2354,14 @@
// F[fifo_read_err]: 29:29
prim_subreg #(
.DW (1),
- .SWACCESS("RW"),
+ .SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_read_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (err_code_fifo_read_err_we),
- .wd (err_code_fifo_read_err_wd),
+ .we (1'b0),
+ .wd ('0 ),
// from internal hardware
.de (hw2reg.err_code.fifo_read_err.de),
@@ -2323,15 +2379,14 @@
// F[fifo_state_err]: 30:30
prim_subreg #(
.DW (1),
- .SWACCESS("RW"),
+ .SWACCESS("RO"),
.RESVAL (1'h0)
) u_err_code_fifo_state_err (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (err_code_fifo_state_err_we),
- .wd (err_code_fifo_state_err_wd),
+ .we (1'b0),
+ .wd ('0 ),
// from internal hardware
.de (hw2reg.err_code.fifo_state_err.de),
@@ -2346,9 +2401,36 @@
);
+ // R[err_code_test]: V(False)
+
+ prim_subreg #(
+ .DW (5),
+ .SWACCESS("RW"),
+ .RESVAL (5'h0)
+ ) u_err_code_test (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (err_code_test_we & regwen_qs),
+ .wd (err_code_test_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.err_code_test.qe),
+ .q (reg2hw.err_code_test.q ),
+
+ // to register interface (read)
+ .qs (err_code_test_qs)
+ );
- logic [45:0] addr_hit;
+
+
+ logic [46:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ENTROPY_SRC_INTR_STATE_OFFSET);
@@ -2397,6 +2479,7 @@
addr_hit[43] = (reg_addr == ENTROPY_SRC_DEBUG_STATUS_OFFSET);
addr_hit[44] = (reg_addr == ENTROPY_SRC_SEED_OFFSET);
addr_hit[45] = (reg_addr == ENTROPY_SRC_ERR_CODE_OFFSET);
+ addr_hit[46] = (reg_addr == ENTROPY_SRC_ERR_CODE_TEST_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -2450,6 +2533,7 @@
if (addr_hit[43] && reg_we && (ENTROPY_SRC_PERMIT[43] != (ENTROPY_SRC_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[44] && reg_we && (ENTROPY_SRC_PERMIT[44] != (ENTROPY_SRC_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[45] && reg_we && (ENTROPY_SRC_PERMIT[45] != (ENTROPY_SRC_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[46] && reg_we && (ENTROPY_SRC_PERMIT[46] != (ENTROPY_SRC_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_es_entropy_valid_we = addr_hit[0] & reg_we & ~wr_err;
@@ -2458,8 +2542,8 @@
assign intr_state_es_health_test_failed_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_es_health_test_failed_wd = reg_wdata[1];
- assign intr_state_es_fifo_err_we = addr_hit[0] & reg_we & ~wr_err;
- assign intr_state_es_fifo_err_wd = reg_wdata[2];
+ assign intr_state_es_fatal_err_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_es_fatal_err_wd = reg_wdata[2];
assign intr_enable_es_entropy_valid_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_es_entropy_valid_wd = reg_wdata[0];
@@ -2467,8 +2551,8 @@
assign intr_enable_es_health_test_failed_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_es_health_test_failed_wd = reg_wdata[1];
- assign intr_enable_es_fifo_err_we = addr_hit[1] & reg_we & ~wr_err;
- assign intr_enable_es_fifo_err_wd = reg_wdata[2];
+ assign intr_enable_es_fatal_err_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_es_fatal_err_wd = reg_wdata[2];
assign intr_test_es_entropy_valid_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_es_entropy_valid_wd = reg_wdata[0];
@@ -2476,11 +2560,14 @@
assign intr_test_es_health_test_failed_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_es_health_test_failed_wd = reg_wdata[1];
- assign intr_test_es_fifo_err_we = addr_hit[2] & reg_we & ~wr_err;
- assign intr_test_es_fifo_err_wd = reg_wdata[2];
+ assign intr_test_es_fatal_err_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_es_fatal_err_wd = reg_wdata[2];
- assign alert_test_we = addr_hit[3] & reg_we & ~wr_err;
- assign alert_test_wd = reg_wdata[0];
+ assign alert_test_recov_alert_we = addr_hit[3] & reg_we & ~wr_err;
+ assign alert_test_recov_alert_wd = reg_wdata[0];
+
+ assign alert_test_fatal_alert_we = addr_hit[3] & reg_we & ~wr_err;
+ assign alert_test_fatal_alert_wd = reg_wdata[1];
assign regwen_we = addr_hit[4] & reg_we & ~wr_err;
assign regwen_wd = reg_wdata[0];
@@ -2678,23 +2765,16 @@
assign seed_we = addr_hit[44] & reg_we & ~wr_err;
assign seed_wd = reg_wdata[3:0];
- assign err_code_sfifo_esrng_err_we = addr_hit[45] & reg_we & ~wr_err;
- assign err_code_sfifo_esrng_err_wd = reg_wdata[0];
- assign err_code_sfifo_precon_err_we = addr_hit[45] & reg_we & ~wr_err;
- assign err_code_sfifo_precon_err_wd = reg_wdata[1];
- assign err_code_sfifo_esfinal_err_we = addr_hit[45] & reg_we & ~wr_err;
- assign err_code_sfifo_esfinal_err_wd = reg_wdata[2];
- assign err_code_fifo_write_err_we = addr_hit[45] & reg_we & ~wr_err;
- assign err_code_fifo_write_err_wd = reg_wdata[28];
- assign err_code_fifo_read_err_we = addr_hit[45] & reg_we & ~wr_err;
- assign err_code_fifo_read_err_wd = reg_wdata[29];
- assign err_code_fifo_state_err_we = addr_hit[45] & reg_we & ~wr_err;
- assign err_code_fifo_state_err_wd = reg_wdata[30];
+
+
+
+ assign err_code_test_we = addr_hit[46] & reg_we & ~wr_err;
+ assign err_code_test_wd = reg_wdata[4:0];
// Read data return
always_comb begin
@@ -2703,13 +2783,13 @@
addr_hit[0]: begin
reg_rdata_next[0] = intr_state_es_entropy_valid_qs;
reg_rdata_next[1] = intr_state_es_health_test_failed_qs;
- reg_rdata_next[2] = intr_state_es_fifo_err_qs;
+ reg_rdata_next[2] = intr_state_es_fatal_err_qs;
end
addr_hit[1]: begin
reg_rdata_next[0] = intr_enable_es_entropy_valid_qs;
reg_rdata_next[1] = intr_enable_es_health_test_failed_qs;
- reg_rdata_next[2] = intr_enable_es_fifo_err_qs;
+ reg_rdata_next[2] = intr_enable_es_fatal_err_qs;
end
addr_hit[2]: begin
@@ -2720,6 +2800,7 @@
addr_hit[3]: begin
reg_rdata_next[0] = '0;
+ reg_rdata_next[1] = '0;
end
addr_hit[4]: begin
@@ -2929,11 +3010,17 @@
reg_rdata_next[0] = err_code_sfifo_esrng_err_qs;
reg_rdata_next[1] = err_code_sfifo_precon_err_qs;
reg_rdata_next[2] = err_code_sfifo_esfinal_err_qs;
+ reg_rdata_next[20] = err_code_es_ack_sm_err_qs;
+ reg_rdata_next[21] = err_code_es_main_sm_err_qs;
reg_rdata_next[28] = err_code_fifo_write_err_qs;
reg_rdata_next[29] = err_code_fifo_read_err_qs;
reg_rdata_next[30] = err_code_fifo_state_err_qs;
end
+ addr_hit[46]: begin
+ reg_rdata_next[4:0] = err_code_test_qs;
+ end
+
default: begin
reg_rdata_next = '1;
end
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index b230507..14703d7 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -6459,7 +6459,7 @@
type: interrupt
}
{
- name: es_fifo_err
+ name: es_fatal_err
width: 1
bits: "2"
bitinfo:
@@ -6474,7 +6474,7 @@
alert_list:
[
{
- name: recov_alert_count_met
+ name: recov_alert
width: 1
bits: "0"
bitinfo:
@@ -6486,6 +6486,19 @@
type: alert
async: 1
}
+ {
+ name: fatal_alert
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: alert
+ async: 1
+ }
]
wakeup_list: []
reset_request_list: []
@@ -11162,7 +11175,7 @@
module_name: entropy_src
}
{
- name: entropy_src_es_fifo_err
+ name: entropy_src_es_fatal_err
width: 1
bits: "2"
bitinfo:
@@ -11430,7 +11443,7 @@
module_name: lc_ctrl
}
{
- name: entropy_src_recov_alert_count_met
+ name: entropy_src_recov_alert
width: 1
bits: "0"
bitinfo:
@@ -11444,6 +11457,20 @@
module_name: entropy_src
}
{
+ name: entropy_src_fatal_alert
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: alert
+ async: 1
+ module_name: entropy_src
+ }
+ {
name: csrng_fatal_alert
width: 1
bits: "0"
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 2ecf2cd..621bf91 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -22,9 +22,10 @@
assign alert_if[15].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
assign alert_if[17].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
diff --git a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
index c66641a..10d9659 100644
--- a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
@@ -22,7 +22,8 @@
"otp_ctrl_fatal_check_error",
"lc_ctrl_fatal_prog_error",
"lc_ctrl_fatal_state_error",
- "entropy_src_recov_alert_count_met",
+ "entropy_src_recov_alert",
+ "entropy_src_fatal_alert",
"csrng_fatal_alert",
"sram_ctrl_main_fatal_parity_error",
"sram_ctrl_ret_aon_fatal_parity_error",
@@ -31,4 +32,4 @@
"flash_ctrl_recov_ecc_err"
};
-parameter uint NUM_ALERTS = 24;
+parameter uint NUM_ALERTS = 25;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 7e71e54..07aa720 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -46,7 +46,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "24",
+ default: "25",
local: "true"
},
{ name: "EscCntDw",
@@ -64,7 +64,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "24'b111011100001100000001111",
+ default: "25'b1110111100001100000001111",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
index 2dfb5b7..9078ec7 100644
--- a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
@@ -10,5 +10,5 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-parameter uint NUM_ALERTS = 24;
-parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 24'b111011100001100000001111;
+parameter uint NUM_ALERTS = 25;
+parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 25'b1110111100001100000001111;
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index be2025f..c27c6ad 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 24;
+ parameter int NAlerts = 25;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
- parameter logic [NAlerts-1:0] AsyncOn = 24'b111011100001100000001111;
+ parameter logic [NAlerts-1:0] AsyncOn = 25'b1110111100001100000001111;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -457,14 +457,14 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [920:917]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [916:913]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [912:905]
- alert_handler_reg2hw_regwen_reg_t regwen; // [904:904]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [903:880]
- alert_handler_reg2hw_alert_en_mreg_t [23:0] alert_en; // [879:856]
- alert_handler_reg2hw_alert_class_mreg_t [23:0] alert_class; // [855:808]
- alert_handler_reg2hw_alert_cause_mreg_t [23:0] alert_cause; // [807:784]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [924:921]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [920:917]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [916:909]
+ alert_handler_reg2hw_regwen_reg_t regwen; // [908:908]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [907:884]
+ alert_handler_reg2hw_alert_en_mreg_t [24:0] alert_en; // [883:859]
+ alert_handler_reg2hw_alert_class_mreg_t [24:0] alert_class; // [858:809]
+ alert_handler_reg2hw_alert_cause_mreg_t [24:0] alert_cause; // [808:784]
alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
@@ -506,8 +506,8 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [275:268]
- alert_handler_hw2reg_alert_cause_mreg_t [23:0] alert_cause; // [267:220]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [277:270]
+ alert_handler_hw2reg_alert_cause_mreg_t [24:0] alert_cause; // [269:220]
alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [219:212]
alert_handler_hw2reg_classa_regwen_reg_t classa_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -679,10 +679,10 @@
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
4'b 0001, // index[ 3] ALERT_HANDLER_REGWEN
4'b 0111, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC
- 4'b 0111, // index[ 5] ALERT_HANDLER_ALERT_EN
+ 4'b 1111, // index[ 5] ALERT_HANDLER_ALERT_EN
4'b 1111, // index[ 6] ALERT_HANDLER_ALERT_CLASS_0
- 4'b 0011, // index[ 7] ALERT_HANDLER_ALERT_CLASS_1
- 4'b 0111, // index[ 8] ALERT_HANDLER_ALERT_CAUSE
+ 4'b 0111, // index[ 7] ALERT_HANDLER_ALERT_CLASS_1
+ 4'b 1111, // index[ 8] ALERT_HANDLER_ALERT_CAUSE
4'b 0001, // index[ 9] ALERT_HANDLER_LOC_ALERT_EN
4'b 0001, // index[10] ALERT_HANDLER_LOC_ALERT_CLASS
4'b 0001, // index[11] ALERT_HANDLER_LOC_ALERT_CAUSE
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 2826e40..751a776 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -181,6 +181,9 @@
logic alert_en_en_a_23_qs;
logic alert_en_en_a_23_wd;
logic alert_en_en_a_23_we;
+ logic alert_en_en_a_24_qs;
+ logic alert_en_en_a_24_wd;
+ logic alert_en_en_a_24_we;
logic [1:0] alert_class_0_class_a_0_qs;
logic [1:0] alert_class_0_class_a_0_wd;
logic alert_class_0_class_a_0_we;
@@ -253,6 +256,9 @@
logic [1:0] alert_class_1_class_a_23_qs;
logic [1:0] alert_class_1_class_a_23_wd;
logic alert_class_1_class_a_23_we;
+ logic [1:0] alert_class_1_class_a_24_qs;
+ logic [1:0] alert_class_1_class_a_24_wd;
+ logic alert_class_1_class_a_24_we;
logic alert_cause_a_0_qs;
logic alert_cause_a_0_wd;
logic alert_cause_a_0_we;
@@ -325,6 +331,9 @@
logic alert_cause_a_23_qs;
logic alert_cause_a_23_wd;
logic alert_cause_a_23_we;
+ logic alert_cause_a_24_qs;
+ logic alert_cause_a_24_wd;
+ logic alert_cause_a_24_we;
logic loc_alert_en_en_la_0_qs;
logic loc_alert_en_en_la_0_wd;
logic loc_alert_en_en_la_0_we;
@@ -1555,6 +1564,32 @@
);
+ // F[en_a_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a_24 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a_24_we & regwen_qs),
+ .wd (alert_en_en_a_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[24].q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a_24_qs)
+ );
+
+
// Subregister 0 of Multireg alert_class
@@ -2187,6 +2222,32 @@
);
+ // F[class_a_24]: 17:16
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_1_class_a_24 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_1_class_a_24_we & regwen_qs),
+ .wd (alert_class_1_class_a_24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[24].q ),
+
+ // to register interface (read)
+ .qs (alert_class_1_class_a_24_qs)
+ );
+
+
// Subregister 0 of Multireg alert_cause
@@ -2816,6 +2877,32 @@
);
+ // F[a_24]: 24:24
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a_24 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a_24_we),
+ .wd (alert_cause_a_24_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[24].de),
+ .d (hw2reg.alert_cause[24].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[24].q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a_24_qs)
+ );
+
+
// Subregister 0 of Multireg loc_alert_en
@@ -5492,6 +5579,9 @@
assign alert_en_en_a_23_we = addr_hit[5] & reg_we & ~wr_err;
assign alert_en_en_a_23_wd = reg_wdata[23];
+ assign alert_en_en_a_24_we = addr_hit[5] & reg_we & ~wr_err;
+ assign alert_en_en_a_24_wd = reg_wdata[24];
+
assign alert_class_0_class_a_0_we = addr_hit[6] & reg_we & ~wr_err;
assign alert_class_0_class_a_0_wd = reg_wdata[1:0];
@@ -5564,6 +5654,9 @@
assign alert_class_1_class_a_23_we = addr_hit[7] & reg_we & ~wr_err;
assign alert_class_1_class_a_23_wd = reg_wdata[15:14];
+ assign alert_class_1_class_a_24_we = addr_hit[7] & reg_we & ~wr_err;
+ assign alert_class_1_class_a_24_wd = reg_wdata[17:16];
+
assign alert_cause_a_0_we = addr_hit[8] & reg_we & ~wr_err;
assign alert_cause_a_0_wd = reg_wdata[0];
@@ -5636,6 +5729,9 @@
assign alert_cause_a_23_we = addr_hit[8] & reg_we & ~wr_err;
assign alert_cause_a_23_wd = reg_wdata[23];
+ assign alert_cause_a_24_we = addr_hit[8] & reg_we & ~wr_err;
+ assign alert_cause_a_24_wd = reg_wdata[24];
+
assign loc_alert_en_en_la_0_we = addr_hit[9] & reg_we & ~wr_err;
assign loc_alert_en_en_la_0_wd = reg_wdata[0];
@@ -5970,6 +6066,7 @@
reg_rdata_next[21] = alert_en_en_a_21_qs;
reg_rdata_next[22] = alert_en_en_a_22_qs;
reg_rdata_next[23] = alert_en_en_a_23_qs;
+ reg_rdata_next[24] = alert_en_en_a_24_qs;
end
addr_hit[6]: begin
@@ -6000,6 +6097,7 @@
reg_rdata_next[11:10] = alert_class_1_class_a_21_qs;
reg_rdata_next[13:12] = alert_class_1_class_a_22_qs;
reg_rdata_next[15:14] = alert_class_1_class_a_23_qs;
+ reg_rdata_next[17:16] = alert_class_1_class_a_24_qs;
end
addr_hit[8]: begin
@@ -6027,6 +6125,7 @@
reg_rdata_next[21] = alert_cause_a_21_qs;
reg_rdata_next[22] = alert_cause_a_22_qs;
reg_rdata_next[23] = alert_cause_a_23_qs;
+ reg_rdata_next[24] = alert_cause_a_24_qs;
end
addr_hit[9]: begin
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index c5d5148..1329d52 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -370,7 +370,7 @@
logic intr_csrng_cs_fatal_err;
logic intr_entropy_src_es_entropy_valid;
logic intr_entropy_src_es_health_test_failed;
- logic intr_entropy_src_es_fifo_err;
+ logic intr_entropy_src_es_fatal_err;
logic intr_edn0_edn_cmd_req_done;
logic intr_edn0_edn_fifo_err;
logic intr_edn1_edn_cmd_req_done;
@@ -1915,11 +1915,12 @@
// Interrupt
.intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid),
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
- .intr_es_fifo_err_o (intr_entropy_src_es_fifo_err),
+ .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [20]: recov_alert_count_met
- .alert_tx_o ( alert_tx[20:20] ),
- .alert_rx_i ( alert_rx[20:20] ),
+ // [20]: recov_alert
+ // [21]: fatal_alert
+ .alert_tx_o ( alert_tx[21:20] ),
+ .alert_rx_i ( alert_rx[21:20] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -1981,9 +1982,9 @@
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [21]: fatal_parity_error
- .alert_tx_o ( alert_tx[21:21] ),
- .alert_rx_i ( alert_rx[21:21] ),
+ // [22]: fatal_parity_error
+ .alert_tx_o ( alert_tx[22:22] ),
+ .alert_rx_i ( alert_rx[22:22] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2011,10 +2012,10 @@
// Interrupt
.intr_done_o (intr_otbn_done),
- // [22]: fatal
- // [23]: recov
- .alert_tx_o ( alert_tx[23:22] ),
- .alert_rx_i ( alert_rx[23:22] ),
+ // [23]: fatal
+ // [24]: recov
+ .alert_tx_o ( alert_tx[24:23] ),
+ .alert_rx_i ( alert_rx[24:23] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[3]),
@@ -2028,7 +2029,7 @@
// interrupt assignments
assign intr_vector = {
- intr_entropy_src_es_fifo_err, // ID 139
+ intr_entropy_src_es_fatal_err, // ID 139
intr_entropy_src_es_health_test_failed, // ID 138
intr_entropy_src_es_entropy_valid, // ID 137
intr_aon_timer_aon_wdog_timer_bark, // ID 136
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index e0f692c..f0e28ef 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -182,7 +182,7 @@
[kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark] = kTopEarlgreyPlicPeripheralAonTimerAon,
[kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid] = kTopEarlgreyPlicPeripheralEntropySrc,
[kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed] = kTopEarlgreyPlicPeripheralEntropySrc,
- [kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr] = kTopEarlgreyPlicPeripheralEntropySrc,
+ [kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr] = kTopEarlgreyPlicPeripheralEntropySrc,
};
@@ -193,7 +193,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[24] = {
+ top_earlgrey_alert_for_peripheral[25] = {
[kTopEarlgreyAlertIdAesRecovCtrlUpdateErr] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn,
@@ -211,7 +211,8 @@
[kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl,
- [kTopEarlgreyAlertIdEntropySrcRecovAlertCountMet] = kTopEarlgreyAlertPeripheralEntropySrc,
+ [kTopEarlgreyAlertIdEntropySrcRecovAlert] = kTopEarlgreyAlertPeripheralEntropySrc,
+ [kTopEarlgreyAlertIdEntropySrcFatalAlert] = kTopEarlgreyAlertPeripheralEntropySrc,
[kTopEarlgreyAlertIdCsrngFatalAlert] = kTopEarlgreyAlertPeripheralCsrng,
[kTopEarlgreyAlertIdSramCtrlMainFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlMain,
[kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 72a9b0e..618fc93 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -927,7 +927,7 @@
kTopEarlgreyPlicIrqIdAonTimerAonWdogTimerBark = 167, /**< aon_timer_aon_wdog_timer_bark */
kTopEarlgreyPlicIrqIdEntropySrcEsEntropyValid = 168, /**< entropy_src_es_entropy_valid */
kTopEarlgreyPlicIrqIdEntropySrcEsHealthTestFailed = 169, /**< entropy_src_es_health_test_failed */
- kTopEarlgreyPlicIrqIdEntropySrcEsFifoErr = 170, /**< entropy_src_es_fifo_err */
+ kTopEarlgreyPlicIrqIdEntropySrcEsFatalErr = 170, /**< entropy_src_es_fatal_err */
kTopEarlgreyPlicIrqIdLast = 170, /**< \internal The Last Valid Interrupt ID. */
} top_earlgrey_plic_irq_id_t;
@@ -996,14 +996,15 @@
kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 14, /**< otp_ctrl_fatal_check_error */
kTopEarlgreyAlertIdLcCtrlFatalProgError = 15, /**< lc_ctrl_fatal_prog_error */
kTopEarlgreyAlertIdLcCtrlFatalStateError = 16, /**< lc_ctrl_fatal_state_error */
- kTopEarlgreyAlertIdEntropySrcRecovAlertCountMet = 17, /**< entropy_src_recov_alert_count_met */
- kTopEarlgreyAlertIdCsrngFatalAlert = 18, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 19, /**< sram_ctrl_main_fatal_parity_error */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 20, /**< sram_ctrl_ret_aon_fatal_parity_error */
- kTopEarlgreyAlertIdFlashCtrlRecovErr = 21, /**< flash_ctrl_recov_err */
- kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 22, /**< flash_ctrl_recov_mp_err */
- kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 23, /**< flash_ctrl_recov_ecc_err */
- kTopEarlgreyAlertIdLast = 23, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 17, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 18, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 19, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 20, /**< sram_ctrl_main_fatal_parity_error */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 21, /**< sram_ctrl_ret_aon_fatal_parity_error */
+ kTopEarlgreyAlertIdFlashCtrlRecovErr = 22, /**< flash_ctrl_recov_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 23, /**< flash_ctrl_recov_mp_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 24, /**< flash_ctrl_recov_ecc_err */
+ kTopEarlgreyAlertIdLast = 24, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1013,7 +1014,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[24];
+ top_earlgrey_alert_for_peripheral[25];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
