[top] Re-align English Breakfast top level with Earl Grey
This commit re-aligns the English Breakfast top level with Earl Grey
to make it functional again. Since this functional configuration no
longer fits the FPGA on the CW305 board, the following changes are
made in the English Breakfast top to reduce resource utilization:
- Remove the alert handler
- Disable some Ibex features (BT-ALU, WB-Stage).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc
index c919a57..8dd465a 100644
--- a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc
+++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc
@@ -22,7 +22,9 @@
"u_prim_ram_1p_adv.u_mem."
"gen_generic.u_impl_generic");
- MemArea rom(top_scope + ".u_rom_rom.u_prim_rom.gen_generic.u_impl_generic",
+ MemArea rom(top_scope +
+ ".u_rom_ctrl.gen_rom_scramble_disabled.u_rom."
+ "u_prim_rom.gen_generic.u_impl_generic",
0x4000 / 4, 4);
MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4,
4);
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index b55b564..2b6ee5e 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -154,7 +154,7 @@
{ name: "sys_io_div4", gen: true, type: "top", parent: "sys_src", clk: "io_div4" }
{ name: "sys_aon", gen: true, type: "top", parent: "sys_src", clk: "aon" }
{ name: "spi_device", gen: true, type: "top", parent: "sys_src", clk: "io_div2", sw: true }
- { name: "spi_host0", gen: true, type: "top", parent: "sys_src", clk: "io_div2", sw: true }
+ { name: "spi_host0", gen: true, type: "top", parent: "sys_src", clk: "io", sw: true }
{ name: "usb", gen: true, type: "top", parent: "sys_src", clk: "usb", sw: true }
]
}
@@ -162,11 +162,6 @@
// Number of cores: used in rv_plic and timer
num_cores: "1",
-
- // TODO: remove completely
- host: [
- ]
-
// `module` defines the peripherals.
// Details are coming from each modules' config file `ip.hjson`
// TODO: Define parameter here
@@ -209,7 +204,7 @@
},
{ name: "spi_host0",
type: "spi_host",
- clock_srcs: {clk_i: "io_div4", clk_core_i: "io_div2"},
+ clock_srcs: {clk_i: "io_div4", clk_core_i: "io"},
clock_group: "peri",
reset_connections: {rst_ni: "spi_host0", rst_core_ni: "spi_host0"},
base_addr: "0x40060000",
@@ -236,14 +231,6 @@
reset_connections: {rst_ni: "lc_io_div4", rst_kmac_ni: "sys"},
base_addr: "0x40140000",
},
- { name: "alert_handler",
- type: "alert_handler",
- clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"},
- clock_group: "timers",
- reset_connections: {rst_ni: "sys_io_div4", rst_edn_ni: "sys"},
- base_addr: "0x40150000",
- attr: "templated",
- },
{ name: "pwrmgr_aon",
type: "pwrmgr",
clock_srcs: {clk_i: "io_div4", clk_slow_i: "aon"},
@@ -308,16 +295,19 @@
clock_group: "infra",
reset_connections: {rst_ni: "sys_io_div4", rst_otp_ni: "lc_io_div4"},
domain: "Aon",
- base_addrs: {regs: "0x40500000", ram: "0x40600000"}
+ param_decl: {
+ InstrExec: "0",
+ }
+ base_addrs: {regs: "0x40500000", ram: "0x40600000"},
// Memory regions must be associated with a dedicated
// TL-UL device interface.
memory: {
ram: {
- label: "ram_ret_aon",
+ label: "ram_ret_aon",
swaccess: "rw",
exec: "True",
byte_write: "True",
- size: "0x1000"
+ size: "0x1000"
}
}
},
@@ -332,7 +322,7 @@
{ name: "rv_dm",
type: "rv_dm",
clock_srcs: {clk_i: "main"},
- clock_group: "secure",
+ clock_group: "infra",
reset_connections: {rst_ni: "lc"},
// Note that this module also contains a bus host.
base_addrs: {rom: "0x00010000", regs: "0x41200000"}
@@ -350,6 +340,10 @@
clock_srcs: {clk_i: "main", clk_edn_i: "main"},
clock_group: "trans",
reset_connections: {rst_ni: "sys", rst_edn_ni: "sys"},
+ param_decl: {
+ Masking: "1",
+ SBoxImpl: "aes_pkg::SBoxImplDom"
+ }
base_addr: "0x41100000",
},
{ name: "hmac",
@@ -364,7 +358,10 @@
clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"},
clock_group: "secure",
reset_connections: {rst_ni: "sys", rst_otp_ni: "lc_io_div4"},
- base_addrs: {regs: "0x411C0000", ram: "0x10000000"}
+ param_decl: {
+ InstrExec: "1",
+ }
+ base_addrs: {regs: "0x411C0000", ram: "0x10000000"},
// Memory regions must be associated with a dedicated
// TL-UL device interface.
memory: {
@@ -379,7 +376,6 @@
},
{ name: "rom_ctrl",
type: "rom_ctrl",
- param_decl: {SecDisableScrambling: "1'b1"},
clock_srcs: {clk_i: "main"},
clock_group: "infra",
reset_connections: {rst_ni: "sys"},
@@ -392,6 +388,9 @@
byte_write: "False",
size: "0x4000"
}
+ },
+ param_decl: {
+ SecDisableScrambling: "1'b1"
}
},
{ name: "rv_core_ibex",
@@ -412,8 +411,8 @@
BranchPredictor: "0",
DbgTriggerEn: "1",
SecureIbex: "1",
- DmHaltAddr: "ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0]",
- DmExceptionAddr: "ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0]",
+ DmHaltAddr: "tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::HaltAddress[31:0]",
+ DmExceptionAddr: "tl_main_pkg::ADDR_SPACE_RV_DM__ROM + dm::ExceptionAddress[31:0]",
PipeLine: "0"
}
clock_srcs: {clk_i: "main", clk_esc_i: "io_div4"},
@@ -423,7 +422,7 @@
},
]
- // Memories (RAM, eFlash) are defined at the top.
+ // Memories (ROM, RAM, eFlash) are defined at the top.
// It utilizes the primitive cells but configurable
memory: [
{ name: "eflash",
@@ -558,15 +557,6 @@
// e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
inter_module: {
'connect': {
- 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
- 'alert_handler.esc_rx' : ['rv_core_ibex.esc_rx',
- 'lc_ctrl.esc_scrap_state0_rx',
- 'lc_ctrl.esc_scrap_state1_rx'
- 'pwrmgr_aon.esc_rst_rx'],
- 'alert_handler.esc_tx' : ['rv_core_ibex.esc_tx',
- 'lc_ctrl.esc_scrap_state0_tx',
- 'lc_ctrl.esc_scrap_state1_tx',
- 'pwrmgr_aon.esc_rst_tx'],
'flash_ctrl.flash' : ['eflash.flash_ctrl'],
'flash_ctrl.rma_req' : ['lc_ctrl.lc_flash_rma_req'],
'flash_ctrl.rma_ack' : ['lc_ctrl.lc_flash_rma_ack'],
@@ -578,8 +568,7 @@
'pwrmgr_aon.strap' : ['pinmux_aon.strap_en'],
'pwrmgr_aon.low_power' : ['pinmux_aon.sleep_en',
'aon_timer_aon.sleep_mode'],
- 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
- 'rv_core_ibex.crash_dump' : ['rstmgr_aon.cpu_dump'],
+ 'pwrmgr_aon.fetch_en' : ['rv_core_ibex.pwrmgr_cpu_en'],
// usbdev connection to pinmux
'usbdev.usb_out_of_rst' : ['pinmux_aon.usb_out_of_rst'],
@@ -594,14 +583,13 @@
'clkmgr_aon.idle' : [],
// Pinmux JTAG signals
- // Note that the DFT TAP will be connected
- // automatically by the DFT insertion tool,
- // hence it does not have to be connected here.
'pinmux_aon.lc_jtag' : ['lc_ctrl.jtag'],
'pinmux_aon.rv_jtag' : ['rv_dm.jtag'],
// LC function control signal broadcast
- 'lc_ctrl.lc_dft_en' : ['pinmux_aon.lc_dft_en'],
+ 'lc_ctrl.lc_dft_en' : ['pinmux_aon.lc_dft_en',
+ 'clkmgr_aon.lc_dft_en'
+ ],
'lc_ctrl.lc_nvm_debug_en' : ['eflash.lc_nvm_debug_en'],
'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en',
'sram_ctrl_ret_aon.lc_hw_debug_en',
@@ -624,8 +612,23 @@
'lc_ctrl.lc_iso_part_sw_wr_en' : ['flash_ctrl.lc_iso_part_sw_wr_en'],
'lc_ctrl.lc_seed_hw_rd_en' : ['flash_ctrl.lc_seed_hw_rd_en'],
- // TODO: Put passthrough here?
- //'spi_device.passthrough': ['spi_host0.passthrough']
+ // rv_plic connections
+ 'rv_plic.msip' : ['rv_core_ibex.irq_software'],
+ 'rv_plic.irq' : ['rv_core_ibex.irq_external'],
+
+ // rv_dm connections
+ 'rv_dm.debug_req': ['rv_core_ibex.debug_req'],
+
+ // rv_timer connections
+
+
+ // rv core ibex connections
+ 'rv_core_ibex.rst_cpu_n' : ['rstmgr_aon.rst_cpu_n'],
+ 'rv_core_ibex.crash_dump' : ['rstmgr_aon.cpu_dump'],
+ 'rv_core_ibex.pwrmgr' : ['pwrmgr_aon.pwr_cpu'],
+
+ // spi passthrough connection
+ 'spi_device.passthrough' : ['spi_host0.passthrough']
// Debug module reset request to reset manager
'rv_dm.ndmreset_req' : ['rstmgr_aon.ndmreset_req']
@@ -635,20 +638,32 @@
// It defines the signal in the top and connect from the module,
// use of the signal is up to top template
'top': [
- 'rstmgr_aon.resets', 'rstmgr_aon.rst_cpu_n',
- 'pwrmgr_aon.pwr_cpu', 'pwrmgr_aon.fetch_en',
- 'clkmgr_aon.clocks',
+ // reset and clock connections
+ 'rstmgr_aon.resets', 'clkmgr_aon.clocks',
- // Debug request from debug module to CPU
- 'rv_dm.debug_req',
+ // dedicated timer interrupt
+ 'rv_core_ibex.irq_timer',
+
+ // hardwired connections
+ 'rv_core_ibex.hart_id', 'rv_core_ibex.boot_addr',
// Xbars
- 'main.tl_corei', 'main.tl_cored'
+
+ // Pinmux JTAG signals for the tool-inserted DFT TAP
+ 'pinmux_aon.dft_jtag',
+
+ // OTP HW_CFG Broadcast signals.
+ // TODO(#6713): The actual struct breakout and mapping currently needs to
+ // be performed by hand in the toplevel template.
+ 'lc_ctrl.otp_device_id',
+ 'lc_ctrl.otp_manuf_state',
+ 'sram_ctrl_main.otp_en_sram_ifetch',
+ 'sram_ctrl_ret_aon.otp_en_sram_ifetch'
],
// ext is to create port in the top.
'external': {
- // 'adc_ctrl_aon.adc' : 'adc'
+ # 'adc_ctrl_aon.adc' : 'adc'
'ast.edn' : '',
'ast.lc_dft_en' : '',
'ast.ram_1p_cfg' : 'ram_1p_cfg',
@@ -671,12 +686,14 @@
'pinmux_aon.dft_strap_test' : 'dft_strap_test'
'pinmux_aon.dft_hold_tap_sel' : 'dft_hold_tap_sel',
'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast',
- 'rstmgr_aon.por_n' : 'por_n'
# 'otp_ctrl.otp_ast_pwr_seq' : '',
# 'otp_ctrl.otp_ast_pwr_seq_h' : '',
+ # 'otp_ctrl.otp_alert' : 'otp_alert',
+ 'rstmgr_aon.por_n' : 'por_n'
'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert',
'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status',
'sensor_ctrl_aon.ast2pinmux' : '',
+ # 'sensor_ctrl_aon.ast_init_done': 'ast_init_done',
'usbdev.usb_ref_val' : '',
'usbdev.usb_ref_pulse' : '',
},
@@ -700,6 +717,20 @@
}
],
+ // Modules whose interrupts are connected to RV_PLIC.
+ interrupt_module: [
+ "uart0",
+ "gpio",
+ "spi_device",
+ "spi_host0",
+ // "rv_timer", connected to a dedicated interrupt input in rv_core_ibex.
+ "usbdev",
+ "pwrmgr_aon",
+ "aon_timer_aon",
+ "flash_ctrl",
+ "hmac",
+ ]
+
// ===== PINMUX & PINOUT ======================================================
pinout: {
@@ -809,7 +840,8 @@
//
// - instance: This is the comportable IO instance name where the IO signal comes from.
//
- // - connection: Can have either of the following values:
+ // - connection: This key is similar to the connection key in the pinout/pad configuration and
+ // can have either of the following values:
//
// 1) 'direct': This is a dedicated IO signal that is directly connected to a pad.
// Such an IO signal must also specify the 'port' and 'pad' keys
diff --git a/hw/top_englishbreakfast/data/xbar_main.hjson b/hw/top_englishbreakfast/data/xbar_main.hjson
index 1d2437b..42d5fa0 100644
--- a/hw/top_englishbreakfast/data/xbar_main.hjson
+++ b/hw/top_englishbreakfast/data/xbar_main.hjson
@@ -9,19 +9,18 @@
other_reset_list: [ "rst_fixed_ni" ] // Secondary clocks used by specific nodes
nodes: [
- { name: "corei",
+ { name: "rv_core_ibex.corei",
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
pipeline: "false"
},
- { name: "cored",
+ { name: "rv_core_ibex.cored",
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
pipeline: "false"
-
},
{ name: "rv_dm.sba",
type: "host",
@@ -96,6 +95,12 @@
inst_type: "rv_plic",
pipeline_byp: "false"
},
+ { name: "rv_core_ibex.cfg",
+ type: "device",
+ clock: "clk_main_i"
+ reset: "rst_main_ni"
+ pipeline_byp: "false"
+ },
{ name: "sram_ctrl_main.regs",
type: "device",
clock: "clk_main_i",
@@ -110,16 +115,19 @@
},
],
connections: {
- corei: ["rom_ctrl.rom", "rv_dm.rom", "sram_ctrl_main.ram", "eflash"],
- cored: [
- "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.rom", "rv_dm.regs", "eflash", "peri",
- "flash_ctrl.core", "flash_ctrl.prim", "aes", "hmac", "rv_plic", "sram_ctrl_main.ram",
- "sram_ctrl_main.regs"
+ rv_core_ibex.corei: ["rom_ctrl.rom", "rv_dm.rom", "sram_ctrl_main.ram", "eflash"],
+ rv_core_ibex.cored: [
+ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.rom", "rv_dm.regs",
+ "sram_ctrl_main.ram", "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim",
+ "aes", "hmac",
+ "rv_plic", "sram_ctrl_main.ram", "sram_ctrl_main.regs",
+ "rv_core_ibex.cfg"
],
rv_dm.sba: [
- "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.regs", "eflash", "peri",
- "flash_ctrl.core", "flash_ctrl.prim", "aes", "hmac", "rv_plic", "sram_ctrl_main.ram",
- "sram_ctrl_main.regs"
+ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.regs", "sram_ctrl_main.ram",
+ "eflash", "peri", "flash_ctrl.core", "flash_ctrl.prim", "aes",
+ "hmac", "rv_plic",
+ "sram_ctrl_main.regs", "rv_core_ibex.cfg"
],
},
}
diff --git a/hw/top_englishbreakfast/data/xbar_peri.hjson b/hw/top_englishbreakfast/data/xbar_peri.hjson
index d6e8849..e8f96f9 100644
--- a/hw/top_englishbreakfast/data/xbar_peri.hjson
+++ b/hw/top_englishbreakfast/data/xbar_peri.hjson
@@ -87,12 +87,6 @@
reset: "rst_peri_ni",
pipeline: "false",
},
- { name: "alert_handler",
- type: "device",
- clock: "clk_peri_i",
- reset: "rst_peri_ni",
- pipeline: "false",
- },
{ name: "sram_ctrl_ret_aon.regs",
type: "device",
clock: "clk_peri_i",
@@ -105,17 +99,14 @@
reset: "rst_peri_ni",
pipeline: "false"
},
-// { name: "ast",
-// type: "device",
-// clock: "clk_peri_i",
-// reset: "rst_peri_ni",
-// pipeline: "false",
-// },
],
connections: {
- main: ["uart0", "gpio", "spi_device", "spi_host0", "rv_timer", "usbdev",
- "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon", "lc_ctrl",
- "sensor_ctrl_aon", "alert_handler", "sram_ctrl_ret_aon.ram",
- "sram_ctrl_ret_aon.regs"],
+ main: [
+ "uart0",
+ "gpio", "spi_device", "spi_host0", "rv_timer", "usbdev",
+ "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon",
+ "lc_ctrl", "sensor_ctrl_aon",
+ "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs",
+ ],
},
}
diff --git a/hw/top_englishbreakfast/util/prepare_sw.py b/hw/top_englishbreakfast/util/prepare_sw.py
index 6e7cf43..b89ec7f 100755
--- a/hw/top_englishbreakfast/util/prepare_sw.py
+++ b/hw/top_englishbreakfast/util/prepare_sw.py
@@ -5,6 +5,7 @@
r"""Script to prepare SW for non-earlgrey tops
"""
+import argparse
import sys
import subprocess
import re
@@ -13,6 +14,20 @@
def main():
+ parser = argparse.ArgumentParser(
+ prog="prepare_sw",
+ description="Script to prepare SW sources for English Breakfast",
+ formatter_class=argparse.RawDescriptionHelpFormatter)
+
+ parser.add_argument(
+ '--build',
+ '-b',
+ default=False,
+ action='store_true',
+ help='Build ROM based on reduced design')
+
+ args = parser.parse_args()
+
# Config
name_old = 'earlgrey'
name = 'englishbreakfast'
@@ -62,6 +77,8 @@
# need to change some file and variable names in auto-generated files.
# 3. The build system still uses some sources from the original top level.
# We thus need to replace those with the new sources patched in 2.
+ # 4. References to IP cores not available on English Breakfast need to be
+ # removed from the source code of the boot ROM and some applications.
# 1.
cmd = ['sed', '-i', "s/TOPNAME='top_{}'/TOPNAME='top_{}'/g".format(name_old, name),
@@ -107,10 +124,10 @@
with open(path_out + file_name_new, "w") as file_out:
file_out.write(text)
- # Generate the boot_rom to enable the FPGA build.
- print("Generating boot ROM...")
- cmd = ['ninja', '-C', path_root + '/build-out',
- 'sw/device/boot_rom/boot_rom_export_fpga_nexysvideo']
+ # 4.
+ print("Patching SW sources...")
+ cmd = ['git', 'apply', '-p1', path_root + '/hw/' + topname + '/util/sw_sources.patch',
+ '--verbose']
try:
subprocess.run(cmd,
check=True,
@@ -119,10 +136,34 @@
universal_newlines=True)
except subprocess.CalledProcessError as e:
- print("Failed to generate boot ROM: " + str(e))
+ print("Failed to patch SW sources: " + str(e))
sys.exit(1)
- return 0
+ if (args.build):
+ # Build the software including boot_rom to enable the FPGA build.
+ binaries = [
+ 'sw/device/boot_rom/boot_rom_export_fpga_nexysvideo',
+ 'sw/device/sca/aes_serial_export_fpga_nexysvideo',
+ 'sw/device/boot_rom/boot_rom_export_sim_verilator',
+ 'sw/device/tests/dif_aes_smoketest_export_sim_verilator',
+ 'sw/device/examples/hello_world/hello_world_export_sim_verilator',
+ ]
+ for binary in binaries:
+ print("Building " + binary + "...")
+ cmd = ['ninja', '-C', path_root + '/build-out',
+ binary]
+ try:
+ subprocess.run(cmd,
+ check=True,
+ stdout=subprocess.PIPE,
+ stderr=subprocess.STDOUT,
+ universal_newlines=True)
+
+ except subprocess.CalledProcessError as e:
+ print("Failed to generate boot ROM: " + str(e))
+ sys.exit(1)
+
+ return 0
if __name__ == "__main__":
diff --git a/hw/top_englishbreakfast/util/sw_sources.patch b/hw/top_englishbreakfast/util/sw_sources.patch
new file mode 100644
index 0000000..6f7fb9c
--- /dev/null
+++ b/hw/top_englishbreakfast/util/sw_sources.patch
@@ -0,0 +1,186 @@
+diff --git a/sw/device/boot_rom/rom_crt.S b/sw/device/boot_rom/rom_crt.S
+index 538712db1..1c8e29d86 100644
+--- a/sw/device/boot_rom/rom_crt.S
++++ b/sw/device/boot_rom/rom_crt.S
+@@ -81,19 +81,6 @@ _reset_start:
+ _start:
+ .globl _start
+
+- // Enable entropy complex - this is not the full enable
+- li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
+- li t0, 0x2
+- sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
+-
+- li a0, TOP_EARLGREY_CSRNG_BASE_ADDR
+- li t0, 0xaa
+- sw t0, CSRNG_CTRL_REG_OFFSET(a0)
+-
+- li a0, TOP_EARLGREY_EDN0_BASE_ADDR
+- li t0, 0xaa
+- sw t0, EDN_CTRL_REG_OFFSET(a0)
+-
+ // Request memory scrambling and init
+ li a0, TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR
+ li a1, (1<<SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT)|(1<<SRAM_CTRL_CTRL_INIT_BIT)
+diff --git a/sw/device/lib/pinmux.c b/sw/device/lib/pinmux.c
+index 8861f54ba..8442bb896 100644
+--- a/sw/device/lib/pinmux.c
++++ b/sw/device/lib/pinmux.c
+@@ -60,24 +60,4 @@ void pinmux_init(void) {
+ reg_offset = kTopEarlgreyPinmuxMioOutIoc11 << 2;
+ mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK;
+ mmio_region_write32(reg32, reg_offset, reg_value & mask);
+-
+- // Configure UART1 RX input to connect to MIO pad IOC8
+- reg32 = mmio_region_from_addr(PINMUX0_BASE_ADDR +
+- PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET);
+- reg_value = kTopEarlgreyPinmuxInselIoc8;
+- // We've got one insel configuration field per register. Hence, we have to
+- // convert the enumeration index into a byte address using << 2.
+- reg_offset = kTopEarlgreyPinmuxPeripheralInUart1Rx << 2;
+- mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK;
+- mmio_region_write32(reg32, reg_offset, reg_value & mask);
+-
+- // Configure UART1 TX output to connect to MIO pad IOC9
+- reg32 =
+- mmio_region_from_addr(PINMUX0_BASE_ADDR + PINMUX_MIO_OUTSEL_0_REG_OFFSET);
+- reg_value = kTopEarlgreyPinmuxOutselUart1Tx;
+- // We've got one insel configuration field per register. Hence, we have to
+- // convert the enumeration index into a byte address using << 2.
+- reg_offset = kTopEarlgreyPinmuxMioOutIoc9 << 2;
+- mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK;
+- mmio_region_write32(reg32, reg_offset, reg_value & mask);
+ }
+diff --git a/sw/device/sca/aes_serial.c b/sw/device/sca/aes_serial.c
+index 50bee15fa..8f5976a83 100644
+--- a/sw/device/sca/aes_serial.c
++++ b/sw/device/sca/aes_serial.c
+@@ -203,21 +203,13 @@ int main(void) {
+ sca_init();
+ sca_get_uart(&uart1);
+
+- LOG_INFO("Running AES serial");
+-
+- LOG_INFO("Disabling entropy complex and unneeded clocks to reduce noise.");
+- sca_reduce_noise();
+-
+- LOG_INFO("Initializing simple serial interface to capture board.");
+ simple_serial_init(uart1);
+ simple_serial_register_handler('k', aes_serial_set_key);
+ simple_serial_register_handler('p', aes_serial_single_encrypt);
+ simple_serial_register_handler('b', aes_serial_batch_encrypt);
+
+- LOG_INFO("Initializing AES unit.");
+ init_aes();
+
+- LOG_INFO("Starting simple serial packet handling.");
+ while (true) {
+ simple_serial_process_packet();
+ }
+diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c
+index 9e732a812..ca2bd0ab7 100644
+--- a/sw/device/sca/lib/sca.c
++++ b/sw/device/sca/lib/sca.c
+@@ -50,7 +50,6 @@ enum {
+ kRvTimerHart = kTopEarlgreyPlicTargetIbex0,
+ };
+
+-static dif_uart_t uart0;
+ static dif_uart_t uart1;
+ static dif_gpio_t gpio;
+ static dif_rv_timer_t timer;
+@@ -72,16 +71,9 @@ static void sca_init_uart(void) {
+ (dif_uart_params_t){
+ .base_addr = mmio_region_from_addr(TOP_EARLGREY_UART0_BASE_ADDR),
+ },
+- &uart0));
+- IGNORE_RESULT(dif_uart_configure(&uart0, uart_config));
+- base_uart_stdout(&uart0);
+-
+- IGNORE_RESULT(dif_uart_init(
+- (dif_uart_params_t){
+- .base_addr = mmio_region_from_addr(TOP_EARLGREY_UART1_BASE_ADDR),
+- },
+ &uart1));
+ IGNORE_RESULT(dif_uart_configure(&uart1, uart_config));
++ base_uart_stdout(&uart1);
+ }
+
+ /**
+@@ -137,41 +129,16 @@ void sca_init(void) {
+ }
+
+ void sca_reduce_noise() {
+- // Disable/stopping functionality not yet provided by EDN and CSRNG DIFs.
+- mmio_region_write32(mmio_region_from_addr(TOP_EARLGREY_EDN0_BASE_ADDR),
+- EDN_CTRL_REG_OFFSET, EDN_CTRL_REG_RESVAL);
+- mmio_region_write32(mmio_region_from_addr(TOP_EARLGREY_EDN1_BASE_ADDR),
+- EDN_CTRL_REG_OFFSET, EDN_CTRL_REG_RESVAL);
+- mmio_region_write32(mmio_region_from_addr(TOP_EARLGREY_CSRNG_BASE_ADDR),
+- CSRNG_CTRL_REG_OFFSET, CSRNG_CTRL_REG_RESVAL);
+-
+- // Disable entropy source through DIF.
+- const dif_entropy_params_t entropy_params = {
+- .base_addr = mmio_region_from_addr(TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR),
+- };
+- dif_entropy_t entropy;
+- IGNORE_RESULT(dif_entropy_init(entropy_params, &entropy) == kDifEntropyOk);
+- IGNORE_RESULT(dif_entropy_disable(&entropy) == kDifEntropyOk);
+-
+ // Disable HMAC, KMAC, OTBN and USB clocks through CLKMGR DIF.
+ const dif_clkmgr_params_t clkmgr_params = {
+ .base_addr = mmio_region_from_addr(TOP_EARLGREY_CLKMGR_AON_BASE_ADDR),
+ .last_gateable_clock = CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
+- .last_hintable_clock = CLKMGR_CLK_HINTS_STATUS_CLK_MAIN_OTBN_VAL_BIT};
++ .last_hintable_clock = CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT};
+ dif_clkmgr_t clkmgr;
+ IGNORE_RESULT(dif_clkmgr_init(clkmgr_params, &clkmgr) == kDifClkmgrOk);
+ IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
+ &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT,
+ kDifClkmgrToggleDisabled) == kDifClkmgrOk);
+- IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
+- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_KMAC_HINT_BIT,
+- kDifClkmgrToggleDisabled) == kDifClkmgrOk);
+- IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
+- &clkmgr, CLKMGR_CLK_HINTS_CLK_IO_DIV4_OTBN_HINT_BIT,
+- kDifClkmgrToggleDisabled) == kDifClkmgrOk);
+- IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
+- &clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_OTBN_HINT_BIT,
+- kDifClkmgrToggleDisabled) == kDifClkmgrOk);
+ IGNORE_RESULT(dif_clkmgr_gateable_clock_set_enabled(
+ &clkmgr, CLKMGR_CLK_ENABLES_CLK_USB_PERI_EN_BIT,
+ kDifClkmgrToggleDisabled) == kDifClkmgrOk);
+diff --git a/sw/device/tests/dif/dif_aes_smoketest.c b/sw/device/tests/dif/dif_aes_smoketest.c
+index 70c3baaf9..5d69301e2 100644
+--- a/sw/device/tests/dif/dif_aes_smoketest.c
++++ b/sw/device/tests/dif/dif_aes_smoketest.c
+@@ -7,7 +7,6 @@
+ #include "sw/device/lib/dif/dif_aes.h"
+ #include "sw/device/lib/runtime/log.h"
+ #include "sw/device/lib/testing/check.h"
+-#include "sw/device/lib/testing/entropy_testutils.h"
+ #include "sw/device/lib/testing/test_main.h"
+
+ #include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+@@ -67,9 +66,6 @@ bool test_main(void) {
+
+ LOG_INFO("Running AES test");
+
+- // First of all, we need to get the entropy complex up and running.
+- entropy_testutils_boot_mode_init();
+-
+ // Initialise AES.
+ dif_aes_params_t params = {
+ .base_addr = mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR),
+diff --git a/sw/device/tests/dif/meson.build b/sw/device/tests/dif/meson.build
+index 7ff797bcb..b9e53a744 100644
+--- a/sw/device/tests/dif/meson.build
++++ b/sw/device/tests/dif/meson.build
+@@ -217,7 +217,6 @@ dif_aes_smoketest_lib = declare_dependency(
+ sw_lib_dif_aes,
+ sw_lib_mmio,
+ sw_lib_runtime_log,
+- sw_lib_testing_entropy_testutils_lib,
+ sw_lib_testing_test_status,
+ ],
+ ),
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 58c9a43..1b2b669 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -1081,6 +1081,9 @@
.SecAesAllowForcingMasks(1'b1),
.SecAesSkipPRNGReseeding(1'b1),
.RvCoreIbexICache(0),
+ .RvCoreIbexICacheECC(0),
+ .RvCoreIbexBranchTargetALU(0),
+ .RvCoreIbexWritebackStage(0),
% else:
.AesMasking(1'b0),
.AesSBoxImpl(aes_pkg::SBoxImplLut),
