commit 7824ccc3195c1d9f5dedd70c006b8ec0fd68faae
author Tom Roberts <tomroberts@lowrisc.org> Thu Nov 05 11:34:03 2020 +0000
committer Tom Roberts <53745528+tomroberts-lowrisc@users.noreply.github.com> Fri Nov 06 08:57:30 2020 +0000
tree 669a46402bae1bc9e9b59a58f5c39a4d06135b86
parent 3a5fdd65bfd8e71701c7e019ae980ec39610b474

[ibex] Enable icache in top_earlgrey

Fixes #3539

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>

hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv

diff --git a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
index 29b820c..ff018f2 100644
--- a/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
+++ b/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv
@@ -70,6 +70,8 @@
   // if pipeline is 0, passthrough the fifo completely
   localparam int FifoPass = PipeLine ? 1'b0 : 1'b1;
   localparam int FifoDepth = PipeLine ? 4'h2 : 4'h0;
+  // ICache creates more outstanding transactions
+  localparam int NumOutstandingReqs = ICache ? 8 : 2;
 
   // Instruction interface (internal)
   logic        instr_req;
@@ -235,7 +237,7 @@
   //
 
   tlul_adapter_host #(
-    .MAX_REQS(2)
+    .MAX_REQS(NumOutstandingReqs)
   ) tl_adapter_host_i_ibex (
     .clk_i,
     .rst_ni,

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index eeddd41..5286036 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -39,6 +39,7 @@
 
   // Manually defined parameters
   parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
+  parameter bit IbexICache = 1,
   parameter bit IbexPipeLine = 0,
   parameter     BootRomInitFile = ""
 ) (
@@ -203,8 +204,8 @@
     .RegFile                  (IbexRegFile),
     .BranchTargetALU          (1),
     .WritebackStage           (1),
-    .ICache                   (0),
-    .ICacheECC                (0),
+    .ICache                   (IbexICache),
+    .ICacheECC                (1),
     .BranchPredictor          (0),
     .DbgTriggerEn             (1),
     .SecureIbex               (0),

hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 340be87..8eb6894 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -20,6 +20,7 @@
 
   // Manually defined parameters
   parameter ibex_pkg::regfile_e IbexRegFile = ibex_pkg::RegFileFF,
+  parameter bit IbexICache = 1,
   parameter bit IbexPipeLine = 0,
   parameter     BootRomInitFile = ""
 ) (
@@ -325,8 +326,8 @@
     .RegFile                  (IbexRegFile),
     .BranchTargetALU          (1),
     .WritebackStage           (1),
-    .ICache                   (0),
-    .ICacheECC                (0),
+    .ICache                   (IbexICache),
+    .ICacheECC                (1),
     .BranchPredictor          (0),
     .DbgTriggerEn             (1),
     .SecureIbex               (0),

hw/top_earlgrey/rtl/top_earlgrey_cw305.sv

diff --git a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
index dc8df3e..81a5de0 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_cw305.sv
@@ -242,6 +242,7 @@
     .SecAesStartTriggerDelay(40),
     .SecAesAllowForcingMasks(1'b1),
     .IbexRegFile(ibex_pkg::RegFileFPGA),
+    .IbexICache(0),
     .IbexPipeLine(1),
     .OtbnRegFile(otbn_pkg::RegFileFPGA),
     .BootRomInitFile(BootRomInitFile)