[dv/common] move reset test to cip_base_vseq
Move reset test to CIP base common seq
Add hmac new csr
Delete redundant code in stress test
diff --git a/hw/dv/sv/cip_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/cip_base_vseq.sv
index e1e9e4d..63f9b6a 100644
--- a/hw/dv/sv/cip_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/cip_base_vseq.sv
@@ -202,6 +202,12 @@
exp_pins = '0;
exp_intr_state = ~interrupts;
end
+ // if reset, pin should be reset to 0
+ if (!cfg.clk_rst_vif.rst_n) begin
+ exp_pins = '0;
+ exp_intr_state = '0;
+ `uvm_info(`gfn, "interrupt pin expect value set to 0 due to reset", UVM_LOW)
+ end
`DV_CHECK_EQ(act_pins, exp_pins)
csr = get_interrupt_csr("intr_state", "", indices, scope);
csr_rd_check(.ptr(csr), .compare_value(exp_intr_state), .compare_mask(interrupts));
@@ -215,9 +221,10 @@
if (common_seq_type == "") void'($value$plusargs("run_%0s", common_seq_type));
// check which test type
case (common_seq_type)
- "intr_test": run_intr_test_vseq(num_times);
- "tl_errors": run_tl_errors_vseq(num_times);
- default : run_csr_vseq_wrapper(num_times);
+ "intr_test": run_intr_test_vseq(num_times);
+ "tl_errors": run_tl_errors_vseq(num_times);
+ "stress_all_with_rand_reset": run_stress_all_with_rand_reset_vseq(num_times);
+ default: run_csr_vseq_wrapper(num_times);
endcase
endtask
@@ -305,4 +312,61 @@
`DV_CHECK_EQ(cfg.intr_vif.sample(), {NUM_MAX_INTERRUPTS{1'b0}})
endtask
+ // task to insert random reset within the input vseqs list, then check all CSR values
+ virtual task run_stress_all_with_rand_reset_vseq(int num_times=1);
+ string stress_seq_name;
+ void'($value$plusargs("stress_seq=%0s", stress_seq_name));
+
+ for (int i = 1; i <= num_times; i++) begin
+ bit ongoing_reset;
+ bit do_read_and_check_all_csrs;
+ fork
+ begin: isolation_fork
+ fork : run_test_seqs
+ begin : seq_wo_reset
+ uvm_sequence seq;
+ dv_base_vseq #(RAL_T, CFG_T, COV_T, VIRTUAL_SEQUENCER_T) dv_vseq;
+
+ seq = create_seq_by_name(stress_seq_name);
+ `downcast(dv_vseq, seq)
+ dv_vseq.do_dut_init = 0;
+ dv_vseq.set_sequencer(p_sequencer);
+ `DV_CHECK_RANDOMIZE_FATAL(dv_vseq)
+ dv_vseq.start(p_sequencer);
+ wait (ongoing_reset == 0)
+ `uvm_info(`gfn, $sformatf("Finished run %0d/%0d w/o reset", i, num_trans), UVM_LOW)
+ end
+ begin : issue_rand_reset
+ cfg.clk_rst_vif.wait_clks(delay);
+ ongoing_reset = 1'b1;
+ `uvm_info(`gfn, $sformatf("Reset is issued for run %0d/%0d", i, num_trans), UVM_LOW)
+ apply_reset("HARD");
+ ongoing_reset = 1'b0;
+ do_read_and_check_all_csrs = 1'b1;
+ csr_utils_pkg::clear_outstanding_access();
+ end
+ join_any
+ p_sequencer.tl_sequencer_h.stop_sequences();
+ disable fork;
+ // delay to avoid race condition when sending item and checking no item after reset occur at
+ // the same time
+ #1ps;
+ if (do_read_and_check_all_csrs) read_and_check_all_csrs();
+ end : isolation_fork
+ join
+ end
+ endtask
+
+ // task to read all csrs and check against ral expected value
+ // used after reset
+ virtual task read_and_check_all_csrs();
+ uvm_reg csrs[$];
+ ral.get_registers(csrs);
+ csrs.shuffle();
+
+ foreach (csrs[i]) begin
+ csr_rd_check(.ptr(csrs[i]), .compare_vs_ral(1));
+ end
+ endtask
+
endclass
diff --git a/hw/dv/sv/csr_utils/README.md b/hw/dv/sv/csr_utils/README.md
index d7580d2..b23403b 100644
--- a/hw/dv/sv/csr_utils/README.md
+++ b/hw/dv/sv/csr_utils/README.md
@@ -33,6 +33,10 @@
task automatic wait_no_outstanding_access();
wait(outstanding_accesses == 0);
endtask
+
+ function automatic void clear_outstanding_access();
+ outstanding_accesses = 0;
+ endfunction
```
##### CSR spinwait
@@ -46,6 +50,23 @@
csr_spinwait(.ptr(ral.status.fifo_full), .exp_data(1'b0));
```
+##### Under_reset
+Due to `csr_utils_pkg` is not connected to any interface, methods inside
+this package are not able to get reset information. Current the `under_reset`
+bit is declared with two functions:
+```systemverilog
+function automatic void reset_occurred();
+ under_reset = 1;
+endfunction
+
+function automatic void reset_cleared();
+ under_reset = 0;
+endfunction
+```
+This reset information is updated in `dv_lib/dv_base_vseq.sv`. When the
+`apply_reset` task is triggered, it will set and reset the `under_reset` bit
+via the functions above.
+
#### Global CSR util methods
##### Global methods for CSR and MEM attributes
This package provides methods to access CSR or Memory attributes, such as address,
diff --git a/hw/dv/sv/csr_utils/csr_utils_pkg.sv b/hw/dv/sv/csr_utils/csr_utils_pkg.sv
index 47cb5c0..0c631e1 100644
--- a/hw/dv/sv/csr_utils/csr_utils_pkg.sv
+++ b/hw/dv/sv/csr_utils/csr_utils_pkg.sv
@@ -17,6 +17,7 @@
uint default_spinwait_timeout_ns = 10_000_000; // 10ms
string msg_id = "csr_utils";
bit default_csr_blocking = 1;
+ bit under_reset = 0;
// csr field struct - hold field specific params
typedef struct {
@@ -48,6 +49,18 @@
wait(outstanding_accesses == 0);
endtask
+ function automatic void clear_outstanding_access();
+ outstanding_accesses = 0;
+ endfunction
+
+ function automatic void reset_occurred();
+ under_reset = 1;
+ endfunction
+
+ function automatic void reset_cleared();
+ under_reset = 0;
+ endfunction
+
// Get all valid csr addrs - useful to check if incoming addr falls in the csr range.
function automatic void get_csr_addrs(input uvm_reg_block ral, ref uvm_reg_addr_t csr_addrs[$]);
uvm_reg csrs[$];
@@ -334,7 +347,7 @@
end
csr_rd(.ptr(ptr), .value(obs), .check(check), .path(path),
.blocking(1), .timeout_ns(timeout_ns), .map(map));
- if (compare) begin
+ if (compare && !under_reset) begin
obs = obs & compare_mask;
exp = (compare_vs_ral ? exp : compare_value) & compare_mask;
`DV_CHECK_EQ(obs, exp, {"Regname: ", ptr.get_full_name(), " ", err_msg},
diff --git a/hw/dv/sv/dv_lib/dv_base_vseq.sv b/hw/dv/sv/dv_lib/dv_base_vseq.sv
index e3fac2e..8c08574 100644
--- a/hw/dv/sv/dv_lib/dv_base_vseq.sv
+++ b/hw/dv/sv/dv_lib/dv_base_vseq.sv
@@ -12,6 +12,16 @@
// number of iterations to run the test seq - please override constraint in extended vseq
// randomization for this is disabled in pre_start since we don't want to re-randomize it again
rand uint num_trans;
+ rand uint delay;
+ constraint delay_c {
+ delay dist {
+ 0 :/ 1,
+ [1 :100] :/ 1,
+ [101 :10_000] :/ 8,
+ [10_001 :1_000_000] :/ 1
+ };
+ }
+
constraint num_trans_c {
num_trans inside {[1:20]};
}
@@ -60,8 +70,12 @@
endtask
virtual task apply_reset(string kind = "HARD");
- if (kind == "HARD") cfg.clk_rst_vif.apply_reset();
- if (cfg.has_ral) ral.reset(kind);
+ if (kind == "HARD") begin
+ csr_utils_pkg::reset_occurred();
+ cfg.clk_rst_vif.apply_reset();
+ csr_utils_pkg::reset_cleared();
+ end
+ if (cfg.has_ral) ral.reset(kind);
endtask
virtual task wait_for_reset(string reset_kind = "HARD");
diff --git a/hw/dv/tools/common_tests.mk b/hw/dv/tools/common_tests.mk
index 0d0b6ee..f2b199e 100644
--- a/hw/dv/tools/common_tests.mk
+++ b/hw/dv/tools/common_tests.mk
@@ -52,4 +52,11 @@
RUN_OPTS += +run_intr_test
endif
+ifeq (${TEST_NAME},${TEST_PREFIX}_stress_all_with_rand_reset)
+ UVM_TEST_SEQ = ${TEST_PREFIX}_common_vseq
+ RUN_OPTS += +run_stress_all_with_rand_reset
+ RUN_OPTS += +test_timeout_ns=10_000_000_000
+ RUN_OPTS += +stress_seq=${TEST_PREFIX}_stress_all_vseq
+endif
+
diff --git a/hw/ip/hmac/data/hmac_testplan.hjson b/hw/ip/hmac/data/hmac_testplan.hjson
index 37052ee..0a27735 100644
--- a/hw/ip/hmac/data/hmac_testplan.hjson
+++ b/hw/ip/hmac/data/hmac_testplan.hjson
@@ -65,11 +65,11 @@
tests: ["hmac_stress_all"]
}
{
- name: reset
+ name: stress_all_with_rand_reset
desc: '''Reset test insert random reset during the stress_all test. After reset is asserted,
the test will read and check all valid CSR registers.'''
milestone: V2
- tests: ["hmac_reset"]
+ tests: ["hmac_stress_all_with_rand_reset"]
}
]
}
diff --git a/hw/ip/hmac/dv/Makefile b/hw/ip/hmac/dv/Makefile
index d402570..5ac8aa9 100644
--- a/hw/ip/hmac/dv/Makefile
+++ b/hw/ip/hmac/dv/Makefile
@@ -68,12 +68,9 @@
RUN_OPTS += +test_timeout_ns=10_000_000_000
endif
-ifeq (${TEST_NAME},hmac_reset)
- UVM_TEST_SEQ = hmac_reset_vseq
+ifeq (${TEST_NAME},hmac_stress_all_with_rand_reset)
RUN_OPTS += +test_vectors_dir=${DV_DIR}/../../../dv/sv/test_vectors/
- RUN_OPTS += +test_timeout_ns=10_000_000_000
endif
-
####################################################################################################
## Include the tool Makefile below ##
## Dont add anything else below it! ##
diff --git a/hw/ip/hmac/dv/env/hmac_scoreboard.sv b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
index 95a3acb..ac25d00 100644
--- a/hw/ip/hmac/dv/env/hmac_scoreboard.sv
+++ b/hw/ip/hmac/dv/env/hmac_scoreboard.sv
@@ -84,6 +84,8 @@
// any bytes left after hmac_process will be added to the wr_cnt
if (msg_q.size() % 4 != 0) incr_wr_and_check_fifo_full();
msg_q.delete();
+ end else if (hmac_start) begin
+ msg_q.delete(); // make sure did not include previous msg
end
end else if (item.a_data[HashStart] == 1) begin
void'(ral.intr_state.hmac_err.predict(.value(1), .kind(UVM_PREDICT_DIRECT)));
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
index 6c9ee4e..99178ed 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_base_vseq.sv
@@ -279,20 +279,13 @@
virtual task compare_digest(bit [TL_DW-1:0] exp_digest[8]);
logic [TL_DW-1:0] act_digest[8];
csr_rd_digest(act_digest);
- foreach (act_digest[i]) begin
- `DV_CHECK_EQ(act_digest[i], exp_digest[i], $sformatf("for index %0d", i))
+ if (cfg.clk_rst_vif.rst_n) begin
+ foreach (act_digest[i]) begin
+ `DV_CHECK_EQ(act_digest[i], exp_digest[i], $sformatf("for index %0d", i))
+ end
+ end else begin
+ `uvm_info(`gfn, "skipped comparison due to reset", UVM_LOW)
end
endtask
- // task to read all csrs and check against ral expected value
- // used after reset
- virtual task read_and_check_all_csrs();
- uvm_reg csrs[$];
- ral.get_registers(csrs);
- csrs.shuffle();
-
- foreach (csrs[i]) begin
- csr_rd_check(.ptr(csrs[i]), .compare_vs_ral(1));
- end
- endtask
endclass : hmac_base_vseq
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_reset_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_reset_vseq.sv
deleted file mode 100644
index d599075..0000000
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_reset_vseq.sv
+++ /dev/null
@@ -1,58 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-// one thread running the hmac_stress_all sequence
-// another thread randomly insert reset
-// after reset, check if all readable csrs are set to default reset value
-
-class hmac_reset_vseq extends hmac_base_vseq;
- `uvm_object_utils(hmac_reset_vseq)
-
- rand uint delay;
-
- `uvm_object_new
-
- constraint delay_c {
- delay dist {
- 0 :/ 1,
- [1 :100] :/ 1,
- [101 :10_000] :/ 8,
- [10_001 :1_000_000] :/ 1
- };
- }
-
- task body();
- for (int i = 1; i <= num_trans; i++) begin
- bit reset_flag;
- fork
- begin : seq_wo_reset
- hmac_stress_all_vseq hmac_vseq = new;
-
- // dut_init (reset) is skipped because reset is randomly asserted in the reset thread
- if (i > 0) hmac_vseq.do_dut_init = 0;
-
- hmac_vseq.set_sequencer(p_sequencer);
- `DV_CHECK_RANDOMIZE_FATAL(hmac_vseq)
- hmac_vseq.start(p_sequencer);
- end
-
- begin : reset
- `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay)
- cfg.clk_rst_vif.wait_clks(delay);
- csr_utils_pkg::wait_no_outstanding_access(); // TODO : temp wait, need support
- reset_flag = 1'b1;
- end
- join_any
- disable fork;
-
- if (reset_flag) begin // trigger reset
- `uvm_info(`gfn, "hmac_reset triggered", UVM_LOW)
- apply_reset("HARD");
- read_and_check_all_csrs();
- reset_flag = 1'b0;
- end
- end // end for loop
- endtask : body
-
-endclass
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
index 72bf667..ae0891e 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_stress_all_vseq.sv
@@ -26,8 +26,9 @@
seq = create_seq_by_name(seq_names[seq_idx]);
`downcast(hmac_vseq, seq)
- // dut_init (reset) can be skipped after the 1st seq
- if (i > 0) hmac_vseq.do_dut_init = $urandom_range(0, 1);
+ // dut_init (reset) can be skipped
+ if (do_dut_init) hmac_vseq.do_dut_init = $urandom_range(0, 1);
+ else hmac_vseq.do_dut_init = 0;
hmac_vseq.set_sequencer(p_sequencer);
`DV_CHECK_RANDOMIZE_FATAL(hmac_vseq)
diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
index 5d8e644..8e90ae6 100644
--- a/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
+++ b/hw/ip/hmac/dv/env/seq_lib/hmac_vseq_list.sv
@@ -12,4 +12,3 @@
`include "hmac_common_vseq.sv"
`include "hmac_datapath_stress_vseq.sv"
`include "hmac_stress_all_vseq.sv"
-`include "hmac_reset_vseq.sv"
