[top/earlgrey] Generated codes for PINMUX
As templates and generation script are changed in previous commit, all
related generated codes are re-generated.
diff --git a/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson
index 100de00..6f3b94c 100644
--- a/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/doc/autogen/top_earlgrey.gen.hjson
@@ -393,6 +393,29 @@
interrupt_list: []
scan: "false"
}
+ {
+ name: pinmux
+ type: pinmux
+ clock: main
+ clock_connections:
+ {
+ clk_i: main
+ }
+ reset_connections:
+ {
+ rst_ni: sys
+ }
+ base_addr: 0x40070000
+ generated: "true"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ interrupt_list: []
+ scan: "false"
+ }
]
memory:
[
@@ -475,6 +498,7 @@
aes
hmac
rv_plic
+ pinmux
]
dm_sba:
[
@@ -489,6 +513,7 @@
aes
hmac
rv_plic
+ pinmux
]
}
nodes:
@@ -637,6 +662,16 @@
pipeline_byp: "false"
pipeline: "true"
}
+ {
+ name: pinmux
+ type: device
+ clock: main
+ inst_type: pinmux
+ base_addr: 0x40070000
+ size_byte: 0x1000
+ pipeline_byp: "false"
+ pipeline: "true"
+ }
]
clock: main
}
@@ -774,6 +809,7 @@
]
pinmux:
{
+ num_mio: 32
dio_modules:
[
{
@@ -784,10 +820,10 @@
]
}
{
- name: uart.tx
+ name: uart
pad:
[
- ChA[0]
+ ChA[0..1]
]
}
]
@@ -852,9 +888,9 @@
]
}
{
- name: uart_tx
+ name: uart_rx
width: 1
- type: output
+ type: input
pad:
[
{
@@ -863,15 +899,20 @@
}
]
}
- ]
- inputs:
- [
{
- name: uart_rx
+ name: uart_tx
width: 1
- type: input
+ type: output
+ pad:
+ [
+ {
+ name: ChA
+ index: 1
+ }
+ ]
}
]
+ inputs: []
outputs: []
inouts:
[
diff --git a/hw/top_earlgrey/dv/env/chip_reg_block.sv b/hw/top_earlgrey/dv/env/chip_reg_block.sv
index 8a160f0..1b5d72e 100644
--- a/hw/top_earlgrey/dv/env/chip_reg_block.sv
+++ b/hw/top_earlgrey/dv/env/chip_reg_block.sv
@@ -5232,7 +5232,7 @@
p32 = dv_base_reg_field::type_id::create("p32");
p32.configure(
.parent(this),
- .size(1),
+ .size(32),
.lsb_pos(0),
.access("RO"),
.volatile(1),
@@ -5364,8 +5364,8 @@
p44 = dv_base_reg_field::type_id::create("p44");
p44.configure(
.parent(this),
- .size(1),
- .lsb_pos(12),
+ .size(32),
+ .lsb_pos(0),
.access("RO"),
.volatile(1),
.reset(32'h0),
@@ -5375,8 +5375,8 @@
p45 = dv_base_reg_field::type_id::create("p45");
p45.configure(
.parent(this),
- .size(1),
- .lsb_pos(13),
+ .size(32),
+ .lsb_pos(0),
.access("RO"),
.volatile(1),
.reset(32'h0),
@@ -5386,8 +5386,8 @@
p46 = dv_base_reg_field::type_id::create("p46");
p46.configure(
.parent(this),
- .size(1),
- .lsb_pos(14),
+ .size(32),
+ .lsb_pos(0),
.access("RO"),
.volatile(1),
.reset(32'h0),
@@ -5397,8 +5397,8 @@
p47 = dv_base_reg_field::type_id::create("p47");
p47.configure(
.parent(this),
- .size(1),
- .lsb_pos(15),
+ .size(32),
+ .lsb_pos(0),
.access("RO"),
.volatile(1),
.reset(32'h0),
@@ -5419,9 +5419,9 @@
p49 = dv_base_reg_field::type_id::create("p49");
p49.configure(
.parent(this),
- .size(1),
- .lsb_pos(17),
- .access("RO"),
+ .size(3),
+ .lsb_pos(1),
+ .access("RW"),
.volatile(1),
.reset(32'h0),
.has_reset(1),
@@ -5453,8 +5453,8 @@
p52.configure(
.parent(this),
.size(1),
- .lsb_pos(20),
- .access("RO"),
+ .lsb_pos(0),
+ .access("RW"),
.volatile(1),
.reset(32'h0),
.has_reset(1),
@@ -5464,8 +5464,8 @@
p53.configure(
.parent(this),
.size(1),
- .lsb_pos(21),
- .access("RO"),
+ .lsb_pos(1),
+ .access("RW"),
.volatile(1),
.reset(32'h0),
.has_reset(1),
@@ -5475,8 +5475,8 @@
p54.configure(
.parent(this),
.size(1),
- .lsb_pos(22),
- .access("RO"),
+ .lsb_pos(2),
+ .access("RW"),
.volatile(1),
.reset(32'h0),
.has_reset(1),
@@ -6590,8 +6590,8 @@
prio13 = dv_base_reg_field::type_id::create("prio13");
prio13.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(23),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6620,8 +6620,8 @@
prio14 = dv_base_reg_field::type_id::create("prio14");
prio14.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(24),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6650,8 +6650,8 @@
prio15 = dv_base_reg_field::type_id::create("prio15");
prio15.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(25),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6680,8 +6680,8 @@
prio16 = dv_base_reg_field::type_id::create("prio16");
prio16.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(26),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6710,8 +6710,8 @@
prio17 = dv_base_reg_field::type_id::create("prio17");
prio17.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(27),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6740,8 +6740,8 @@
prio18 = dv_base_reg_field::type_id::create("prio18");
prio18.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(28),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6770,8 +6770,8 @@
prio19 = dv_base_reg_field::type_id::create("prio19");
prio19.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(29),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6800,8 +6800,8 @@
prio20 = dv_base_reg_field::type_id::create("prio20");
prio20.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(30),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6830,8 +6830,8 @@
prio21 = dv_base_reg_field::type_id::create("prio21");
prio21.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(31),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6860,7 +6860,7 @@
prio22 = dv_base_reg_field::type_id::create("prio22");
prio22.configure(
.parent(this),
- .size(2),
+ .size(1),
.lsb_pos(0),
.access("RW"),
.volatile(0),
@@ -6890,8 +6890,8 @@
prio23 = dv_base_reg_field::type_id::create("prio23");
prio23.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(1),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6920,8 +6920,8 @@
prio24 = dv_base_reg_field::type_id::create("prio24");
prio24.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(2),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6950,8 +6950,8 @@
prio25 = dv_base_reg_field::type_id::create("prio25");
prio25.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(3),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -6980,8 +6980,8 @@
prio26 = dv_base_reg_field::type_id::create("prio26");
prio26.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(4),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7010,8 +7010,8 @@
prio27 = dv_base_reg_field::type_id::create("prio27");
prio27.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(5),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7040,8 +7040,8 @@
prio28 = dv_base_reg_field::type_id::create("prio28");
prio28.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(6),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7070,8 +7070,8 @@
prio29 = dv_base_reg_field::type_id::create("prio29");
prio29.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(7),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7100,8 +7100,8 @@
prio30 = dv_base_reg_field::type_id::create("prio30");
prio30.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(8),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7130,8 +7130,8 @@
prio31 = dv_base_reg_field::type_id::create("prio31");
prio31.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(9),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7160,8 +7160,8 @@
prio32 = dv_base_reg_field::type_id::create("prio32");
prio32.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(10),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7190,8 +7190,8 @@
prio33 = dv_base_reg_field::type_id::create("prio33");
prio33.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(11),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7220,8 +7220,8 @@
prio34 = dv_base_reg_field::type_id::create("prio34");
prio34.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(12),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -7250,8 +7250,107 @@
prio35 = dv_base_reg_field::type_id::create("prio35");
prio35.configure(
.parent(this),
- .size(2),
- .lsb_pos(0),
+ .size(1),
+ .lsb_pos(13),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le46 = dv_base_reg_field::type_id::create("le46");
+ le46.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(14),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le47 = dv_base_reg_field::type_id::create("le47");
+ le47.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(15),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le48 = dv_base_reg_field::type_id::create("le48");
+ le48.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le49 = dv_base_reg_field::type_id::create("le49");
+ le49.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(17),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le50 = dv_base_reg_field::type_id::create("le50");
+ le50.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le51 = dv_base_reg_field::type_id::create("le51");
+ le51.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(19),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le52 = dv_base_reg_field::type_id::create("le52");
+ le52.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(20),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le53 = dv_base_reg_field::type_id::create("le53");
+ le53.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(21),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ le54 = dv_base_reg_field::type_id::create("le54");
+ le54.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(22),
.access("RW"),
.volatile(0),
.reset(32'h0),
@@ -8057,6 +8156,560 @@
e16 = dv_base_reg_field::type_id::create("e16");
e16.configure(
.parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio45
+
+// Class: rv_plic_reg_prio46
+class rv_plic_reg_prio46 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio46;
+
+ `uvm_object_utils(rv_plic_reg_prio46)
+
+ function new(string name = "rv_plic_reg_prio46",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio46 = dv_base_reg_field::type_id::create("prio46");
+ prio46.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio46
+
+// Class: rv_plic_reg_prio47
+class rv_plic_reg_prio47 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio47;
+
+ `uvm_object_utils(rv_plic_reg_prio47)
+
+ function new(string name = "rv_plic_reg_prio47",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio47 = dv_base_reg_field::type_id::create("prio47");
+ prio47.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio47
+
+// Class: rv_plic_reg_prio48
+class rv_plic_reg_prio48 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio48;
+
+ `uvm_object_utils(rv_plic_reg_prio48)
+
+ function new(string name = "rv_plic_reg_prio48",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio48 = dv_base_reg_field::type_id::create("prio48");
+ prio48.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio48
+
+// Class: rv_plic_reg_prio49
+class rv_plic_reg_prio49 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio49;
+
+ `uvm_object_utils(rv_plic_reg_prio49)
+
+ function new(string name = "rv_plic_reg_prio49",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio49 = dv_base_reg_field::type_id::create("prio49");
+ prio49.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio49
+
+// Class: rv_plic_reg_prio50
+class rv_plic_reg_prio50 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio50;
+
+ `uvm_object_utils(rv_plic_reg_prio50)
+
+ function new(string name = "rv_plic_reg_prio50",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio50 = dv_base_reg_field::type_id::create("prio50");
+ prio50.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio50
+
+// Class: rv_plic_reg_prio51
+class rv_plic_reg_prio51 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio51;
+
+ `uvm_object_utils(rv_plic_reg_prio51)
+
+ function new(string name = "rv_plic_reg_prio51",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio51 = dv_base_reg_field::type_id::create("prio51");
+ prio51.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio51
+
+// Class: rv_plic_reg_prio52
+class rv_plic_reg_prio52 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio52;
+
+ `uvm_object_utils(rv_plic_reg_prio52)
+
+ function new(string name = "rv_plic_reg_prio52",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio52 = dv_base_reg_field::type_id::create("prio52");
+ prio52.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio52
+
+// Class: rv_plic_reg_prio53
+class rv_plic_reg_prio53 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prio53;
+
+ `uvm_object_utils(rv_plic_reg_prio53)
+
+ function new(string name = "rv_plic_reg_prio53",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prio53 = dv_base_reg_field::type_id::create("prio53");
+ prio53.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e25 = dv_base_reg_field::type_id::create("e25");
+ e25.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(25),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e26 = dv_base_reg_field::type_id::create("e26");
+ e26.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(26),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e27 = dv_base_reg_field::type_id::create("e27");
+ e27.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(27),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e28 = dv_base_reg_field::type_id::create("e28");
+ e28.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(28),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e29 = dv_base_reg_field::type_id::create("e29");
+ e29.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(29),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e30 = dv_base_reg_field::type_id::create("e30");
+ e30.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(30),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e31 = dv_base_reg_field::type_id::create("e31");
+ e31.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_plic_reg_prio54
+
+// Class: rv_plic_reg_ie00
+class rv_plic_reg_ie00 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field e0;
+ rand dv_base_reg_field e1;
+ rand dv_base_reg_field e2;
+ rand dv_base_reg_field e3;
+ rand dv_base_reg_field e4;
+ rand dv_base_reg_field e5;
+ rand dv_base_reg_field e6;
+ rand dv_base_reg_field e7;
+ rand dv_base_reg_field e8;
+ rand dv_base_reg_field e9;
+ rand dv_base_reg_field e10;
+ rand dv_base_reg_field e11;
+ rand dv_base_reg_field e12;
+ rand dv_base_reg_field e13;
+ rand dv_base_reg_field e14;
+ rand dv_base_reg_field e15;
+ rand dv_base_reg_field e16;
+ rand dv_base_reg_field e17;
+ rand dv_base_reg_field e18;
+ rand dv_base_reg_field e19;
+ rand dv_base_reg_field e20;
+ rand dv_base_reg_field e21;
+ rand dv_base_reg_field e22;
+ rand dv_base_reg_field e23;
+ rand dv_base_reg_field e24;
+ rand dv_base_reg_field e25;
+ rand dv_base_reg_field e26;
+ rand dv_base_reg_field e27;
+ rand dv_base_reg_field e28;
+ rand dv_base_reg_field e29;
+ rand dv_base_reg_field e30;
+ rand dv_base_reg_field e31;
+
+ `uvm_object_utils(rv_plic_reg_ie00)
+
+ function new(string name = "rv_plic_reg_ie00",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ e0 = dv_base_reg_field::type_id::create("e0");
+ e0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e1 = dv_base_reg_field::type_id::create("e1");
+ e1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e2 = dv_base_reg_field::type_id::create("e2");
+ e2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e3 = dv_base_reg_field::type_id::create("e3");
+ e3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e4 = dv_base_reg_field::type_id::create("e4");
+ e4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e5 = dv_base_reg_field::type_id::create("e5");
+ e5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e6 = dv_base_reg_field::type_id::create("e6");
+ e6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e7 = dv_base_reg_field::type_id::create("e7");
+ e7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(7),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e8 = dv_base_reg_field::type_id::create("e8");
+ e8.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(8),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e9 = dv_base_reg_field::type_id::create("e9");
+ e9.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(9),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e10 = dv_base_reg_field::type_id::create("e10");
+ e10.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(10),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e11 = dv_base_reg_field::type_id::create("e11");
+ e11.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(11),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e12 = dv_base_reg_field::type_id::create("e12");
+ e12.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e13 = dv_base_reg_field::type_id::create("e13");
+ e13.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(13),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e14 = dv_base_reg_field::type_id::create("e14");
+ e14.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(14),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e15 = dv_base_reg_field::type_id::create("e15");
+ e15.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(15),
+ .access("RW"),
+ .volatile(0),
+ .reset(32'h0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ e16 = dv_base_reg_field::type_id::create("e16");
+ e16.configure(
+ .parent(this),
.size(1),
.lsb_pos(16),
.access("RW"),
@@ -8148,84 +8801,7 @@
.size(1),
.lsb_pos(24),
.access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e25 = dv_base_reg_field::type_id::create("e25");
- e25.configure(
- .parent(this),
- .size(1),
- .lsb_pos(25),
- .access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e26 = dv_base_reg_field::type_id::create("e26");
- e26.configure(
- .parent(this),
- .size(1),
- .lsb_pos(26),
- .access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e27 = dv_base_reg_field::type_id::create("e27");
- e27.configure(
- .parent(this),
- .size(1),
- .lsb_pos(27),
- .access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e28 = dv_base_reg_field::type_id::create("e28");
- e28.configure(
- .parent(this),
- .size(1),
- .lsb_pos(28),
- .access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e29 = dv_base_reg_field::type_id::create("e29");
- e29.configure(
- .parent(this),
- .size(1),
- .lsb_pos(29),
- .access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e30 = dv_base_reg_field::type_id::create("e30");
- e30.configure(
- .parent(this),
- .size(1),
- .lsb_pos(30),
- .access("RW"),
- .volatile(0),
- .reset(32'h0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- e31 = dv_base_reg_field::type_id::create("e31");
- e31.configure(
- .parent(this),
- .size(1),
- .lsb_pos(31),
- .access("RW"),
- .volatile(0),
+ .volatile(1),
.reset(32'h0),
.has_reset(1),
.is_rand(1),
@@ -8289,7 +8865,7 @@
.lsb_pos(1),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8300,7 +8876,7 @@
.lsb_pos(2),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8311,7 +8887,7 @@
.lsb_pos(3),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8322,7 +8898,7 @@
.lsb_pos(4),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8333,7 +8909,7 @@
.lsb_pos(5),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8344,7 +8920,7 @@
.lsb_pos(6),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8355,7 +8931,7 @@
.lsb_pos(7),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8366,7 +8942,7 @@
.lsb_pos(8),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8377,7 +8953,7 @@
.lsb_pos(9),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8388,7 +8964,7 @@
.lsb_pos(10),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8399,7 +8975,7 @@
.lsb_pos(11),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8410,7 +8986,7 @@
.lsb_pos(12),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8421,7 +8997,7 @@
.lsb_pos(13),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8432,7 +9008,7 @@
.lsb_pos(14),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8443,7 +9019,7 @@
.lsb_pos(15),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8454,7 +9030,7 @@
.lsb_pos(16),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8465,7 +9041,7 @@
.lsb_pos(17),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8476,7 +9052,7 @@
.lsb_pos(18),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8487,7 +9063,7 @@
.lsb_pos(19),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8498,7 +9074,7 @@
.lsb_pos(20),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8509,7 +9085,7 @@
.lsb_pos(21),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8520,7 +9096,7 @@
.lsb_pos(22),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8550,7 +9126,7 @@
.lsb_pos(0),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8580,7 +9156,7 @@
.lsb_pos(0),
.access("RW"),
.volatile(1),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -8610,7 +9186,7 @@
.lsb_pos(0),
.access("RW"),
.volatile(0),
- .reset(32'h0),
+ .reset(0),
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
@@ -9088,6 +9664,1184 @@
endfunction : build
endclass : rv_plic_reg_block
+// Block: pinmux
+// Class: pinmux_reg_regen
+class pinmux_reg_regen extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field regen;
+
+ `uvm_object_utils(pinmux_reg_regen)
+
+ function new(string name = "pinmux_reg_regen",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ regen = dv_base_reg_field::type_id::create("regen");
+ regen.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_regen
+
+// Class: pinmux_reg_periph_insel0
+class pinmux_reg_periph_insel0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in0;
+ rand dv_base_reg_field in1;
+ rand dv_base_reg_field in2;
+ rand dv_base_reg_field in3;
+ rand dv_base_reg_field in4;
+
+ `uvm_object_utils(pinmux_reg_periph_insel0)
+
+ function new(string name = "pinmux_reg_periph_insel0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in0 = dv_base_reg_field::type_id::create("in0");
+ in0.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in1 = dv_base_reg_field::type_id::create("in1");
+ in1.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in2 = dv_base_reg_field::type_id::create("in2");
+ in2.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in3 = dv_base_reg_field::type_id::create("in3");
+ in3.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in4 = dv_base_reg_field::type_id::create("in4");
+ in4.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel0
+
+// Class: pinmux_reg_periph_insel1
+class pinmux_reg_periph_insel1 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in5;
+ rand dv_base_reg_field in6;
+ rand dv_base_reg_field in7;
+ rand dv_base_reg_field in8;
+ rand dv_base_reg_field in9;
+
+ `uvm_object_utils(pinmux_reg_periph_insel1)
+
+ function new(string name = "pinmux_reg_periph_insel1",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in5 = dv_base_reg_field::type_id::create("in5");
+ in5.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in6 = dv_base_reg_field::type_id::create("in6");
+ in6.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in7 = dv_base_reg_field::type_id::create("in7");
+ in7.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in8 = dv_base_reg_field::type_id::create("in8");
+ in8.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in9 = dv_base_reg_field::type_id::create("in9");
+ in9.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel1
+
+// Class: pinmux_reg_periph_insel2
+class pinmux_reg_periph_insel2 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in10;
+ rand dv_base_reg_field in11;
+ rand dv_base_reg_field in12;
+ rand dv_base_reg_field in13;
+ rand dv_base_reg_field in14;
+
+ `uvm_object_utils(pinmux_reg_periph_insel2)
+
+ function new(string name = "pinmux_reg_periph_insel2",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in10 = dv_base_reg_field::type_id::create("in10");
+ in10.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in11 = dv_base_reg_field::type_id::create("in11");
+ in11.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in12 = dv_base_reg_field::type_id::create("in12");
+ in12.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in13 = dv_base_reg_field::type_id::create("in13");
+ in13.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in14 = dv_base_reg_field::type_id::create("in14");
+ in14.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel2
+
+// Class: pinmux_reg_periph_insel3
+class pinmux_reg_periph_insel3 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in15;
+ rand dv_base_reg_field in16;
+ rand dv_base_reg_field in17;
+ rand dv_base_reg_field in18;
+ rand dv_base_reg_field in19;
+
+ `uvm_object_utils(pinmux_reg_periph_insel3)
+
+ function new(string name = "pinmux_reg_periph_insel3",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in15 = dv_base_reg_field::type_id::create("in15");
+ in15.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in16 = dv_base_reg_field::type_id::create("in16");
+ in16.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in17 = dv_base_reg_field::type_id::create("in17");
+ in17.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in18 = dv_base_reg_field::type_id::create("in18");
+ in18.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in19 = dv_base_reg_field::type_id::create("in19");
+ in19.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel3
+
+// Class: pinmux_reg_periph_insel4
+class pinmux_reg_periph_insel4 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in20;
+ rand dv_base_reg_field in21;
+ rand dv_base_reg_field in22;
+ rand dv_base_reg_field in23;
+ rand dv_base_reg_field in24;
+
+ `uvm_object_utils(pinmux_reg_periph_insel4)
+
+ function new(string name = "pinmux_reg_periph_insel4",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in20 = dv_base_reg_field::type_id::create("in20");
+ in20.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in21 = dv_base_reg_field::type_id::create("in21");
+ in21.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in22 = dv_base_reg_field::type_id::create("in22");
+ in22.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in23 = dv_base_reg_field::type_id::create("in23");
+ in23.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in24 = dv_base_reg_field::type_id::create("in24");
+ in24.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel4
+
+// Class: pinmux_reg_periph_insel5
+class pinmux_reg_periph_insel5 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in25;
+ rand dv_base_reg_field in26;
+ rand dv_base_reg_field in27;
+ rand dv_base_reg_field in28;
+ rand dv_base_reg_field in29;
+
+ `uvm_object_utils(pinmux_reg_periph_insel5)
+
+ function new(string name = "pinmux_reg_periph_insel5",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in25 = dv_base_reg_field::type_id::create("in25");
+ in25.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in26 = dv_base_reg_field::type_id::create("in26");
+ in26.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in27 = dv_base_reg_field::type_id::create("in27");
+ in27.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in28 = dv_base_reg_field::type_id::create("in28");
+ in28.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in29 = dv_base_reg_field::type_id::create("in29");
+ in29.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel5
+
+// Class: pinmux_reg_periph_insel6
+class pinmux_reg_periph_insel6 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field in30;
+ rand dv_base_reg_field in31;
+
+ `uvm_object_utils(pinmux_reg_periph_insel6)
+
+ function new(string name = "pinmux_reg_periph_insel6",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ in30 = dv_base_reg_field::type_id::create("in30");
+ in30.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ in31 = dv_base_reg_field::type_id::create("in31");
+ in31.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_periph_insel6
+
+// Class: pinmux_reg_mio_outsel0
+class pinmux_reg_mio_outsel0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out0;
+ rand dv_base_reg_field out1;
+ rand dv_base_reg_field out2;
+ rand dv_base_reg_field out3;
+ rand dv_base_reg_field out4;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel0)
+
+ function new(string name = "pinmux_reg_mio_outsel0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out0 = dv_base_reg_field::type_id::create("out0");
+ out0.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out1 = dv_base_reg_field::type_id::create("out1");
+ out1.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out2 = dv_base_reg_field::type_id::create("out2");
+ out2.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out3 = dv_base_reg_field::type_id::create("out3");
+ out3.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out4 = dv_base_reg_field::type_id::create("out4");
+ out4.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel0
+
+// Class: pinmux_reg_mio_outsel1
+class pinmux_reg_mio_outsel1 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out5;
+ rand dv_base_reg_field out6;
+ rand dv_base_reg_field out7;
+ rand dv_base_reg_field out8;
+ rand dv_base_reg_field out9;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel1)
+
+ function new(string name = "pinmux_reg_mio_outsel1",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out5 = dv_base_reg_field::type_id::create("out5");
+ out5.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out6 = dv_base_reg_field::type_id::create("out6");
+ out6.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out7 = dv_base_reg_field::type_id::create("out7");
+ out7.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out8 = dv_base_reg_field::type_id::create("out8");
+ out8.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out9 = dv_base_reg_field::type_id::create("out9");
+ out9.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel1
+
+// Class: pinmux_reg_mio_outsel2
+class pinmux_reg_mio_outsel2 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out10;
+ rand dv_base_reg_field out11;
+ rand dv_base_reg_field out12;
+ rand dv_base_reg_field out13;
+ rand dv_base_reg_field out14;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel2)
+
+ function new(string name = "pinmux_reg_mio_outsel2",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out10 = dv_base_reg_field::type_id::create("out10");
+ out10.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out11 = dv_base_reg_field::type_id::create("out11");
+ out11.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out12 = dv_base_reg_field::type_id::create("out12");
+ out12.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out13 = dv_base_reg_field::type_id::create("out13");
+ out13.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out14 = dv_base_reg_field::type_id::create("out14");
+ out14.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel2
+
+// Class: pinmux_reg_mio_outsel3
+class pinmux_reg_mio_outsel3 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out15;
+ rand dv_base_reg_field out16;
+ rand dv_base_reg_field out17;
+ rand dv_base_reg_field out18;
+ rand dv_base_reg_field out19;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel3)
+
+ function new(string name = "pinmux_reg_mio_outsel3",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out15 = dv_base_reg_field::type_id::create("out15");
+ out15.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out16 = dv_base_reg_field::type_id::create("out16");
+ out16.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out17 = dv_base_reg_field::type_id::create("out17");
+ out17.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out18 = dv_base_reg_field::type_id::create("out18");
+ out18.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out19 = dv_base_reg_field::type_id::create("out19");
+ out19.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel3
+
+// Class: pinmux_reg_mio_outsel4
+class pinmux_reg_mio_outsel4 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out20;
+ rand dv_base_reg_field out21;
+ rand dv_base_reg_field out22;
+ rand dv_base_reg_field out23;
+ rand dv_base_reg_field out24;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel4)
+
+ function new(string name = "pinmux_reg_mio_outsel4",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out20 = dv_base_reg_field::type_id::create("out20");
+ out20.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out21 = dv_base_reg_field::type_id::create("out21");
+ out21.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out22 = dv_base_reg_field::type_id::create("out22");
+ out22.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out23 = dv_base_reg_field::type_id::create("out23");
+ out23.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out24 = dv_base_reg_field::type_id::create("out24");
+ out24.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel4
+
+// Class: pinmux_reg_mio_outsel5
+class pinmux_reg_mio_outsel5 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out25;
+ rand dv_base_reg_field out26;
+ rand dv_base_reg_field out27;
+ rand dv_base_reg_field out28;
+ rand dv_base_reg_field out29;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel5)
+
+ function new(string name = "pinmux_reg_mio_outsel5",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out25 = dv_base_reg_field::type_id::create("out25");
+ out25.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out26 = dv_base_reg_field::type_id::create("out26");
+ out26.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out27 = dv_base_reg_field::type_id::create("out27");
+ out27.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(12),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out28 = dv_base_reg_field::type_id::create("out28");
+ out28.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(18),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out29 = dv_base_reg_field::type_id::create("out29");
+ out29.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(24),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel5
+
+// Class: pinmux_reg_mio_outsel6
+class pinmux_reg_mio_outsel6 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field out30;
+ rand dv_base_reg_field out31;
+
+ `uvm_object_utils(pinmux_reg_mio_outsel6)
+
+ function new(string name = "pinmux_reg_mio_outsel6",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ out30 = dv_base_reg_field::type_id::create("out30");
+ out30.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ out31 = dv_base_reg_field::type_id::create("out31");
+ out31.configure(
+ .parent(this),
+ .size(6),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(2),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : pinmux_reg_mio_outsel6
+
+// Class: pinmux_reg_block
+class pinmux_reg_block extends dv_base_reg_block;
+ // registers
+ rand pinmux_reg_regen regen;
+ rand pinmux_reg_periph_insel0 periph_insel0;
+ rand pinmux_reg_periph_insel1 periph_insel1;
+ rand pinmux_reg_periph_insel2 periph_insel2;
+ rand pinmux_reg_periph_insel3 periph_insel3;
+ rand pinmux_reg_periph_insel4 periph_insel4;
+ rand pinmux_reg_periph_insel5 periph_insel5;
+ rand pinmux_reg_periph_insel6 periph_insel6;
+ rand pinmux_reg_mio_outsel0 mio_outsel0;
+ rand pinmux_reg_mio_outsel1 mio_outsel1;
+ rand pinmux_reg_mio_outsel2 mio_outsel2;
+ rand pinmux_reg_mio_outsel3 mio_outsel3;
+ rand pinmux_reg_mio_outsel4 mio_outsel4;
+ rand pinmux_reg_mio_outsel5 mio_outsel5;
+ rand pinmux_reg_mio_outsel6 mio_outsel6;
+
+ `uvm_object_utils(pinmux_reg_block)
+
+ function new(string name = "pinmux_reg_block",
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, has_coverage);
+ endfunction : new
+
+ virtual function void build(uvm_reg_addr_t base_addr);
+ // create default map
+ this.default_map = create_map(.name("default_map"),
+ .base_addr(base_addr),
+ .n_bytes(4),
+ .endian(UVM_LITTLE_ENDIAN));
+
+ // create registers
+ regen = pinmux_reg_regen::type_id::create("regen");
+ regen.configure(.blk_parent(this));
+ regen.build();
+ default_map.add_reg(.rg(regen),
+ .offset(32'h0),
+ .rights("RW"));
+ periph_insel0 = pinmux_reg_periph_insel0::type_id::create("periph_insel0");
+ periph_insel0.configure(.blk_parent(this));
+ periph_insel0.build();
+ default_map.add_reg(.rg(periph_insel0),
+ .offset(32'h4),
+ .rights("RW"));
+ periph_insel1 = pinmux_reg_periph_insel1::type_id::create("periph_insel1");
+ periph_insel1.configure(.blk_parent(this));
+ periph_insel1.build();
+ default_map.add_reg(.rg(periph_insel1),
+ .offset(32'h8),
+ .rights("RW"));
+ periph_insel2 = pinmux_reg_periph_insel2::type_id::create("periph_insel2");
+ periph_insel2.configure(.blk_parent(this));
+ periph_insel2.build();
+ default_map.add_reg(.rg(periph_insel2),
+ .offset(32'hc),
+ .rights("RW"));
+ periph_insel3 = pinmux_reg_periph_insel3::type_id::create("periph_insel3");
+ periph_insel3.configure(.blk_parent(this));
+ periph_insel3.build();
+ default_map.add_reg(.rg(periph_insel3),
+ .offset(32'h10),
+ .rights("RW"));
+ periph_insel4 = pinmux_reg_periph_insel4::type_id::create("periph_insel4");
+ periph_insel4.configure(.blk_parent(this));
+ periph_insel4.build();
+ default_map.add_reg(.rg(periph_insel4),
+ .offset(32'h14),
+ .rights("RW"));
+ periph_insel5 = pinmux_reg_periph_insel5::type_id::create("periph_insel5");
+ periph_insel5.configure(.blk_parent(this));
+ periph_insel5.build();
+ default_map.add_reg(.rg(periph_insel5),
+ .offset(32'h18),
+ .rights("RW"));
+ periph_insel6 = pinmux_reg_periph_insel6::type_id::create("periph_insel6");
+ periph_insel6.configure(.blk_parent(this));
+ periph_insel6.build();
+ default_map.add_reg(.rg(periph_insel6),
+ .offset(32'h1c),
+ .rights("RW"));
+ mio_outsel0 = pinmux_reg_mio_outsel0::type_id::create("mio_outsel0");
+ mio_outsel0.configure(.blk_parent(this));
+ mio_outsel0.build();
+ default_map.add_reg(.rg(mio_outsel0),
+ .offset(32'h20),
+ .rights("RW"));
+ mio_outsel1 = pinmux_reg_mio_outsel1::type_id::create("mio_outsel1");
+ mio_outsel1.configure(.blk_parent(this));
+ mio_outsel1.build();
+ default_map.add_reg(.rg(mio_outsel1),
+ .offset(32'h24),
+ .rights("RW"));
+ mio_outsel2 = pinmux_reg_mio_outsel2::type_id::create("mio_outsel2");
+ mio_outsel2.configure(.blk_parent(this));
+ mio_outsel2.build();
+ default_map.add_reg(.rg(mio_outsel2),
+ .offset(32'h28),
+ .rights("RW"));
+ mio_outsel3 = pinmux_reg_mio_outsel3::type_id::create("mio_outsel3");
+ mio_outsel3.configure(.blk_parent(this));
+ mio_outsel3.build();
+ default_map.add_reg(.rg(mio_outsel3),
+ .offset(32'h2c),
+ .rights("RW"));
+ threshold0 = rv_plic_reg_threshold0::type_id::create("threshold0");
+ threshold0.configure(.blk_parent(this));
+ threshold0.build();
+ default_map.add_reg(.rg(threshold0),
+ .offset(32'h108),
+ .rights("RW"));
+ cc0 = rv_plic_reg_cc0::type_id::create("cc0");
+ cc0.configure(.blk_parent(this));
+ cc0.build();
+ default_map.add_reg(.rg(cc0),
+ .offset(32'h10c),
+ .rights("RW"));
+ msip0 = rv_plic_reg_msip0::type_id::create("msip0");
+ msip0.configure(.blk_parent(this));
+ msip0.build();
+ default_map.add_reg(.rg(msip0),
+ .offset(32'h110),
+ .rights("RW"));
+ endfunction : build
+
+endclass : rv_plic_reg_block
`endif
@@ -11193,6 +12947,7 @@
rand spi_device_reg_block spi_device;
rand flash_ctrl_reg_block flash_ctrl;
rand rv_timer_reg_block rv_timer;
+ rand aes_reg_block aes;
rand rv_plic_reg_block rv_plic;
rand aes_reg_block aes;
rand hmac_reg_block hmac;
@@ -11241,6 +12996,11 @@
rv_timer.build(.base_addr(base_addr + 32'h40080000));
default_map.add_submap(.child_map(rv_timer.default_map),
.offset(base_addr + 32'h40080000));
+ aes = aes_reg_block::type_id::create("aes");
+ aes.configure(.parent(this));
+ aes.build(.base_addr(base_addr + 32'h40110000));
+ default_map.add_submap(.child_map(aes.default_map),
+ .offset(base_addr + 32'h40110000));
rv_plic = rv_plic_reg_block::type_id::create("rv_plic");
rv_plic.configure(.parent(this));
rv_plic.build(.base_addr(base_addr + 32'h40090000));
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
new file mode 100644
index 0000000..1669106
--- /dev/null
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -0,0 +1,103 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson -o hw/top_earlgrey/
+
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+# PINMUX register template
+#
+# Parameter (given by python tool)
+# - n_periph_in: Number of peripheral inputs
+# - n_periph_out: Number of peripheral outputs
+# - n_mio_pads: Number of muxed IO pads
+#
+{
+ name: "PINMUX",
+ clock_primary: "clk_i",
+ bus_device: "tlul",
+ regwidth: "32",
+ param_list: [
+ { name: "NPeriphIn",
+ desc: "Number of peripheral inputs",
+ type: "int",
+ default: "32",
+ local: "true"
+ },
+ { name: "NPeriphOut",
+ desc: "Number of peripheral outputs",
+ type: "int",
+ default: "32",
+ local: "true"
+ },
+ { name: "NMioPads",
+ desc: "Number of muxed IO pads",
+ type: "int",
+ default: "32",
+ local: "true"
+ },
+ ],
+ registers: [
+ { name: "REGEN",
+ desc: '''
+ Register write enable for all control registers.
+ ''',
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ {
+ bits: "0",
+ desc: ''' When true, all configuration registers can be modified.
+ When false, they become read-only. Defaults true, write zero to clear.
+ '''
+ resval: 1,
+ },
+ ]
+ },
+# inputs
+ { multireg: { name: "PERIPH_INSEL",
+ desc: "Mux select for peripheral inputs.",
+ count: "NPeriphIn",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ cname: "IN",
+ fields: [
+ { bits: "5:0",
+ name: "IN",
+ desc: '''
+ 0: tie constantly to zero, 1: tie constantly to 1.
+ >=2: MIO pads (i.e., add 2 to the native MIO pad index).
+ '''
+ resval: 0
+ }
+ ]
+ }
+ },
+# outputs
+ { multireg: { name: "MIO_OUTSEL",
+ desc: "Mux select for MIO outputs.",
+ count: "NMioPads",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "REGEN",
+ cname: "OUT",
+ fields: [
+ { bits: "5:0",
+ name: "OUT",
+ desc: '''
+ 0: tie constantly to zero, 1: tie constantly to 1. 2: high-Z
+ >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).
+ '''
+ resval: 2
+ }
+ ]
+ }
+ },
+ ],
+}
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
new file mode 100644
index 0000000..1357aaa
--- /dev/null
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -0,0 +1,96 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Package auto-generated by `reggen` containing data structure
+
+package pinmux_reg_pkg;
+
+ // Param list
+ localparam int NPeriphIn = 32;
+ localparam int NPeriphOut = 32;
+ localparam int NMioPads = 32;
+
+/////////////////////////////////////////////////////////////////////
+// Typedefs for multiregs
+/////////////////////////////////////////////////////////////////////
+
+typedef struct packed {
+ logic [5:0] q;
+} pinmux_reg2hw_periph_insel_mreg_t;
+typedef struct packed {
+ logic [5:0] q;
+} pinmux_reg2hw_mio_outsel_mreg_t;
+
+
+/////////////////////////////////////////////////////////////////////
+// Register to internal design logic
+/////////////////////////////////////////////////////////////////////
+
+typedef struct packed {
+ pinmux_reg2hw_periph_insel_mreg_t [31:0] periph_insel; // [383:192]
+ pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [191:0]
+} pinmux_reg2hw_t;
+
+/////////////////////////////////////////////////////////////////////
+// Internal design logic to register
+/////////////////////////////////////////////////////////////////////
+
+
+ // Register Address
+ parameter PINMUX_REGEN_OFFSET = 6'h 0;
+ parameter PINMUX_PERIPH_INSEL0_OFFSET = 6'h 4;
+ parameter PINMUX_PERIPH_INSEL1_OFFSET = 6'h 8;
+ parameter PINMUX_PERIPH_INSEL2_OFFSET = 6'h c;
+ parameter PINMUX_PERIPH_INSEL3_OFFSET = 6'h 10;
+ parameter PINMUX_PERIPH_INSEL4_OFFSET = 6'h 14;
+ parameter PINMUX_PERIPH_INSEL5_OFFSET = 6'h 18;
+ parameter PINMUX_PERIPH_INSEL6_OFFSET = 6'h 1c;
+ parameter PINMUX_MIO_OUTSEL0_OFFSET = 6'h 20;
+ parameter PINMUX_MIO_OUTSEL1_OFFSET = 6'h 24;
+ parameter PINMUX_MIO_OUTSEL2_OFFSET = 6'h 28;
+ parameter PINMUX_MIO_OUTSEL3_OFFSET = 6'h 2c;
+ parameter PINMUX_MIO_OUTSEL4_OFFSET = 6'h 30;
+ parameter PINMUX_MIO_OUTSEL5_OFFSET = 6'h 34;
+ parameter PINMUX_MIO_OUTSEL6_OFFSET = 6'h 38;
+
+
+ // Register Index
+ typedef enum int {
+ PINMUX_REGEN,
+ PINMUX_PERIPH_INSEL0,
+ PINMUX_PERIPH_INSEL1,
+ PINMUX_PERIPH_INSEL2,
+ PINMUX_PERIPH_INSEL3,
+ PINMUX_PERIPH_INSEL4,
+ PINMUX_PERIPH_INSEL5,
+ PINMUX_PERIPH_INSEL6,
+ PINMUX_MIO_OUTSEL0,
+ PINMUX_MIO_OUTSEL1,
+ PINMUX_MIO_OUTSEL2,
+ PINMUX_MIO_OUTSEL3,
+ PINMUX_MIO_OUTSEL4,
+ PINMUX_MIO_OUTSEL5,
+ PINMUX_MIO_OUTSEL6
+ } pinmux_id_e;
+
+ // Register width information to check illegal writes
+ localparam logic [3:0] PINMUX_PERMIT [15] = '{
+ 4'b 0001, // index[ 0] PINMUX_REGEN
+ 4'b 1111, // index[ 1] PINMUX_PERIPH_INSEL0
+ 4'b 1111, // index[ 2] PINMUX_PERIPH_INSEL1
+ 4'b 1111, // index[ 3] PINMUX_PERIPH_INSEL2
+ 4'b 1111, // index[ 4] PINMUX_PERIPH_INSEL3
+ 4'b 1111, // index[ 5] PINMUX_PERIPH_INSEL4
+ 4'b 1111, // index[ 6] PINMUX_PERIPH_INSEL5
+ 4'b 0011, // index[ 7] PINMUX_PERIPH_INSEL6
+ 4'b 1111, // index[ 8] PINMUX_MIO_OUTSEL0
+ 4'b 1111, // index[ 9] PINMUX_MIO_OUTSEL1
+ 4'b 1111, // index[10] PINMUX_MIO_OUTSEL2
+ 4'b 1111, // index[11] PINMUX_MIO_OUTSEL3
+ 4'b 1111, // index[12] PINMUX_MIO_OUTSEL4
+ 4'b 1111, // index[13] PINMUX_MIO_OUTSEL5
+ 4'b 0011 // index[14] PINMUX_MIO_OUTSEL6
+ };
+endpackage
+
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
new file mode 100644
index 0000000..4cd0466
--- /dev/null
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -0,0 +1,2374 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+module pinmux_reg_top (
+ input clk_i,
+ input rst_ni,
+
+ // Below Regster interface can be changed
+ input tlul_pkg::tl_h2d_t tl_i,
+ output tlul_pkg::tl_d2h_t tl_o,
+ // To HW
+ output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
+
+ // Config
+ input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+ import pinmux_reg_pkg::* ;
+
+ localparam AW = 6;
+ localparam DW = 32;
+ localparam DBW = DW/8; // Byte Width
+
+ // register signals
+ logic reg_we;
+ logic reg_re;
+ logic [AW-1:0] reg_addr;
+ logic [DW-1:0] reg_wdata;
+ logic [DBW-1:0] reg_be;
+ logic [DW-1:0] reg_rdata;
+ logic reg_error;
+
+ logic addrmiss, wr_err;
+
+ logic [DW-1:0] reg_rdata_next;
+
+ tlul_pkg::tl_h2d_t tl_reg_h2d;
+ tlul_pkg::tl_d2h_t tl_reg_d2h;
+
+ assign tl_reg_h2d = tl_i;
+ assign tl_o = tl_reg_d2h;
+
+ tlul_adapter_reg #(
+ .RegAw(AW),
+ .RegDw(DW)
+ ) u_reg_if (
+ .clk_i,
+ .rst_ni,
+
+ .tl_i (tl_reg_h2d),
+ .tl_o (tl_reg_d2h),
+
+ .we_o (reg_we),
+ .re_o (reg_re),
+ .addr_o (reg_addr),
+ .wdata_o (reg_wdata),
+ .be_o (reg_be),
+ .rdata_i (reg_rdata),
+ .error_i (reg_error)
+ );
+
+ assign reg_rdata = reg_rdata_next ;
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
+
+ // Define SW related signals
+ // Format: <reg>_<field>_{wd|we|qs}
+ // or <reg>_{wd|we|qs} if field == 1 or 0
+ logic regen_qs;
+ logic regen_wd;
+ logic regen_we;
+ logic [5:0] periph_insel0_in0_qs;
+ logic [5:0] periph_insel0_in0_wd;
+ logic periph_insel0_in0_we;
+ logic [5:0] periph_insel0_in1_qs;
+ logic [5:0] periph_insel0_in1_wd;
+ logic periph_insel0_in1_we;
+ logic [5:0] periph_insel0_in2_qs;
+ logic [5:0] periph_insel0_in2_wd;
+ logic periph_insel0_in2_we;
+ logic [5:0] periph_insel0_in3_qs;
+ logic [5:0] periph_insel0_in3_wd;
+ logic periph_insel0_in3_we;
+ logic [5:0] periph_insel0_in4_qs;
+ logic [5:0] periph_insel0_in4_wd;
+ logic periph_insel0_in4_we;
+ logic [5:0] periph_insel1_in5_qs;
+ logic [5:0] periph_insel1_in5_wd;
+ logic periph_insel1_in5_we;
+ logic [5:0] periph_insel1_in6_qs;
+ logic [5:0] periph_insel1_in6_wd;
+ logic periph_insel1_in6_we;
+ logic [5:0] periph_insel1_in7_qs;
+ logic [5:0] periph_insel1_in7_wd;
+ logic periph_insel1_in7_we;
+ logic [5:0] periph_insel1_in8_qs;
+ logic [5:0] periph_insel1_in8_wd;
+ logic periph_insel1_in8_we;
+ logic [5:0] periph_insel1_in9_qs;
+ logic [5:0] periph_insel1_in9_wd;
+ logic periph_insel1_in9_we;
+ logic [5:0] periph_insel2_in10_qs;
+ logic [5:0] periph_insel2_in10_wd;
+ logic periph_insel2_in10_we;
+ logic [5:0] periph_insel2_in11_qs;
+ logic [5:0] periph_insel2_in11_wd;
+ logic periph_insel2_in11_we;
+ logic [5:0] periph_insel2_in12_qs;
+ logic [5:0] periph_insel2_in12_wd;
+ logic periph_insel2_in12_we;
+ logic [5:0] periph_insel2_in13_qs;
+ logic [5:0] periph_insel2_in13_wd;
+ logic periph_insel2_in13_we;
+ logic [5:0] periph_insel2_in14_qs;
+ logic [5:0] periph_insel2_in14_wd;
+ logic periph_insel2_in14_we;
+ logic [5:0] periph_insel3_in15_qs;
+ logic [5:0] periph_insel3_in15_wd;
+ logic periph_insel3_in15_we;
+ logic [5:0] periph_insel3_in16_qs;
+ logic [5:0] periph_insel3_in16_wd;
+ logic periph_insel3_in16_we;
+ logic [5:0] periph_insel3_in17_qs;
+ logic [5:0] periph_insel3_in17_wd;
+ logic periph_insel3_in17_we;
+ logic [5:0] periph_insel3_in18_qs;
+ logic [5:0] periph_insel3_in18_wd;
+ logic periph_insel3_in18_we;
+ logic [5:0] periph_insel3_in19_qs;
+ logic [5:0] periph_insel3_in19_wd;
+ logic periph_insel3_in19_we;
+ logic [5:0] periph_insel4_in20_qs;
+ logic [5:0] periph_insel4_in20_wd;
+ logic periph_insel4_in20_we;
+ logic [5:0] periph_insel4_in21_qs;
+ logic [5:0] periph_insel4_in21_wd;
+ logic periph_insel4_in21_we;
+ logic [5:0] periph_insel4_in22_qs;
+ logic [5:0] periph_insel4_in22_wd;
+ logic periph_insel4_in22_we;
+ logic [5:0] periph_insel4_in23_qs;
+ logic [5:0] periph_insel4_in23_wd;
+ logic periph_insel4_in23_we;
+ logic [5:0] periph_insel4_in24_qs;
+ logic [5:0] periph_insel4_in24_wd;
+ logic periph_insel4_in24_we;
+ logic [5:0] periph_insel5_in25_qs;
+ logic [5:0] periph_insel5_in25_wd;
+ logic periph_insel5_in25_we;
+ logic [5:0] periph_insel5_in26_qs;
+ logic [5:0] periph_insel5_in26_wd;
+ logic periph_insel5_in26_we;
+ logic [5:0] periph_insel5_in27_qs;
+ logic [5:0] periph_insel5_in27_wd;
+ logic periph_insel5_in27_we;
+ logic [5:0] periph_insel5_in28_qs;
+ logic [5:0] periph_insel5_in28_wd;
+ logic periph_insel5_in28_we;
+ logic [5:0] periph_insel5_in29_qs;
+ logic [5:0] periph_insel5_in29_wd;
+ logic periph_insel5_in29_we;
+ logic [5:0] periph_insel6_in30_qs;
+ logic [5:0] periph_insel6_in30_wd;
+ logic periph_insel6_in30_we;
+ logic [5:0] periph_insel6_in31_qs;
+ logic [5:0] periph_insel6_in31_wd;
+ logic periph_insel6_in31_we;
+ logic [5:0] mio_outsel0_out0_qs;
+ logic [5:0] mio_outsel0_out0_wd;
+ logic mio_outsel0_out0_we;
+ logic [5:0] mio_outsel0_out1_qs;
+ logic [5:0] mio_outsel0_out1_wd;
+ logic mio_outsel0_out1_we;
+ logic [5:0] mio_outsel0_out2_qs;
+ logic [5:0] mio_outsel0_out2_wd;
+ logic mio_outsel0_out2_we;
+ logic [5:0] mio_outsel0_out3_qs;
+ logic [5:0] mio_outsel0_out3_wd;
+ logic mio_outsel0_out3_we;
+ logic [5:0] mio_outsel0_out4_qs;
+ logic [5:0] mio_outsel0_out4_wd;
+ logic mio_outsel0_out4_we;
+ logic [5:0] mio_outsel1_out5_qs;
+ logic [5:0] mio_outsel1_out5_wd;
+ logic mio_outsel1_out5_we;
+ logic [5:0] mio_outsel1_out6_qs;
+ logic [5:0] mio_outsel1_out6_wd;
+ logic mio_outsel1_out6_we;
+ logic [5:0] mio_outsel1_out7_qs;
+ logic [5:0] mio_outsel1_out7_wd;
+ logic mio_outsel1_out7_we;
+ logic [5:0] mio_outsel1_out8_qs;
+ logic [5:0] mio_outsel1_out8_wd;
+ logic mio_outsel1_out8_we;
+ logic [5:0] mio_outsel1_out9_qs;
+ logic [5:0] mio_outsel1_out9_wd;
+ logic mio_outsel1_out9_we;
+ logic [5:0] mio_outsel2_out10_qs;
+ logic [5:0] mio_outsel2_out10_wd;
+ logic mio_outsel2_out10_we;
+ logic [5:0] mio_outsel2_out11_qs;
+ logic [5:0] mio_outsel2_out11_wd;
+ logic mio_outsel2_out11_we;
+ logic [5:0] mio_outsel2_out12_qs;
+ logic [5:0] mio_outsel2_out12_wd;
+ logic mio_outsel2_out12_we;
+ logic [5:0] mio_outsel2_out13_qs;
+ logic [5:0] mio_outsel2_out13_wd;
+ logic mio_outsel2_out13_we;
+ logic [5:0] mio_outsel2_out14_qs;
+ logic [5:0] mio_outsel2_out14_wd;
+ logic mio_outsel2_out14_we;
+ logic [5:0] mio_outsel3_out15_qs;
+ logic [5:0] mio_outsel3_out15_wd;
+ logic mio_outsel3_out15_we;
+ logic [5:0] mio_outsel3_out16_qs;
+ logic [5:0] mio_outsel3_out16_wd;
+ logic mio_outsel3_out16_we;
+ logic [5:0] mio_outsel3_out17_qs;
+ logic [5:0] mio_outsel3_out17_wd;
+ logic mio_outsel3_out17_we;
+ logic [5:0] mio_outsel3_out18_qs;
+ logic [5:0] mio_outsel3_out18_wd;
+ logic mio_outsel3_out18_we;
+ logic [5:0] mio_outsel3_out19_qs;
+ logic [5:0] mio_outsel3_out19_wd;
+ logic mio_outsel3_out19_we;
+ logic [5:0] mio_outsel4_out20_qs;
+ logic [5:0] mio_outsel4_out20_wd;
+ logic mio_outsel4_out20_we;
+ logic [5:0] mio_outsel4_out21_qs;
+ logic [5:0] mio_outsel4_out21_wd;
+ logic mio_outsel4_out21_we;
+ logic [5:0] mio_outsel4_out22_qs;
+ logic [5:0] mio_outsel4_out22_wd;
+ logic mio_outsel4_out22_we;
+ logic [5:0] mio_outsel4_out23_qs;
+ logic [5:0] mio_outsel4_out23_wd;
+ logic mio_outsel4_out23_we;
+ logic [5:0] mio_outsel4_out24_qs;
+ logic [5:0] mio_outsel4_out24_wd;
+ logic mio_outsel4_out24_we;
+ logic [5:0] mio_outsel5_out25_qs;
+ logic [5:0] mio_outsel5_out25_wd;
+ logic mio_outsel5_out25_we;
+ logic [5:0] mio_outsel5_out26_qs;
+ logic [5:0] mio_outsel5_out26_wd;
+ logic mio_outsel5_out26_we;
+ logic [5:0] mio_outsel5_out27_qs;
+ logic [5:0] mio_outsel5_out27_wd;
+ logic mio_outsel5_out27_we;
+ logic [5:0] mio_outsel5_out28_qs;
+ logic [5:0] mio_outsel5_out28_wd;
+ logic mio_outsel5_out28_we;
+ logic [5:0] mio_outsel5_out29_qs;
+ logic [5:0] mio_outsel5_out29_wd;
+ logic mio_outsel5_out29_we;
+ logic [5:0] mio_outsel6_out30_qs;
+ logic [5:0] mio_outsel6_out30_wd;
+ logic mio_outsel6_out30_we;
+ logic [5:0] mio_outsel6_out31_qs;
+ logic [5:0] mio_outsel6_out31_wd;
+ logic mio_outsel6_out31_we;
+
+ // Register instances
+ // R[regen]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_regen (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (regen_we),
+ .wd (regen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (regen_qs)
+ );
+
+
+
+ // Subregister 0 of Multireg periph_insel
+ // R[periph_insel0]: V(False)
+
+ // F[in0]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel0_in0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel0_in0_we & regen_qs),
+ .wd (periph_insel0_in0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[0].q ),
+
+ // to register interface (read)
+ .qs (periph_insel0_in0_qs)
+ );
+
+
+ // F[in1]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel0_in1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel0_in1_we & regen_qs),
+ .wd (periph_insel0_in1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[1].q ),
+
+ // to register interface (read)
+ .qs (periph_insel0_in1_qs)
+ );
+
+
+ // F[in2]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel0_in2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel0_in2_we & regen_qs),
+ .wd (periph_insel0_in2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[2].q ),
+
+ // to register interface (read)
+ .qs (periph_insel0_in2_qs)
+ );
+
+
+ // F[in3]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel0_in3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel0_in3_we & regen_qs),
+ .wd (periph_insel0_in3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[3].q ),
+
+ // to register interface (read)
+ .qs (periph_insel0_in3_qs)
+ );
+
+
+ // F[in4]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel0_in4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel0_in4_we & regen_qs),
+ .wd (periph_insel0_in4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[4].q ),
+
+ // to register interface (read)
+ .qs (periph_insel0_in4_qs)
+ );
+
+
+ // Subregister 5 of Multireg periph_insel
+ // R[periph_insel1]: V(False)
+
+ // F[in5]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel1_in5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel1_in5_we & regen_qs),
+ .wd (periph_insel1_in5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[5].q ),
+
+ // to register interface (read)
+ .qs (periph_insel1_in5_qs)
+ );
+
+
+ // F[in6]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel1_in6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel1_in6_we & regen_qs),
+ .wd (periph_insel1_in6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[6].q ),
+
+ // to register interface (read)
+ .qs (periph_insel1_in6_qs)
+ );
+
+
+ // F[in7]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel1_in7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel1_in7_we & regen_qs),
+ .wd (periph_insel1_in7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[7].q ),
+
+ // to register interface (read)
+ .qs (periph_insel1_in7_qs)
+ );
+
+
+ // F[in8]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel1_in8 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel1_in8_we & regen_qs),
+ .wd (periph_insel1_in8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[8].q ),
+
+ // to register interface (read)
+ .qs (periph_insel1_in8_qs)
+ );
+
+
+ // F[in9]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel1_in9 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel1_in9_we & regen_qs),
+ .wd (periph_insel1_in9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[9].q ),
+
+ // to register interface (read)
+ .qs (periph_insel1_in9_qs)
+ );
+
+
+ // Subregister 10 of Multireg periph_insel
+ // R[periph_insel2]: V(False)
+
+ // F[in10]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel2_in10 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel2_in10_we & regen_qs),
+ .wd (periph_insel2_in10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[10].q ),
+
+ // to register interface (read)
+ .qs (periph_insel2_in10_qs)
+ );
+
+
+ // F[in11]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel2_in11 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel2_in11_we & regen_qs),
+ .wd (periph_insel2_in11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[11].q ),
+
+ // to register interface (read)
+ .qs (periph_insel2_in11_qs)
+ );
+
+
+ // F[in12]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel2_in12 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel2_in12_we & regen_qs),
+ .wd (periph_insel2_in12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[12].q ),
+
+ // to register interface (read)
+ .qs (periph_insel2_in12_qs)
+ );
+
+
+ // F[in13]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel2_in13 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel2_in13_we & regen_qs),
+ .wd (periph_insel2_in13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[13].q ),
+
+ // to register interface (read)
+ .qs (periph_insel2_in13_qs)
+ );
+
+
+ // F[in14]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel2_in14 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel2_in14_we & regen_qs),
+ .wd (periph_insel2_in14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[14].q ),
+
+ // to register interface (read)
+ .qs (periph_insel2_in14_qs)
+ );
+
+
+ // Subregister 15 of Multireg periph_insel
+ // R[periph_insel3]: V(False)
+
+ // F[in15]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel3_in15 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel3_in15_we & regen_qs),
+ .wd (periph_insel3_in15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[15].q ),
+
+ // to register interface (read)
+ .qs (periph_insel3_in15_qs)
+ );
+
+
+ // F[in16]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel3_in16 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel3_in16_we & regen_qs),
+ .wd (periph_insel3_in16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[16].q ),
+
+ // to register interface (read)
+ .qs (periph_insel3_in16_qs)
+ );
+
+
+ // F[in17]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel3_in17 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel3_in17_we & regen_qs),
+ .wd (periph_insel3_in17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[17].q ),
+
+ // to register interface (read)
+ .qs (periph_insel3_in17_qs)
+ );
+
+
+ // F[in18]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel3_in18 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel3_in18_we & regen_qs),
+ .wd (periph_insel3_in18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[18].q ),
+
+ // to register interface (read)
+ .qs (periph_insel3_in18_qs)
+ );
+
+
+ // F[in19]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel3_in19 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel3_in19_we & regen_qs),
+ .wd (periph_insel3_in19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[19].q ),
+
+ // to register interface (read)
+ .qs (periph_insel3_in19_qs)
+ );
+
+
+ // Subregister 20 of Multireg periph_insel
+ // R[periph_insel4]: V(False)
+
+ // F[in20]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel4_in20 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel4_in20_we & regen_qs),
+ .wd (periph_insel4_in20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[20].q ),
+
+ // to register interface (read)
+ .qs (periph_insel4_in20_qs)
+ );
+
+
+ // F[in21]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel4_in21 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel4_in21_we & regen_qs),
+ .wd (periph_insel4_in21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[21].q ),
+
+ // to register interface (read)
+ .qs (periph_insel4_in21_qs)
+ );
+
+
+ // F[in22]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel4_in22 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel4_in22_we & regen_qs),
+ .wd (periph_insel4_in22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[22].q ),
+
+ // to register interface (read)
+ .qs (periph_insel4_in22_qs)
+ );
+
+
+ // F[in23]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel4_in23 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel4_in23_we & regen_qs),
+ .wd (periph_insel4_in23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[23].q ),
+
+ // to register interface (read)
+ .qs (periph_insel4_in23_qs)
+ );
+
+
+ // F[in24]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel4_in24 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel4_in24_we & regen_qs),
+ .wd (periph_insel4_in24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[24].q ),
+
+ // to register interface (read)
+ .qs (periph_insel4_in24_qs)
+ );
+
+
+ // Subregister 25 of Multireg periph_insel
+ // R[periph_insel5]: V(False)
+
+ // F[in25]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel5_in25 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel5_in25_we & regen_qs),
+ .wd (periph_insel5_in25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[25].q ),
+
+ // to register interface (read)
+ .qs (periph_insel5_in25_qs)
+ );
+
+
+ // F[in26]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel5_in26 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel5_in26_we & regen_qs),
+ .wd (periph_insel5_in26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[26].q ),
+
+ // to register interface (read)
+ .qs (periph_insel5_in26_qs)
+ );
+
+
+ // F[in27]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel5_in27 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel5_in27_we & regen_qs),
+ .wd (periph_insel5_in27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[27].q ),
+
+ // to register interface (read)
+ .qs (periph_insel5_in27_qs)
+ );
+
+
+ // F[in28]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel5_in28 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel5_in28_we & regen_qs),
+ .wd (periph_insel5_in28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[28].q ),
+
+ // to register interface (read)
+ .qs (periph_insel5_in28_qs)
+ );
+
+
+ // F[in29]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel5_in29 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel5_in29_we & regen_qs),
+ .wd (periph_insel5_in29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[29].q ),
+
+ // to register interface (read)
+ .qs (periph_insel5_in29_qs)
+ );
+
+
+ // Subregister 30 of Multireg periph_insel
+ // R[periph_insel6]: V(False)
+
+ // F[in30]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel6_in30 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel6_in30_we & regen_qs),
+ .wd (periph_insel6_in30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[30].q ),
+
+ // to register interface (read)
+ .qs (periph_insel6_in30_qs)
+ );
+
+
+ // F[in31]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h0)
+ ) u_periph_insel6_in31 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (periph_insel6_in31_we & regen_qs),
+ .wd (periph_insel6_in31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.periph_insel[31].q ),
+
+ // to register interface (read)
+ .qs (periph_insel6_in31_qs)
+ );
+
+
+
+
+ // Subregister 0 of Multireg mio_outsel
+ // R[mio_outsel0]: V(False)
+
+ // F[out0]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel0_out0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel0_out0_we & regen_qs),
+ .wd (mio_outsel0_out0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[0].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel0_out0_qs)
+ );
+
+
+ // F[out1]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel0_out1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel0_out1_we & regen_qs),
+ .wd (mio_outsel0_out1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[1].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel0_out1_qs)
+ );
+
+
+ // F[out2]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel0_out2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel0_out2_we & regen_qs),
+ .wd (mio_outsel0_out2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[2].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel0_out2_qs)
+ );
+
+
+ // F[out3]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel0_out3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel0_out3_we & regen_qs),
+ .wd (mio_outsel0_out3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[3].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel0_out3_qs)
+ );
+
+
+ // F[out4]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel0_out4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel0_out4_we & regen_qs),
+ .wd (mio_outsel0_out4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[4].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel0_out4_qs)
+ );
+
+
+ // Subregister 5 of Multireg mio_outsel
+ // R[mio_outsel1]: V(False)
+
+ // F[out5]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel1_out5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel1_out5_we & regen_qs),
+ .wd (mio_outsel1_out5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[5].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel1_out5_qs)
+ );
+
+
+ // F[out6]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel1_out6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel1_out6_we & regen_qs),
+ .wd (mio_outsel1_out6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[6].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel1_out6_qs)
+ );
+
+
+ // F[out7]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel1_out7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel1_out7_we & regen_qs),
+ .wd (mio_outsel1_out7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[7].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel1_out7_qs)
+ );
+
+
+ // F[out8]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel1_out8 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel1_out8_we & regen_qs),
+ .wd (mio_outsel1_out8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[8].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel1_out8_qs)
+ );
+
+
+ // F[out9]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel1_out9 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel1_out9_we & regen_qs),
+ .wd (mio_outsel1_out9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[9].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel1_out9_qs)
+ );
+
+
+ // Subregister 10 of Multireg mio_outsel
+ // R[mio_outsel2]: V(False)
+
+ // F[out10]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel2_out10 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel2_out10_we & regen_qs),
+ .wd (mio_outsel2_out10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[10].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel2_out10_qs)
+ );
+
+
+ // F[out11]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel2_out11 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel2_out11_we & regen_qs),
+ .wd (mio_outsel2_out11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[11].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel2_out11_qs)
+ );
+
+
+ // F[out12]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel2_out12 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel2_out12_we & regen_qs),
+ .wd (mio_outsel2_out12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[12].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel2_out12_qs)
+ );
+
+
+ // F[out13]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel2_out13 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel2_out13_we & regen_qs),
+ .wd (mio_outsel2_out13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[13].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel2_out13_qs)
+ );
+
+
+ // F[out14]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel2_out14 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel2_out14_we & regen_qs),
+ .wd (mio_outsel2_out14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[14].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel2_out14_qs)
+ );
+
+
+ // Subregister 15 of Multireg mio_outsel
+ // R[mio_outsel3]: V(False)
+
+ // F[out15]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel3_out15 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel3_out15_we & regen_qs),
+ .wd (mio_outsel3_out15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[15].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel3_out15_qs)
+ );
+
+
+ // F[out16]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel3_out16 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel3_out16_we & regen_qs),
+ .wd (mio_outsel3_out16_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[16].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel3_out16_qs)
+ );
+
+
+ // F[out17]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel3_out17 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel3_out17_we & regen_qs),
+ .wd (mio_outsel3_out17_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[17].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel3_out17_qs)
+ );
+
+
+ // F[out18]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel3_out18 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel3_out18_we & regen_qs),
+ .wd (mio_outsel3_out18_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[18].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel3_out18_qs)
+ );
+
+
+ // F[out19]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel3_out19 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel3_out19_we & regen_qs),
+ .wd (mio_outsel3_out19_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[19].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel3_out19_qs)
+ );
+
+
+ // Subregister 20 of Multireg mio_outsel
+ // R[mio_outsel4]: V(False)
+
+ // F[out20]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel4_out20 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel4_out20_we & regen_qs),
+ .wd (mio_outsel4_out20_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[20].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel4_out20_qs)
+ );
+
+
+ // F[out21]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel4_out21 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel4_out21_we & regen_qs),
+ .wd (mio_outsel4_out21_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[21].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel4_out21_qs)
+ );
+
+
+ // F[out22]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel4_out22 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel4_out22_we & regen_qs),
+ .wd (mio_outsel4_out22_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[22].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel4_out22_qs)
+ );
+
+
+ // F[out23]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel4_out23 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel4_out23_we & regen_qs),
+ .wd (mio_outsel4_out23_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[23].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel4_out23_qs)
+ );
+
+
+ // F[out24]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel4_out24 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel4_out24_we & regen_qs),
+ .wd (mio_outsel4_out24_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[24].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel4_out24_qs)
+ );
+
+
+ // Subregister 25 of Multireg mio_outsel
+ // R[mio_outsel5]: V(False)
+
+ // F[out25]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel5_out25 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel5_out25_we & regen_qs),
+ .wd (mio_outsel5_out25_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[25].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel5_out25_qs)
+ );
+
+
+ // F[out26]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel5_out26 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel5_out26_we & regen_qs),
+ .wd (mio_outsel5_out26_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[26].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel5_out26_qs)
+ );
+
+
+ // F[out27]: 17:12
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel5_out27 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel5_out27_we & regen_qs),
+ .wd (mio_outsel5_out27_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[27].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel5_out27_qs)
+ );
+
+
+ // F[out28]: 23:18
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel5_out28 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel5_out28_we & regen_qs),
+ .wd (mio_outsel5_out28_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[28].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel5_out28_qs)
+ );
+
+
+ // F[out29]: 29:24
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel5_out29 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel5_out29_we & regen_qs),
+ .wd (mio_outsel5_out29_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[29].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel5_out29_qs)
+ );
+
+
+ // Subregister 30 of Multireg mio_outsel
+ // R[mio_outsel6]: V(False)
+
+ // F[out30]: 5:0
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel6_out30 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel6_out30_we & regen_qs),
+ .wd (mio_outsel6_out30_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[30].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel6_out30_qs)
+ );
+
+
+ // F[out31]: 11:6
+ prim_subreg #(
+ .DW (6),
+ .SWACCESS("RW"),
+ .RESVAL (6'h2)
+ ) u_mio_outsel6_out31 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mio_outsel6_out31_we & regen_qs),
+ .wd (mio_outsel6_out31_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mio_outsel[31].q ),
+
+ // to register interface (read)
+ .qs (mio_outsel6_out31_qs)
+ );
+
+
+
+
+
+ logic [14:0] addr_hit;
+ always_comb begin
+ addr_hit = '0;
+ addr_hit[ 0] = (reg_addr == PINMUX_REGEN_OFFSET);
+ addr_hit[ 1] = (reg_addr == PINMUX_PERIPH_INSEL0_OFFSET);
+ addr_hit[ 2] = (reg_addr == PINMUX_PERIPH_INSEL1_OFFSET);
+ addr_hit[ 3] = (reg_addr == PINMUX_PERIPH_INSEL2_OFFSET);
+ addr_hit[ 4] = (reg_addr == PINMUX_PERIPH_INSEL3_OFFSET);
+ addr_hit[ 5] = (reg_addr == PINMUX_PERIPH_INSEL4_OFFSET);
+ addr_hit[ 6] = (reg_addr == PINMUX_PERIPH_INSEL5_OFFSET);
+ addr_hit[ 7] = (reg_addr == PINMUX_PERIPH_INSEL6_OFFSET);
+ addr_hit[ 8] = (reg_addr == PINMUX_MIO_OUTSEL0_OFFSET);
+ addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL1_OFFSET);
+ addr_hit[10] = (reg_addr == PINMUX_MIO_OUTSEL2_OFFSET);
+ addr_hit[11] = (reg_addr == PINMUX_MIO_OUTSEL3_OFFSET);
+ addr_hit[12] = (reg_addr == PINMUX_MIO_OUTSEL4_OFFSET);
+ addr_hit[13] = (reg_addr == PINMUX_MIO_OUTSEL5_OFFSET);
+ addr_hit[14] = (reg_addr == PINMUX_MIO_OUTSEL6_OFFSET);
+ end
+
+ assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
+
+ // Check sub-word write is permitted
+ always_comb begin
+ wr_err = 1'b0;
+ if (addr_hit[ 0] && reg_we && (PINMUX_PERMIT[ 0] != (PINMUX_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 1] && reg_we && (PINMUX_PERMIT[ 1] != (PINMUX_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 2] && reg_we && (PINMUX_PERMIT[ 2] != (PINMUX_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 3] && reg_we && (PINMUX_PERMIT[ 3] != (PINMUX_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 4] && reg_we && (PINMUX_PERMIT[ 4] != (PINMUX_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 5] && reg_we && (PINMUX_PERMIT[ 5] != (PINMUX_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 6] && reg_we && (PINMUX_PERMIT[ 6] != (PINMUX_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 7] && reg_we && (PINMUX_PERMIT[ 7] != (PINMUX_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 8] && reg_we && (PINMUX_PERMIT[ 8] != (PINMUX_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[ 9] && reg_we && (PINMUX_PERMIT[ 9] != (PINMUX_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[10] && reg_we && (PINMUX_PERMIT[10] != (PINMUX_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[11] && reg_we && (PINMUX_PERMIT[11] != (PINMUX_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[12] && reg_we && (PINMUX_PERMIT[12] != (PINMUX_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[13] && reg_we && (PINMUX_PERMIT[13] != (PINMUX_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[14] && reg_we && (PINMUX_PERMIT[14] != (PINMUX_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
+ end
+
+ assign regen_we = addr_hit[0] & reg_we & ~wr_err;
+ assign regen_wd = reg_wdata[0];
+
+ assign periph_insel0_in0_we = addr_hit[1] & reg_we & ~wr_err;
+ assign periph_insel0_in0_wd = reg_wdata[5:0];
+
+ assign periph_insel0_in1_we = addr_hit[1] & reg_we & ~wr_err;
+ assign periph_insel0_in1_wd = reg_wdata[11:6];
+
+ assign periph_insel0_in2_we = addr_hit[1] & reg_we & ~wr_err;
+ assign periph_insel0_in2_wd = reg_wdata[17:12];
+
+ assign periph_insel0_in3_we = addr_hit[1] & reg_we & ~wr_err;
+ assign periph_insel0_in3_wd = reg_wdata[23:18];
+
+ assign periph_insel0_in4_we = addr_hit[1] & reg_we & ~wr_err;
+ assign periph_insel0_in4_wd = reg_wdata[29:24];
+
+ assign periph_insel1_in5_we = addr_hit[2] & reg_we & ~wr_err;
+ assign periph_insel1_in5_wd = reg_wdata[5:0];
+
+ assign periph_insel1_in6_we = addr_hit[2] & reg_we & ~wr_err;
+ assign periph_insel1_in6_wd = reg_wdata[11:6];
+
+ assign periph_insel1_in7_we = addr_hit[2] & reg_we & ~wr_err;
+ assign periph_insel1_in7_wd = reg_wdata[17:12];
+
+ assign periph_insel1_in8_we = addr_hit[2] & reg_we & ~wr_err;
+ assign periph_insel1_in8_wd = reg_wdata[23:18];
+
+ assign periph_insel1_in9_we = addr_hit[2] & reg_we & ~wr_err;
+ assign periph_insel1_in9_wd = reg_wdata[29:24];
+
+ assign periph_insel2_in10_we = addr_hit[3] & reg_we & ~wr_err;
+ assign periph_insel2_in10_wd = reg_wdata[5:0];
+
+ assign periph_insel2_in11_we = addr_hit[3] & reg_we & ~wr_err;
+ assign periph_insel2_in11_wd = reg_wdata[11:6];
+
+ assign periph_insel2_in12_we = addr_hit[3] & reg_we & ~wr_err;
+ assign periph_insel2_in12_wd = reg_wdata[17:12];
+
+ assign periph_insel2_in13_we = addr_hit[3] & reg_we & ~wr_err;
+ assign periph_insel2_in13_wd = reg_wdata[23:18];
+
+ assign periph_insel2_in14_we = addr_hit[3] & reg_we & ~wr_err;
+ assign periph_insel2_in14_wd = reg_wdata[29:24];
+
+ assign periph_insel3_in15_we = addr_hit[4] & reg_we & ~wr_err;
+ assign periph_insel3_in15_wd = reg_wdata[5:0];
+
+ assign periph_insel3_in16_we = addr_hit[4] & reg_we & ~wr_err;
+ assign periph_insel3_in16_wd = reg_wdata[11:6];
+
+ assign periph_insel3_in17_we = addr_hit[4] & reg_we & ~wr_err;
+ assign periph_insel3_in17_wd = reg_wdata[17:12];
+
+ assign periph_insel3_in18_we = addr_hit[4] & reg_we & ~wr_err;
+ assign periph_insel3_in18_wd = reg_wdata[23:18];
+
+ assign periph_insel3_in19_we = addr_hit[4] & reg_we & ~wr_err;
+ assign periph_insel3_in19_wd = reg_wdata[29:24];
+
+ assign periph_insel4_in20_we = addr_hit[5] & reg_we & ~wr_err;
+ assign periph_insel4_in20_wd = reg_wdata[5:0];
+
+ assign periph_insel4_in21_we = addr_hit[5] & reg_we & ~wr_err;
+ assign periph_insel4_in21_wd = reg_wdata[11:6];
+
+ assign periph_insel4_in22_we = addr_hit[5] & reg_we & ~wr_err;
+ assign periph_insel4_in22_wd = reg_wdata[17:12];
+
+ assign periph_insel4_in23_we = addr_hit[5] & reg_we & ~wr_err;
+ assign periph_insel4_in23_wd = reg_wdata[23:18];
+
+ assign periph_insel4_in24_we = addr_hit[5] & reg_we & ~wr_err;
+ assign periph_insel4_in24_wd = reg_wdata[29:24];
+
+ assign periph_insel5_in25_we = addr_hit[6] & reg_we & ~wr_err;
+ assign periph_insel5_in25_wd = reg_wdata[5:0];
+
+ assign periph_insel5_in26_we = addr_hit[6] & reg_we & ~wr_err;
+ assign periph_insel5_in26_wd = reg_wdata[11:6];
+
+ assign periph_insel5_in27_we = addr_hit[6] & reg_we & ~wr_err;
+ assign periph_insel5_in27_wd = reg_wdata[17:12];
+
+ assign periph_insel5_in28_we = addr_hit[6] & reg_we & ~wr_err;
+ assign periph_insel5_in28_wd = reg_wdata[23:18];
+
+ assign periph_insel5_in29_we = addr_hit[6] & reg_we & ~wr_err;
+ assign periph_insel5_in29_wd = reg_wdata[29:24];
+
+ assign periph_insel6_in30_we = addr_hit[7] & reg_we & ~wr_err;
+ assign periph_insel6_in30_wd = reg_wdata[5:0];
+
+ assign periph_insel6_in31_we = addr_hit[7] & reg_we & ~wr_err;
+ assign periph_insel6_in31_wd = reg_wdata[11:6];
+
+ assign mio_outsel0_out0_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mio_outsel0_out0_wd = reg_wdata[5:0];
+
+ assign mio_outsel0_out1_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mio_outsel0_out1_wd = reg_wdata[11:6];
+
+ assign mio_outsel0_out2_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mio_outsel0_out2_wd = reg_wdata[17:12];
+
+ assign mio_outsel0_out3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mio_outsel0_out3_wd = reg_wdata[23:18];
+
+ assign mio_outsel0_out4_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mio_outsel0_out4_wd = reg_wdata[29:24];
+
+ assign mio_outsel1_out5_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mio_outsel1_out5_wd = reg_wdata[5:0];
+
+ assign mio_outsel1_out6_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mio_outsel1_out6_wd = reg_wdata[11:6];
+
+ assign mio_outsel1_out7_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mio_outsel1_out7_wd = reg_wdata[17:12];
+
+ assign mio_outsel1_out8_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mio_outsel1_out8_wd = reg_wdata[23:18];
+
+ assign mio_outsel1_out9_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mio_outsel1_out9_wd = reg_wdata[29:24];
+
+ assign mio_outsel2_out10_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mio_outsel2_out10_wd = reg_wdata[5:0];
+
+ assign mio_outsel2_out11_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mio_outsel2_out11_wd = reg_wdata[11:6];
+
+ assign mio_outsel2_out12_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mio_outsel2_out12_wd = reg_wdata[17:12];
+
+ assign mio_outsel2_out13_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mio_outsel2_out13_wd = reg_wdata[23:18];
+
+ assign mio_outsel2_out14_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mio_outsel2_out14_wd = reg_wdata[29:24];
+
+ assign mio_outsel3_out15_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mio_outsel3_out15_wd = reg_wdata[5:0];
+
+ assign mio_outsel3_out16_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mio_outsel3_out16_wd = reg_wdata[11:6];
+
+ assign mio_outsel3_out17_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mio_outsel3_out17_wd = reg_wdata[17:12];
+
+ assign mio_outsel3_out18_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mio_outsel3_out18_wd = reg_wdata[23:18];
+
+ assign mio_outsel3_out19_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mio_outsel3_out19_wd = reg_wdata[29:24];
+
+ assign mio_outsel4_out20_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mio_outsel4_out20_wd = reg_wdata[5:0];
+
+ assign mio_outsel4_out21_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mio_outsel4_out21_wd = reg_wdata[11:6];
+
+ assign mio_outsel4_out22_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mio_outsel4_out22_wd = reg_wdata[17:12];
+
+ assign mio_outsel4_out23_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mio_outsel4_out23_wd = reg_wdata[23:18];
+
+ assign mio_outsel4_out24_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mio_outsel4_out24_wd = reg_wdata[29:24];
+
+ assign mio_outsel5_out25_we = addr_hit[13] & reg_we & ~wr_err;
+ assign mio_outsel5_out25_wd = reg_wdata[5:0];
+
+ assign mio_outsel5_out26_we = addr_hit[13] & reg_we & ~wr_err;
+ assign mio_outsel5_out26_wd = reg_wdata[11:6];
+
+ assign mio_outsel5_out27_we = addr_hit[13] & reg_we & ~wr_err;
+ assign mio_outsel5_out27_wd = reg_wdata[17:12];
+
+ assign mio_outsel5_out28_we = addr_hit[13] & reg_we & ~wr_err;
+ assign mio_outsel5_out28_wd = reg_wdata[23:18];
+
+ assign mio_outsel5_out29_we = addr_hit[13] & reg_we & ~wr_err;
+ assign mio_outsel5_out29_wd = reg_wdata[29:24];
+
+ assign mio_outsel6_out30_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mio_outsel6_out30_wd = reg_wdata[5:0];
+
+ assign mio_outsel6_out31_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mio_outsel6_out31_wd = reg_wdata[11:6];
+
+ // Read data return
+ always_comb begin
+ reg_rdata_next = '0;
+ unique case (1'b1)
+ addr_hit[0]: begin
+ reg_rdata_next[0] = regen_qs;
+ end
+
+ addr_hit[1]: begin
+ reg_rdata_next[5:0] = periph_insel0_in0_qs;
+ reg_rdata_next[11:6] = periph_insel0_in1_qs;
+ reg_rdata_next[17:12] = periph_insel0_in2_qs;
+ reg_rdata_next[23:18] = periph_insel0_in3_qs;
+ reg_rdata_next[29:24] = periph_insel0_in4_qs;
+ end
+
+ addr_hit[2]: begin
+ reg_rdata_next[5:0] = periph_insel1_in5_qs;
+ reg_rdata_next[11:6] = periph_insel1_in6_qs;
+ reg_rdata_next[17:12] = periph_insel1_in7_qs;
+ reg_rdata_next[23:18] = periph_insel1_in8_qs;
+ reg_rdata_next[29:24] = periph_insel1_in9_qs;
+ end
+
+ addr_hit[3]: begin
+ reg_rdata_next[5:0] = periph_insel2_in10_qs;
+ reg_rdata_next[11:6] = periph_insel2_in11_qs;
+ reg_rdata_next[17:12] = periph_insel2_in12_qs;
+ reg_rdata_next[23:18] = periph_insel2_in13_qs;
+ reg_rdata_next[29:24] = periph_insel2_in14_qs;
+ end
+
+ addr_hit[4]: begin
+ reg_rdata_next[5:0] = periph_insel3_in15_qs;
+ reg_rdata_next[11:6] = periph_insel3_in16_qs;
+ reg_rdata_next[17:12] = periph_insel3_in17_qs;
+ reg_rdata_next[23:18] = periph_insel3_in18_qs;
+ reg_rdata_next[29:24] = periph_insel3_in19_qs;
+ end
+
+ addr_hit[5]: begin
+ reg_rdata_next[5:0] = periph_insel4_in20_qs;
+ reg_rdata_next[11:6] = periph_insel4_in21_qs;
+ reg_rdata_next[17:12] = periph_insel4_in22_qs;
+ reg_rdata_next[23:18] = periph_insel4_in23_qs;
+ reg_rdata_next[29:24] = periph_insel4_in24_qs;
+ end
+
+ addr_hit[6]: begin
+ reg_rdata_next[5:0] = periph_insel5_in25_qs;
+ reg_rdata_next[11:6] = periph_insel5_in26_qs;
+ reg_rdata_next[17:12] = periph_insel5_in27_qs;
+ reg_rdata_next[23:18] = periph_insel5_in28_qs;
+ reg_rdata_next[29:24] = periph_insel5_in29_qs;
+ end
+
+ addr_hit[7]: begin
+ reg_rdata_next[5:0] = periph_insel6_in30_qs;
+ reg_rdata_next[11:6] = periph_insel6_in31_qs;
+ end
+
+ addr_hit[8]: begin
+ reg_rdata_next[5:0] = mio_outsel0_out0_qs;
+ reg_rdata_next[11:6] = mio_outsel0_out1_qs;
+ reg_rdata_next[17:12] = mio_outsel0_out2_qs;
+ reg_rdata_next[23:18] = mio_outsel0_out3_qs;
+ reg_rdata_next[29:24] = mio_outsel0_out4_qs;
+ end
+
+ addr_hit[9]: begin
+ reg_rdata_next[5:0] = mio_outsel1_out5_qs;
+ reg_rdata_next[11:6] = mio_outsel1_out6_qs;
+ reg_rdata_next[17:12] = mio_outsel1_out7_qs;
+ reg_rdata_next[23:18] = mio_outsel1_out8_qs;
+ reg_rdata_next[29:24] = mio_outsel1_out9_qs;
+ end
+
+ addr_hit[10]: begin
+ reg_rdata_next[5:0] = mio_outsel2_out10_qs;
+ reg_rdata_next[11:6] = mio_outsel2_out11_qs;
+ reg_rdata_next[17:12] = mio_outsel2_out12_qs;
+ reg_rdata_next[23:18] = mio_outsel2_out13_qs;
+ reg_rdata_next[29:24] = mio_outsel2_out14_qs;
+ end
+
+ addr_hit[11]: begin
+ reg_rdata_next[5:0] = mio_outsel3_out15_qs;
+ reg_rdata_next[11:6] = mio_outsel3_out16_qs;
+ reg_rdata_next[17:12] = mio_outsel3_out17_qs;
+ reg_rdata_next[23:18] = mio_outsel3_out18_qs;
+ reg_rdata_next[29:24] = mio_outsel3_out19_qs;
+ end
+
+ addr_hit[12]: begin
+ reg_rdata_next[5:0] = mio_outsel4_out20_qs;
+ reg_rdata_next[11:6] = mio_outsel4_out21_qs;
+ reg_rdata_next[17:12] = mio_outsel4_out22_qs;
+ reg_rdata_next[23:18] = mio_outsel4_out23_qs;
+ reg_rdata_next[29:24] = mio_outsel4_out24_qs;
+ end
+
+ addr_hit[13]: begin
+ reg_rdata_next[5:0] = mio_outsel5_out25_qs;
+ reg_rdata_next[11:6] = mio_outsel5_out26_qs;
+ reg_rdata_next[17:12] = mio_outsel5_out27_qs;
+ reg_rdata_next[23:18] = mio_outsel5_out28_qs;
+ reg_rdata_next[29:24] = mio_outsel5_out29_qs;
+ end
+
+ addr_hit[14]: begin
+ reg_rdata_next[5:0] = mio_outsel6_out30_qs;
+ reg_rdata_next[11:6] = mio_outsel6_out31_qs;
+ end
+
+ default: begin
+ reg_rdata_next = '1;
+ end
+ endcase
+ end
+
+ // Assertions for Register Interface
+ `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
+ `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
+
+ `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
+
+ `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
+
+ `ASSERT(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
+
+endmodule
diff --git a/hw/top_earlgrey/ip/rv_plic/doc/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/doc/autogen/rv_plic.hjson
index 71a0a44..b58d56d 100644
--- a/hw/top_earlgrey/ip/rv_plic/doc/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/doc/autogen/rv_plic.hjson
@@ -523,7 +523,7 @@
],
}
{ name: "CC0",
- desc: "Claim by read, complete by write for Target 0",
+ desc: "Claim interrupt by read, complete interrupt by write for Target 0. Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.",
swaccess: "rw",
hwaccess: "hrw",
hwext: "true",
@@ -534,7 +534,7 @@
],
}
{ name: "MSIP0",
- desc: "msip for Hart 0. Write 1 to here asserts msip_o[0]",
+ desc: "msip for Hart 0. Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear",
swaccess: "rw",
hwaccess: "hro",
fields: [
diff --git a/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson
index 3538267..9b26130 100644
--- a/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar/doc/autogen/xbar_main.gen.hjson
@@ -40,6 +40,7 @@
aes
hmac
rv_plic
+ pinmux
]
dm_sba:
[
@@ -54,6 +55,7 @@
aes
hmac
rv_plic
+ pinmux
]
}
nodes:
@@ -202,6 +204,16 @@
pipeline_byp: "false"
pipeline: "true"
}
+ {
+ name: pinmux
+ type: device
+ clock: main
+ inst_type: pinmux
+ base_addr: 0x40070000
+ size_byte: 0x1000
+ pipeline_byp: "false"
+ pipeline: "true"
+ }
]
clock: main
}
\ No newline at end of file
diff --git a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
index 42a772b..be3cd61 100644
--- a/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
+++ b/hw/top_earlgrey/ip/xbar/dv/autogen/xbar_main_bind.sv
@@ -98,6 +98,12 @@
.h2d (tl_rv_plic_o),
.d2h (tl_rv_plic_i)
);
+ bind xbar_main tlul_assert tlul_assert_device_pinmux (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_pinmux_o),
+ .d2h (tl_pinmux_i)
+ );
endmodule
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
index 06205c1..84b2a90 100644
--- a/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/tl_main_pkg.sv
@@ -18,6 +18,7 @@
localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 40120000;
localparam logic [31:0] ADDR_SPACE_AES = 32'h 40110000;
localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 40090000;
+ localparam logic [31:0] ADDR_SPACE_PINMUX = 32'h 40070000;
localparam logic [31:0] ADDR_MASK_ROM = 32'h 00001fff;
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
@@ -31,9 +32,10 @@
localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_AES = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_PINMUX = 32'h 00000fff;
localparam int N_HOST = 3;
- localparam int N_DEVICE = 12;
+ localparam int N_DEVICE = 13;
typedef enum int {
TlRom = 0,
@@ -47,7 +49,8 @@
TlRvTimer = 8,
TlHmac = 9,
TlAes = 10,
- TlRvPlic = 11
+ TlRvPlic = 11,
+ TlPinmux = 12
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
index 2ccd8ab..b866e6c 100644
--- a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
@@ -7,65 +7,69 @@
//
// Interconnect
// corei
-// -> s1n_15
-// -> sm1_16
-// -> rom
+// -> s1n_16
// -> sm1_17
-// -> debug_mem
+// -> rom
// -> sm1_18
-// -> ram_main
+// -> debug_mem
// -> sm1_19
+// -> ram_main
+// -> sm1_20
// -> eflash
// cored
-// -> s1n_20
-// -> sm1_16
-// -> rom
+// -> s1n_21
// -> sm1_17
-// -> debug_mem
-// -> sm1_18
-// -> ram_main
-// -> sm1_19
-// -> eflash
-// -> sm1_21
-// -> uart
-// -> sm1_22
-// -> gpio
-// -> sm1_23
-// -> spi_device
-// -> sm1_24
-// -> flash_ctrl
-// -> sm1_25
-// -> rv_timer
-// -> sm1_26
-// -> aes
-// -> sm1_27
-// -> hmac
-// -> sm1_28
-// -> rv_plic
-// dm_sba
-// -> s1n_29
-// -> sm1_16
// -> rom
// -> sm1_18
-// -> ram_main
+// -> debug_mem
// -> sm1_19
+// -> ram_main
+// -> sm1_20
// -> eflash
-// -> sm1_21
-// -> uart
// -> sm1_22
-// -> gpio
+// -> uart
// -> sm1_23
-// -> spi_device
+// -> gpio
// -> sm1_24
-// -> flash_ctrl
+// -> spi_device
// -> sm1_25
-// -> rv_timer
+// -> flash_ctrl
// -> sm1_26
-// -> aes
+// -> rv_timer
// -> sm1_27
-// -> hmac
+// -> aes
// -> sm1_28
+// -> hmac
+// -> sm1_29
// -> rv_plic
+// -> sm1_30
+// -> pinmux
+// dm_sba
+// -> s1n_31
+// -> sm1_17
+// -> rom
+// -> sm1_19
+// -> ram_main
+// -> sm1_20
+// -> eflash
+// -> sm1_22
+// -> uart
+// -> sm1_23
+// -> gpio
+// -> sm1_24
+// -> spi_device
+// -> sm1_25
+// -> flash_ctrl
+// -> sm1_26
+// -> rv_timer
+// -> sm1_27
+// -> aes
+// -> sm1_28
+// -> hmac
+// -> sm1_29
+// -> rv_plic
+// -> sm1_30
+// -> pinmux
module xbar_main (
input clk_main_i,
@@ -104,6 +108,8 @@
input tlul_pkg::tl_d2h_t tl_aes_i,
output tlul_pkg::tl_h2d_t tl_rv_plic_o,
input tlul_pkg::tl_d2h_t tl_rv_plic_i,
+ output tlul_pkg::tl_h2d_t tl_pinmux_o,
+ input tlul_pkg::tl_d2h_t tl_pinmux_i,
input scanmode_i
);
@@ -111,33 +117,26 @@
import tlul_pkg::*;
import tl_main_pkg::*;
- tl_h2d_t tl_s1n_15_us_h2d ;
- tl_d2h_t tl_s1n_15_us_d2h ;
+ tl_h2d_t tl_s1n_16_us_h2d ;
+ tl_d2h_t tl_s1n_16_us_d2h ;
- tl_h2d_t tl_s1n_15_ds_h2d [4];
- tl_d2h_t tl_s1n_15_ds_d2h [4];
+ tl_h2d_t tl_s1n_16_ds_h2d [4];
+ tl_d2h_t tl_s1n_16_ds_d2h [4];
// Create steering signal
- logic [2:0] dev_sel_s1n_15;
+ logic [2:0] dev_sel_s1n_16;
- tl_h2d_t tl_sm1_16_us_h2d [3];
- tl_d2h_t tl_sm1_16_us_d2h [3];
-
- tl_h2d_t tl_sm1_16_ds_h2d ;
- tl_d2h_t tl_sm1_16_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_17_us_h2d [2];
- tl_d2h_t tl_sm1_17_us_d2h [2];
+ tl_h2d_t tl_sm1_17_us_h2d [3];
+ tl_d2h_t tl_sm1_17_us_d2h [3];
tl_h2d_t tl_sm1_17_ds_h2d ;
tl_d2h_t tl_sm1_17_ds_d2h ;
- tl_h2d_t tl_sm1_18_us_h2d [3];
- tl_d2h_t tl_sm1_18_us_d2h [3];
+ tl_h2d_t tl_sm1_18_us_h2d [2];
+ tl_d2h_t tl_sm1_18_us_d2h [2];
tl_h2d_t tl_sm1_18_ds_h2d ;
tl_d2h_t tl_sm1_18_ds_d2h ;
@@ -149,22 +148,22 @@
tl_h2d_t tl_sm1_19_ds_h2d ;
tl_d2h_t tl_sm1_19_ds_d2h ;
- tl_h2d_t tl_s1n_20_us_h2d ;
- tl_d2h_t tl_s1n_20_us_d2h ;
+
+ tl_h2d_t tl_sm1_20_us_h2d [3];
+ tl_d2h_t tl_sm1_20_us_d2h [3];
+
+ tl_h2d_t tl_sm1_20_ds_h2d ;
+ tl_d2h_t tl_sm1_20_ds_d2h ;
+
+ tl_h2d_t tl_s1n_21_us_h2d ;
+ tl_d2h_t tl_s1n_21_us_d2h ;
- tl_h2d_t tl_s1n_20_ds_h2d [12];
- tl_d2h_t tl_s1n_20_ds_d2h [12];
+ tl_h2d_t tl_s1n_21_ds_h2d [13];
+ tl_d2h_t tl_s1n_21_ds_d2h [13];
// Create steering signal
- logic [3:0] dev_sel_s1n_20;
-
-
- tl_h2d_t tl_sm1_21_us_h2d [2];
- tl_d2h_t tl_sm1_21_us_d2h [2];
-
- tl_h2d_t tl_sm1_21_ds_h2d ;
- tl_d2h_t tl_sm1_21_ds_d2h ;
+ logic [3:0] dev_sel_s1n_21;
tl_h2d_t tl_sm1_22_us_h2d [2];
@@ -215,213 +214,240 @@
tl_h2d_t tl_sm1_28_ds_h2d ;
tl_d2h_t tl_sm1_28_ds_d2h ;
- tl_h2d_t tl_s1n_29_us_h2d ;
- tl_d2h_t tl_s1n_29_us_d2h ;
+
+ tl_h2d_t tl_sm1_29_us_h2d [2];
+ tl_d2h_t tl_sm1_29_us_d2h [2];
+
+ tl_h2d_t tl_sm1_29_ds_h2d ;
+ tl_d2h_t tl_sm1_29_ds_d2h ;
- tl_h2d_t tl_s1n_29_ds_h2d [11];
- tl_d2h_t tl_s1n_29_ds_d2h [11];
+ tl_h2d_t tl_sm1_30_us_h2d [2];
+ tl_d2h_t tl_sm1_30_us_d2h [2];
+
+ tl_h2d_t tl_sm1_30_ds_h2d ;
+ tl_d2h_t tl_sm1_30_ds_d2h ;
+
+ tl_h2d_t tl_s1n_31_us_h2d ;
+ tl_d2h_t tl_s1n_31_us_d2h ;
+
+
+ tl_h2d_t tl_s1n_31_ds_h2d [12];
+ tl_d2h_t tl_s1n_31_ds_d2h [12];
// Create steering signal
- logic [3:0] dev_sel_s1n_29;
+ logic [3:0] dev_sel_s1n_31;
- assign tl_sm1_16_us_h2d[0] = tl_s1n_15_ds_h2d[0];
- assign tl_s1n_15_ds_d2h[0] = tl_sm1_16_us_d2h[0];
+ assign tl_sm1_17_us_h2d[0] = tl_s1n_16_ds_h2d[0];
+ assign tl_s1n_16_ds_d2h[0] = tl_sm1_17_us_d2h[0];
- assign tl_sm1_17_us_h2d[0] = tl_s1n_15_ds_h2d[1];
- assign tl_s1n_15_ds_d2h[1] = tl_sm1_17_us_d2h[0];
+ assign tl_sm1_18_us_h2d[0] = tl_s1n_16_ds_h2d[1];
+ assign tl_s1n_16_ds_d2h[1] = tl_sm1_18_us_d2h[0];
- assign tl_sm1_18_us_h2d[0] = tl_s1n_15_ds_h2d[2];
- assign tl_s1n_15_ds_d2h[2] = tl_sm1_18_us_d2h[0];
+ assign tl_sm1_19_us_h2d[0] = tl_s1n_16_ds_h2d[2];
+ assign tl_s1n_16_ds_d2h[2] = tl_sm1_19_us_d2h[0];
- assign tl_sm1_19_us_h2d[0] = tl_s1n_15_ds_h2d[3];
- assign tl_s1n_15_ds_d2h[3] = tl_sm1_19_us_d2h[0];
+ assign tl_sm1_20_us_h2d[0] = tl_s1n_16_ds_h2d[3];
+ assign tl_s1n_16_ds_d2h[3] = tl_sm1_20_us_d2h[0];
- assign tl_sm1_16_us_h2d[1] = tl_s1n_20_ds_h2d[0];
- assign tl_s1n_20_ds_d2h[0] = tl_sm1_16_us_d2h[1];
+ assign tl_sm1_17_us_h2d[1] = tl_s1n_21_ds_h2d[0];
+ assign tl_s1n_21_ds_d2h[0] = tl_sm1_17_us_d2h[1];
- assign tl_sm1_17_us_h2d[1] = tl_s1n_20_ds_h2d[1];
- assign tl_s1n_20_ds_d2h[1] = tl_sm1_17_us_d2h[1];
+ assign tl_sm1_18_us_h2d[1] = tl_s1n_21_ds_h2d[1];
+ assign tl_s1n_21_ds_d2h[1] = tl_sm1_18_us_d2h[1];
- assign tl_sm1_18_us_h2d[1] = tl_s1n_20_ds_h2d[2];
- assign tl_s1n_20_ds_d2h[2] = tl_sm1_18_us_d2h[1];
+ assign tl_sm1_19_us_h2d[1] = tl_s1n_21_ds_h2d[2];
+ assign tl_s1n_21_ds_d2h[2] = tl_sm1_19_us_d2h[1];
- assign tl_sm1_19_us_h2d[1] = tl_s1n_20_ds_h2d[3];
- assign tl_s1n_20_ds_d2h[3] = tl_sm1_19_us_d2h[1];
+ assign tl_sm1_20_us_h2d[1] = tl_s1n_21_ds_h2d[3];
+ assign tl_s1n_21_ds_d2h[3] = tl_sm1_20_us_d2h[1];
- assign tl_sm1_21_us_h2d[0] = tl_s1n_20_ds_h2d[4];
- assign tl_s1n_20_ds_d2h[4] = tl_sm1_21_us_d2h[0];
+ assign tl_sm1_22_us_h2d[0] = tl_s1n_21_ds_h2d[4];
+ assign tl_s1n_21_ds_d2h[4] = tl_sm1_22_us_d2h[0];
- assign tl_sm1_22_us_h2d[0] = tl_s1n_20_ds_h2d[5];
- assign tl_s1n_20_ds_d2h[5] = tl_sm1_22_us_d2h[0];
+ assign tl_sm1_23_us_h2d[0] = tl_s1n_21_ds_h2d[5];
+ assign tl_s1n_21_ds_d2h[5] = tl_sm1_23_us_d2h[0];
- assign tl_sm1_23_us_h2d[0] = tl_s1n_20_ds_h2d[6];
- assign tl_s1n_20_ds_d2h[6] = tl_sm1_23_us_d2h[0];
+ assign tl_sm1_24_us_h2d[0] = tl_s1n_21_ds_h2d[6];
+ assign tl_s1n_21_ds_d2h[6] = tl_sm1_24_us_d2h[0];
- assign tl_sm1_24_us_h2d[0] = tl_s1n_20_ds_h2d[7];
- assign tl_s1n_20_ds_d2h[7] = tl_sm1_24_us_d2h[0];
+ assign tl_sm1_25_us_h2d[0] = tl_s1n_21_ds_h2d[7];
+ assign tl_s1n_21_ds_d2h[7] = tl_sm1_25_us_d2h[0];
- assign tl_sm1_25_us_h2d[0] = tl_s1n_20_ds_h2d[8];
- assign tl_s1n_20_ds_d2h[8] = tl_sm1_25_us_d2h[0];
+ assign tl_sm1_26_us_h2d[0] = tl_s1n_21_ds_h2d[8];
+ assign tl_s1n_21_ds_d2h[8] = tl_sm1_26_us_d2h[0];
- assign tl_sm1_26_us_h2d[0] = tl_s1n_20_ds_h2d[9];
- assign tl_s1n_20_ds_d2h[9] = tl_sm1_26_us_d2h[0];
+ assign tl_sm1_27_us_h2d[0] = tl_s1n_21_ds_h2d[9];
+ assign tl_s1n_21_ds_d2h[9] = tl_sm1_27_us_d2h[0];
- assign tl_sm1_27_us_h2d[0] = tl_s1n_20_ds_h2d[10];
- assign tl_s1n_20_ds_d2h[10] = tl_sm1_27_us_d2h[0];
+ assign tl_sm1_28_us_h2d[0] = tl_s1n_21_ds_h2d[10];
+ assign tl_s1n_21_ds_d2h[10] = tl_sm1_28_us_d2h[0];
- assign tl_sm1_28_us_h2d[0] = tl_s1n_20_ds_h2d[11];
- assign tl_s1n_20_ds_d2h[11] = tl_sm1_28_us_d2h[0];
+ assign tl_sm1_29_us_h2d[0] = tl_s1n_21_ds_h2d[11];
+ assign tl_s1n_21_ds_d2h[11] = tl_sm1_29_us_d2h[0];
- assign tl_sm1_16_us_h2d[2] = tl_s1n_29_ds_h2d[0];
- assign tl_s1n_29_ds_d2h[0] = tl_sm1_16_us_d2h[2];
+ assign tl_sm1_30_us_h2d[0] = tl_s1n_21_ds_h2d[12];
+ assign tl_s1n_21_ds_d2h[12] = tl_sm1_30_us_d2h[0];
- assign tl_sm1_18_us_h2d[2] = tl_s1n_29_ds_h2d[1];
- assign tl_s1n_29_ds_d2h[1] = tl_sm1_18_us_d2h[2];
+ assign tl_sm1_17_us_h2d[2] = tl_s1n_31_ds_h2d[0];
+ assign tl_s1n_31_ds_d2h[0] = tl_sm1_17_us_d2h[2];
- assign tl_sm1_19_us_h2d[2] = tl_s1n_29_ds_h2d[2];
- assign tl_s1n_29_ds_d2h[2] = tl_sm1_19_us_d2h[2];
+ assign tl_sm1_19_us_h2d[2] = tl_s1n_31_ds_h2d[1];
+ assign tl_s1n_31_ds_d2h[1] = tl_sm1_19_us_d2h[2];
- assign tl_sm1_21_us_h2d[1] = tl_s1n_29_ds_h2d[3];
- assign tl_s1n_29_ds_d2h[3] = tl_sm1_21_us_d2h[1];
+ assign tl_sm1_20_us_h2d[2] = tl_s1n_31_ds_h2d[2];
+ assign tl_s1n_31_ds_d2h[2] = tl_sm1_20_us_d2h[2];
- assign tl_sm1_22_us_h2d[1] = tl_s1n_29_ds_h2d[4];
- assign tl_s1n_29_ds_d2h[4] = tl_sm1_22_us_d2h[1];
+ assign tl_sm1_22_us_h2d[1] = tl_s1n_31_ds_h2d[3];
+ assign tl_s1n_31_ds_d2h[3] = tl_sm1_22_us_d2h[1];
- assign tl_sm1_23_us_h2d[1] = tl_s1n_29_ds_h2d[5];
- assign tl_s1n_29_ds_d2h[5] = tl_sm1_23_us_d2h[1];
+ assign tl_sm1_23_us_h2d[1] = tl_s1n_31_ds_h2d[4];
+ assign tl_s1n_31_ds_d2h[4] = tl_sm1_23_us_d2h[1];
- assign tl_sm1_24_us_h2d[1] = tl_s1n_29_ds_h2d[6];
- assign tl_s1n_29_ds_d2h[6] = tl_sm1_24_us_d2h[1];
+ assign tl_sm1_24_us_h2d[1] = tl_s1n_31_ds_h2d[5];
+ assign tl_s1n_31_ds_d2h[5] = tl_sm1_24_us_d2h[1];
- assign tl_sm1_25_us_h2d[1] = tl_s1n_29_ds_h2d[7];
- assign tl_s1n_29_ds_d2h[7] = tl_sm1_25_us_d2h[1];
+ assign tl_sm1_25_us_h2d[1] = tl_s1n_31_ds_h2d[6];
+ assign tl_s1n_31_ds_d2h[6] = tl_sm1_25_us_d2h[1];
- assign tl_sm1_26_us_h2d[1] = tl_s1n_29_ds_h2d[8];
- assign tl_s1n_29_ds_d2h[8] = tl_sm1_26_us_d2h[1];
+ assign tl_sm1_26_us_h2d[1] = tl_s1n_31_ds_h2d[7];
+ assign tl_s1n_31_ds_d2h[7] = tl_sm1_26_us_d2h[1];
- assign tl_sm1_27_us_h2d[1] = tl_s1n_29_ds_h2d[9];
- assign tl_s1n_29_ds_d2h[9] = tl_sm1_27_us_d2h[1];
+ assign tl_sm1_27_us_h2d[1] = tl_s1n_31_ds_h2d[8];
+ assign tl_s1n_31_ds_d2h[8] = tl_sm1_27_us_d2h[1];
- assign tl_sm1_28_us_h2d[1] = tl_s1n_29_ds_h2d[10];
- assign tl_s1n_29_ds_d2h[10] = tl_sm1_28_us_d2h[1];
+ assign tl_sm1_28_us_h2d[1] = tl_s1n_31_ds_h2d[9];
+ assign tl_s1n_31_ds_d2h[9] = tl_sm1_28_us_d2h[1];
- assign tl_s1n_15_us_h2d = tl_corei_i;
- assign tl_corei_o = tl_s1n_15_us_d2h;
+ assign tl_sm1_29_us_h2d[1] = tl_s1n_31_ds_h2d[10];
+ assign tl_s1n_31_ds_d2h[10] = tl_sm1_29_us_d2h[1];
- assign tl_rom_o = tl_sm1_16_ds_h2d;
- assign tl_sm1_16_ds_d2h = tl_rom_i;
+ assign tl_sm1_30_us_h2d[1] = tl_s1n_31_ds_h2d[11];
+ assign tl_s1n_31_ds_d2h[11] = tl_sm1_30_us_d2h[1];
- assign tl_debug_mem_o = tl_sm1_17_ds_h2d;
- assign tl_sm1_17_ds_d2h = tl_debug_mem_i;
+ assign tl_s1n_16_us_h2d = tl_corei_i;
+ assign tl_corei_o = tl_s1n_16_us_d2h;
- assign tl_ram_main_o = tl_sm1_18_ds_h2d;
- assign tl_sm1_18_ds_d2h = tl_ram_main_i;
+ assign tl_rom_o = tl_sm1_17_ds_h2d;
+ assign tl_sm1_17_ds_d2h = tl_rom_i;
- assign tl_eflash_o = tl_sm1_19_ds_h2d;
- assign tl_sm1_19_ds_d2h = tl_eflash_i;
+ assign tl_debug_mem_o = tl_sm1_18_ds_h2d;
+ assign tl_sm1_18_ds_d2h = tl_debug_mem_i;
- assign tl_s1n_20_us_h2d = tl_cored_i;
- assign tl_cored_o = tl_s1n_20_us_d2h;
+ assign tl_ram_main_o = tl_sm1_19_ds_h2d;
+ assign tl_sm1_19_ds_d2h = tl_ram_main_i;
- assign tl_uart_o = tl_sm1_21_ds_h2d;
- assign tl_sm1_21_ds_d2h = tl_uart_i;
+ assign tl_eflash_o = tl_sm1_20_ds_h2d;
+ assign tl_sm1_20_ds_d2h = tl_eflash_i;
- assign tl_gpio_o = tl_sm1_22_ds_h2d;
- assign tl_sm1_22_ds_d2h = tl_gpio_i;
+ assign tl_s1n_21_us_h2d = tl_cored_i;
+ assign tl_cored_o = tl_s1n_21_us_d2h;
- assign tl_spi_device_o = tl_sm1_23_ds_h2d;
- assign tl_sm1_23_ds_d2h = tl_spi_device_i;
+ assign tl_uart_o = tl_sm1_22_ds_h2d;
+ assign tl_sm1_22_ds_d2h = tl_uart_i;
- assign tl_flash_ctrl_o = tl_sm1_24_ds_h2d;
- assign tl_sm1_24_ds_d2h = tl_flash_ctrl_i;
+ assign tl_gpio_o = tl_sm1_23_ds_h2d;
+ assign tl_sm1_23_ds_d2h = tl_gpio_i;
- assign tl_rv_timer_o = tl_sm1_25_ds_h2d;
- assign tl_sm1_25_ds_d2h = tl_rv_timer_i;
+ assign tl_spi_device_o = tl_sm1_24_ds_h2d;
+ assign tl_sm1_24_ds_d2h = tl_spi_device_i;
- assign tl_aes_o = tl_sm1_26_ds_h2d;
- assign tl_sm1_26_ds_d2h = tl_aes_i;
+ assign tl_flash_ctrl_o = tl_sm1_25_ds_h2d;
+ assign tl_sm1_25_ds_d2h = tl_flash_ctrl_i;
- assign tl_hmac_o = tl_sm1_27_ds_h2d;
- assign tl_sm1_27_ds_d2h = tl_hmac_i;
+ assign tl_rv_timer_o = tl_sm1_26_ds_h2d;
+ assign tl_sm1_26_ds_d2h = tl_rv_timer_i;
- assign tl_rv_plic_o = tl_sm1_28_ds_h2d;
- assign tl_sm1_28_ds_d2h = tl_rv_plic_i;
+ assign tl_aes_o = tl_sm1_27_ds_h2d;
+ assign tl_sm1_27_ds_d2h = tl_aes_i;
- assign tl_s1n_29_us_h2d = tl_dm_sba_i;
- assign tl_dm_sba_o = tl_s1n_29_us_d2h;
+ assign tl_hmac_o = tl_sm1_28_ds_h2d;
+ assign tl_sm1_28_ds_d2h = tl_hmac_i;
+
+ assign tl_rv_plic_o = tl_sm1_29_ds_h2d;
+ assign tl_sm1_29_ds_d2h = tl_rv_plic_i;
+
+ assign tl_pinmux_o = tl_sm1_30_ds_h2d;
+ assign tl_sm1_30_ds_d2h = tl_pinmux_i;
+
+ assign tl_s1n_31_us_h2d = tl_dm_sba_i;
+ assign tl_dm_sba_o = tl_s1n_31_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_15 = 3'd4;
- if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_15 = 3'd0;
- end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
- dev_sel_s1n_15 = 3'd1;
- end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_15 = 3'd2;
- end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_15 = 3'd3;
+ dev_sel_s1n_16 = 3'd4;
+ if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_16 = 3'd0;
+ end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+ dev_sel_s1n_16 = 3'd1;
+ end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_16 = 3'd2;
+ end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_16 = 3'd3;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_20 = 4'd12;
- if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_20 = 4'd0;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
- dev_sel_s1n_20 = 4'd1;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_20 = 4'd2;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_20 = 4'd3;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
- dev_sel_s1n_20 = 4'd4;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_20 = 4'd5;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_20 = 4'd6;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_20 = 4'd7;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_20 = 4'd8;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_20 = 4'd9;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_20 = 4'd10;
- end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_20 = 4'd11;
+ dev_sel_s1n_21 = 4'd13;
+ if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_21 = 4'd0;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+ dev_sel_s1n_21 = 4'd1;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_21 = 4'd2;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_21 = 4'd3;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+ dev_sel_s1n_21 = 4'd4;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_21 = 4'd5;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_21 = 4'd6;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_21 = 4'd7;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_21 = 4'd8;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_21 = 4'd9;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_21 = 4'd10;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_21 = 4'd11;
+ end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+ dev_sel_s1n_21 = 4'd12;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_29 = 4'd11;
- if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_29 = 4'd0;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_29 = 4'd1;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_29 = 4'd2;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
- dev_sel_s1n_29 = 4'd3;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_29 = 4'd4;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_29 = 4'd5;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_29 = 4'd6;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_29 = 4'd7;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_29 = 4'd8;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_29 = 4'd9;
- end else if ((tl_s1n_29_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_29 = 4'd10;
+ dev_sel_s1n_31 = 4'd12;
+ if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_31 = 4'd0;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_31 = 4'd1;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_31 = 4'd2;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
+ dev_sel_s1n_31 = 4'd3;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_31 = 4'd4;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_31 = 4'd5;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_31 = 4'd6;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_31 = 4'd7;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_31 = 4'd8;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_31 = 4'd9;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_31 = 4'd10;
+ end else if ((tl_s1n_31_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+ dev_sel_s1n_31 = 4'd11;
end
end
@@ -433,14 +459,14 @@
.DReqDepth ({4{4'h0}}),
.DRspDepth ({4{4'h0}}),
.N (4)
- ) u_s1n_15 (
+ ) u_s1n_16 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_15_us_h2d),
- .tl_h_o (tl_s1n_15_us_d2h),
- .tl_d_o (tl_s1n_15_ds_h2d),
- .tl_d_i (tl_s1n_15_ds_d2h),
- .dev_select (dev_sel_s1n_15)
+ .tl_h_i (tl_s1n_16_us_h2d),
+ .tl_h_o (tl_s1n_16_us_d2h),
+ .tl_d_o (tl_s1n_16_ds_h2d),
+ .tl_d_i (tl_s1n_16_ds_d2h),
+ .dev_select (dev_sel_s1n_16)
);
tlul_socket_m1 #(
.HReqDepth ({3{4'h0}}),
@@ -448,20 +474,6 @@
.DReqDepth (4'h0),
.DRspDepth (4'h0),
.M (3)
- ) u_sm1_16 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_16_us_h2d),
- .tl_h_o (tl_sm1_16_us_d2h),
- .tl_d_o (tl_sm1_16_ds_h2d),
- .tl_d_i (tl_sm1_16_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
) u_sm1_17 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -471,11 +483,11 @@
.tl_d_i (tl_sm1_17_ds_d2h)
);
tlul_socket_m1 #(
- .HReqDepth ({3{4'h0}}),
- .HRspDepth ({3{4'h0}}),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
- .M (3)
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
) u_sm1_18 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -498,34 +510,34 @@
.tl_d_o (tl_sm1_19_ds_h2d),
.tl_d_i (tl_sm1_19_ds_d2h)
);
+ tlul_socket_m1 #(
+ .HReqDepth ({3{4'h0}}),
+ .HRspDepth ({3{4'h0}}),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (3)
+ ) u_sm1_20 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_20_us_h2d),
+ .tl_h_o (tl_sm1_20_us_d2h),
+ .tl_d_o (tl_sm1_20_ds_h2d),
+ .tl_d_i (tl_sm1_20_ds_d2h)
+ );
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth ({12{4'h0}}),
- .DRspDepth ({12{4'h0}}),
- .N (12)
- ) u_s1n_20 (
+ .DReqDepth ({13{4'h0}}),
+ .DRspDepth ({13{4'h0}}),
+ .N (13)
+ ) u_s1n_21 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_20_us_h2d),
- .tl_h_o (tl_s1n_20_us_d2h),
- .tl_d_o (tl_s1n_20_ds_h2d),
- .tl_d_i (tl_s1n_20_ds_d2h),
- .dev_select (dev_sel_s1n_20)
- );
- tlul_socket_m1 #(
- .HReqPass (2'h0),
- .HRspPass (2'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_21 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_21_us_h2d),
- .tl_h_o (tl_sm1_21_us_d2h),
- .tl_d_o (tl_sm1_21_ds_h2d),
- .tl_d_i (tl_sm1_21_ds_d2h)
+ .tl_h_i (tl_s1n_21_us_h2d),
+ .tl_h_o (tl_s1n_21_us_d2h),
+ .tl_d_o (tl_s1n_21_ds_h2d),
+ .tl_d_i (tl_s1n_21_ds_d2h),
+ .dev_select (dev_sel_s1n_21)
);
tlul_socket_m1 #(
.HReqPass (2'h0),
@@ -625,20 +637,48 @@
.tl_d_o (tl_sm1_28_ds_h2d),
.tl_d_i (tl_sm1_28_ds_d2h)
);
+ tlul_socket_m1 #(
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_29 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_29_us_h2d),
+ .tl_h_o (tl_sm1_29_us_d2h),
+ .tl_d_o (tl_sm1_29_ds_h2d),
+ .tl_d_i (tl_sm1_29_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqPass (2'h0),
+ .HRspPass (2'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_30 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_30_us_h2d),
+ .tl_h_o (tl_sm1_30_us_d2h),
+ .tl_d_o (tl_sm1_30_ds_h2d),
+ .tl_d_i (tl_sm1_30_ds_d2h)
+ );
tlul_socket_1n #(
.HReqPass (1'b0),
.HRspPass (1'b0),
- .DReqPass (11'h0),
- .DRspPass (11'h0),
- .N (11)
- ) u_s1n_29 (
+ .DReqPass (12'h0),
+ .DRspPass (12'h0),
+ .N (12)
+ ) u_s1n_31 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_29_us_h2d),
- .tl_h_o (tl_s1n_29_us_d2h),
- .tl_d_o (tl_s1n_29_ds_h2d),
- .tl_d_i (tl_s1n_29_ds_d2h),
- .dev_select (dev_sel_s1n_29)
+ .tl_h_i (tl_s1n_31_us_h2d),
+ .tl_h_o (tl_s1n_31_us_d2h),
+ .tl_d_o (tl_s1n_31_ds_h2d),
+ .tl_d_i (tl_s1n_31_ds_d2h),
+ .dev_select (dev_sel_s1n_31)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 4c0452c..6d064bb 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -16,25 +16,20 @@
input jtag_td_i,
output jtag_td_o,
- // uart
- input cio_uart_rx_p2d_i,
- output cio_uart_tx_d2p_o,
- output cio_uart_tx_en_d2p_o,
- // gpio
- input [31:0] cio_gpio_gpio_p2d_i,
- output [31:0] cio_gpio_gpio_d2p_o,
- output [31:0] cio_gpio_gpio_en_d2p_o,
- // spi_device
- input cio_spi_device_sck_p2d_i,
- input cio_spi_device_csb_p2d_i,
- input cio_spi_device_mosi_p2d_i,
- output cio_spi_device_miso_d2p_o,
- output cio_spi_device_miso_en_d2p_o,
- // flash_ctrl
- // rv_timer
- // aes
- // hmac
- // rv_plic
+ // Multiplexed I/O
+ input [31:0] mio_in_i,
+ output logic [31:0] mio_out_o,
+ output logic [31:0] mio_oe_o,
+
+ // Dedicated I/O
+ input dio_spi_device_sck_i,
+ input dio_spi_device_csb_i,
+ input dio_spi_device_mosi_i,
+ output logic dio_spi_device_miso_o,
+ output logic dio_spi_device_miso_en_o,
+ input dio_uart_rx_i,
+ output logic dio_uart_tx_o,
+ output logic dio_uart_tx_en_o,
input scanmode_i // 1 for Scan
);
@@ -84,6 +79,8 @@
tl_d2h_t tl_hmac_d_d2h;
tl_h2d_t tl_rv_plic_d_h2d;
tl_d2h_t tl_rv_plic_d_d2h;
+ tl_h2d_t tl_pinmux_d_h2d;
+ tl_d2h_t tl_pinmux_d_d2h;
tl_h2d_t tl_rom_d_h2d;
tl_d2h_t tl_rom_d_d2h;
@@ -100,6 +97,32 @@
//clock wires declaration
logic main_clk;
+ // Signals
+ logic [31:0] m2p;
+ logic [31:0] p2m;
+ logic [31:0] p2m_en;
+ // uart
+ logic cio_uart_rx_p2d;
+ logic cio_uart_tx_d2p;
+ logic cio_uart_tx_en_d2p;
+ // gpio
+ logic [31:0] cio_gpio_gpio_p2d;
+ logic [31:0] cio_gpio_gpio_d2p;
+ logic [31:0] cio_gpio_gpio_en_d2p;
+ // spi_device
+ logic cio_spi_device_sck_p2d;
+ logic cio_spi_device_csb_p2d;
+ logic cio_spi_device_mosi_p2d;
+ logic cio_spi_device_miso_d2p;
+ logic cio_spi_device_miso_en_d2p;
+ // flash_ctrl
+ // rv_timer
+ // aes
+ // hmac
+ // rv_plic
+ // pinmux
+
+
logic [54:0] intr_vector;
// Interrupt source list
logic intr_uart_tx_watermark;
@@ -366,16 +389,22 @@
uart uart (
.tl_i (tl_uart_d_h2d),
.tl_o (tl_uart_d_d2h),
- .cio_rx_i (cio_uart_rx_p2d_i),
- .cio_tx_o (cio_uart_tx_d2p_o),
- .cio_tx_en_o (cio_uart_tx_en_d2p_o),
- .intr_tx_watermark_o (intr_uart_tx_watermark),
- .intr_rx_watermark_o (intr_uart_rx_watermark),
- .intr_tx_overflow_o (intr_uart_tx_overflow),
- .intr_rx_overflow_o (intr_uart_rx_overflow),
- .intr_rx_frame_err_o (intr_uart_rx_frame_err),
- .intr_rx_break_err_o (intr_uart_rx_break_err),
- .intr_rx_timeout_o (intr_uart_rx_timeout),
+
+ // Input
+ .cio_rx_i (cio_uart_rx_p2d),
+
+ // Output
+ .cio_tx_o (cio_uart_tx_d2p),
+ .cio_tx_en_o (cio_uart_tx_en_d2p),
+
+ // Interrupt
+ .intr_tx_watermark_o (intr_uart_tx_watermark),
+ .intr_rx_watermark_o (intr_uart_rx_watermark),
+ .intr_tx_overflow_o (intr_uart_tx_overflow),
+ .intr_rx_overflow_o (intr_uart_rx_overflow),
+ .intr_rx_frame_err_o (intr_uart_rx_frame_err),
+ .intr_rx_break_err_o (intr_uart_rx_break_err),
+ .intr_rx_timeout_o (intr_uart_rx_timeout),
.intr_rx_parity_err_o (intr_uart_rx_parity_err),
.clk_i (main_clk),
@@ -385,9 +414,15 @@
gpio gpio (
.tl_i (tl_gpio_d_h2d),
.tl_o (tl_gpio_d_d2h),
- .cio_gpio_i (cio_gpio_gpio_p2d_i),
- .cio_gpio_o (cio_gpio_gpio_d2p_o),
- .cio_gpio_en_o (cio_gpio_gpio_en_d2p_o),
+
+ // Input
+ .cio_gpio_i (cio_gpio_gpio_p2d),
+
+ // Output
+ .cio_gpio_o (cio_gpio_gpio_d2p),
+ .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
+
+ // Interrupt
.intr_gpio_o (intr_gpio_gpio),
.clk_i (main_clk),
@@ -397,19 +432,26 @@
spi_device spi_device (
.tl_i (tl_spi_device_d_h2d),
.tl_o (tl_spi_device_d_d2h),
- .cio_sck_i (cio_spi_device_sck_p2d_i),
- .cio_csb_i (cio_spi_device_csb_p2d_i),
- .cio_mosi_i (cio_spi_device_mosi_p2d_i),
- .cio_miso_o (cio_spi_device_miso_d2p_o),
- .cio_miso_en_o (cio_spi_device_miso_en_d2p_o),
- .intr_rxf_o (intr_spi_device_rxf),
- .intr_rxlvl_o (intr_spi_device_rxlvl),
- .intr_txlvl_o (intr_spi_device_txlvl),
- .intr_rxerr_o (intr_spi_device_rxerr),
- .intr_rxoverflow_o (intr_spi_device_rxoverflow),
+
+ // Input
+ .cio_sck_i (cio_spi_device_sck_p2d),
+ .cio_csb_i (cio_spi_device_csb_p2d),
+ .cio_mosi_i (cio_spi_device_mosi_p2d),
+
+ // Output
+ .cio_miso_o (cio_spi_device_miso_d2p),
+ .cio_miso_en_o (cio_spi_device_miso_en_d2p),
+
+ // Interrupt
+ .intr_rxf_o (intr_spi_device_rxf),
+ .intr_rxlvl_o (intr_spi_device_rxlvl),
+ .intr_txlvl_o (intr_spi_device_txlvl),
+ .intr_rxerr_o (intr_spi_device_rxerr),
+ .intr_rxoverflow_o (intr_spi_device_rxoverflow),
.intr_txunderflow_o (intr_spi_device_txunderflow),
.scanmode_i (scanmode_i),
+
.clk_i (main_clk),
.rst_ni (spi_device_rst_n)
);
@@ -417,12 +459,15 @@
flash_ctrl flash_ctrl (
.tl_i (tl_flash_ctrl_d_h2d),
.tl_o (tl_flash_ctrl_d_d2h),
+
+ // Interrupt
.intr_prog_empty_o (intr_flash_ctrl_prog_empty),
- .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
- .intr_rd_full_o (intr_flash_ctrl_rd_full),
- .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
- .intr_op_done_o (intr_flash_ctrl_op_done),
- .intr_op_error_o (intr_flash_ctrl_op_error),
+ .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
+ .intr_rd_full_o (intr_flash_ctrl_rd_full),
+ .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
+ .intr_op_done_o (intr_flash_ctrl_op_done),
+ .intr_op_error_o (intr_flash_ctrl_op_error),
+
.flash_o(flash_c2m),
.flash_i(flash_m2c),
@@ -433,6 +478,8 @@
rv_timer rv_timer (
.tl_i (tl_rv_timer_d_h2d),
.tl_o (tl_rv_timer_d_d2h),
+
+ // Interrupt
.intr_timer_expired_0_0_o (intr_rv_timer_timer_expired_0_0),
.clk_i (main_clk),
@@ -450,9 +497,11 @@
hmac hmac (
.tl_i (tl_hmac_d_h2d),
.tl_o (tl_hmac_d_d2h),
+
+ // Interrupt
.intr_hmac_done_o (intr_hmac_hmac_done),
.intr_fifo_full_o (intr_hmac_fifo_full),
- .intr_hmac_err_o (intr_hmac_hmac_err),
+ .intr_hmac_err_o (intr_hmac_hmac_err),
.clk_i (main_clk),
.rst_ni (sys_rst_n)
@@ -463,6 +512,7 @@
) rv_plic (
.tl_i (tl_rv_plic_d_h2d),
.tl_o (tl_rv_plic_d_d2h),
+
.intr_src_i (intr_vector),
.irq_o (irq_plic),
.irq_id_o (irq_id),
@@ -472,6 +522,22 @@
.rst_ni (sys_rst_n)
);
+ pinmux pinmux (
+ .tl_i (tl_pinmux_d_h2d),
+ .tl_o (tl_pinmux_d_d2h),
+
+ .periph_to_mio_i (p2m ),
+ .periph_to_mio_oe_i (p2m_en ),
+ .mio_to_periph_o (m2p ),
+
+ .mio_out_o (mio_out_o),
+ .mio_oe_o (mio_oe_o ),
+ .mio_in_i (mio_in_i ),
+
+ .clk_i (main_clk),
+ .rst_ni (sys_rst_n)
+ );
+
// interrupt assignments
assign intr_vector = {
intr_hmac_hmac_err,
@@ -534,10 +600,32 @@
.tl_aes_i (tl_aes_d_d2h),
.tl_rv_plic_o (tl_rv_plic_d_h2d),
.tl_rv_plic_i (tl_rv_plic_d_d2h),
+ .tl_pinmux_o (tl_pinmux_d_h2d),
+ .tl_pinmux_i (tl_pinmux_d_d2h),
.scanmode_i
);
+ // Pinmux connections
+ assign p2m = {
+ cio_gpio_gpio_d2p
+ };
+ assign p2m_en = {
+ cio_gpio_gpio_en_d2p
+ };
+ assign {
+ cio_gpio_gpio_p2d
+ } = m2p;
+
+ assign cio_spi_device_sck_p2d = dio_spi_device_sck_i;
+ assign cio_spi_device_csb_p2d = dio_spi_device_csb_i;
+ assign cio_spi_device_mosi_p2d = dio_spi_device_mosi_i;
+ assign dio_spi_device_miso_o = cio_spi_device_miso_d2p;
+ assign dio_spi_device_miso_en_o = cio_spi_device_miso_en_d2p;
+ assign cio_uart_rx_p2d = dio_uart_rx_i;
+ assign dio_uart_tx_o = cio_uart_tx_d2p;
+ assign dio_uart_tx_en_o = cio_uart_tx_en_d2p;
+
// make sure scanmode_i is never X (including during reset)
`ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
new file mode 100644
index 0000000..067b74e
--- /dev/null
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -0,0 +1,82 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#ifndef _TOP_EARLGREY_H_
+#define _TOP_EARLGREY_H_
+
+// PERIPH_INSEL ranges from 0 to NUM_MIO + 2 -1}
+// 0 and 1 are tied to value 0 and 1
+#define NUM_MIO 32
+#define NUM_DIO 6
+
+#define PINMUX_GPIO_GPIO_0_IN 0
+#define PINMUX_GPIO_GPIO_1_IN 1
+#define PINMUX_GPIO_GPIO_2_IN 2
+#define PINMUX_GPIO_GPIO_3_IN 3
+#define PINMUX_GPIO_GPIO_4_IN 4
+#define PINMUX_GPIO_GPIO_5_IN 5
+#define PINMUX_GPIO_GPIO_6_IN 6
+#define PINMUX_GPIO_GPIO_7_IN 7
+#define PINMUX_GPIO_GPIO_8_IN 8
+#define PINMUX_GPIO_GPIO_9_IN 9
+#define PINMUX_GPIO_GPIO_10_IN 10
+#define PINMUX_GPIO_GPIO_11_IN 11
+#define PINMUX_GPIO_GPIO_12_IN 12
+#define PINMUX_GPIO_GPIO_13_IN 13
+#define PINMUX_GPIO_GPIO_14_IN 14
+#define PINMUX_GPIO_GPIO_15_IN 15
+#define PINMUX_GPIO_GPIO_16_IN 16
+#define PINMUX_GPIO_GPIO_17_IN 17
+#define PINMUX_GPIO_GPIO_18_IN 18
+#define PINMUX_GPIO_GPIO_19_IN 19
+#define PINMUX_GPIO_GPIO_20_IN 20
+#define PINMUX_GPIO_GPIO_21_IN 21
+#define PINMUX_GPIO_GPIO_22_IN 22
+#define PINMUX_GPIO_GPIO_23_IN 23
+#define PINMUX_GPIO_GPIO_24_IN 24
+#define PINMUX_GPIO_GPIO_25_IN 25
+#define PINMUX_GPIO_GPIO_26_IN 26
+#define PINMUX_GPIO_GPIO_27_IN 27
+#define PINMUX_GPIO_GPIO_28_IN 28
+#define PINMUX_GPIO_GPIO_29_IN 29
+#define PINMUX_GPIO_GPIO_30_IN 30
+#define PINMUX_GPIO_GPIO_31_IN 31
+
+#define PINMUX_VALUE_0_OUT 0
+#define PINMUX_VALUE_1_OUT 1
+#define PINMUX_VALUE_Z_OUT 2
+#define PINMUX_GPIO_GPIO_0_OUT 3
+#define PINMUX_GPIO_GPIO_1_OUT 4
+#define PINMUX_GPIO_GPIO_2_OUT 5
+#define PINMUX_GPIO_GPIO_3_OUT 6
+#define PINMUX_GPIO_GPIO_4_OUT 7
+#define PINMUX_GPIO_GPIO_5_OUT 8
+#define PINMUX_GPIO_GPIO_6_OUT 9
+#define PINMUX_GPIO_GPIO_7_OUT 10
+#define PINMUX_GPIO_GPIO_8_OUT 11
+#define PINMUX_GPIO_GPIO_9_OUT 12
+#define PINMUX_GPIO_GPIO_10_OUT 13
+#define PINMUX_GPIO_GPIO_11_OUT 14
+#define PINMUX_GPIO_GPIO_12_OUT 15
+#define PINMUX_GPIO_GPIO_13_OUT 16
+#define PINMUX_GPIO_GPIO_14_OUT 17
+#define PINMUX_GPIO_GPIO_15_OUT 18
+#define PINMUX_GPIO_GPIO_16_OUT 19
+#define PINMUX_GPIO_GPIO_17_OUT 20
+#define PINMUX_GPIO_GPIO_18_OUT 21
+#define PINMUX_GPIO_GPIO_19_OUT 22
+#define PINMUX_GPIO_GPIO_20_OUT 23
+#define PINMUX_GPIO_GPIO_21_OUT 24
+#define PINMUX_GPIO_GPIO_22_OUT 25
+#define PINMUX_GPIO_GPIO_23_OUT 26
+#define PINMUX_GPIO_GPIO_24_OUT 27
+#define PINMUX_GPIO_GPIO_25_OUT 28
+#define PINMUX_GPIO_GPIO_26_OUT 29
+#define PINMUX_GPIO_GPIO_27_OUT 30
+#define PINMUX_GPIO_GPIO_28_OUT 31
+#define PINMUX_GPIO_GPIO_29_OUT 32
+#define PINMUX_GPIO_GPIO_30_OUT 33
+#define PINMUX_GPIO_GPIO_31_OUT 34
+
+#endif // _TOP_EARLGREY_H_
