[otbn] Better specify and describe errors
* Introduce a list of all errors that OTBN detects.
* Rename recoverable errors to software errors. In the future, software
errors can be made recoverable, or fatal, depending on a config flag.
(For now, all software errors are always recoverable.)
* Improve their description to better describe what caused the
error. Do not give detailed reasons for the errors, as these reasons
are about to be listed in the ISA documentation in much more detail.
* Reference this list as "authorative source" in other places, e.g. in
the register table.
* Rename some errors to be more internally consistent.
Fixes #8238
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/otbn/data/otbn.hjson b/hw/ip/otbn/data/otbn.hjson
index b5997f5..5cc42b0 100644
--- a/hw/ip/otbn/data/otbn.hjson
+++ b/hw/ip/otbn/data/otbn.hjson
@@ -260,8 +260,10 @@
} // register : status
{ name: "ERR_BITS",
desc: '''
- Error bitfield. Reads as non-zero if an error was seen during OTBN
- operation
+ Description of an error detected during an operation.
+
+ Refer to the section "List of Errors" for a detailed description of the
+ errors.
''',
swaccess: "ro",
hwaccess: "hwo",
@@ -269,81 +271,52 @@
{ bits: "0",
name: "bad_data_addr"
resval: 0,
- desc: '''
- A DMEM read or write occurred with an out of bounds or unaligned
- address.
- '''
+ desc: "A `BAD_DATA_ADDR` error was observed."
}
{ bits: "1",
name: "bad_insn_addr"
resval: 0,
- desc: '''
- An IMEM read occurred with an out of bounds or unaligned address.
- '''
+ desc: "A `BAD_INSN_ADDR` error was observed."
}
{ bits: "2",
resval: 0,
name: "call_stack"
- desc: '''
- A instruction tried to pop from an empty call stack or push to a
- full call stack.
- '''
+ desc: "A `CALL_STACK` error was observed."
}
{ bits: "3",
resval: 0,
name: "illegal_insn"
- desc: '''
- One of the following happened:
- <ul>
- <li>An instruction being excuted had an invalid encoding.</li>
- <li>An access occurred for an invalid CSR or WSR.</li>
- </ul>
- '''
+ desc: "An `ILLEGAL_INSN` error was observed."
}
{ bits: "4",
name: "loop"
resval: 0,
- desc: '''
- One of the following happened:
- <ul>
- <li>A loop was started with an iteration count of zero.</li>
- <li>
- The final instruction of a loop was a branch or another loop.
- </li>
- <li>
- A new loop tried to push to a full loop stack (loop nesting
- level too deep).
- </li>
- </ul>
- '''
+ desc: "A `LOOP` error was observed."
}
{ bits: "5",
- name: "fatal_imem"
+ name: "imem_intg_violation"
resval: 0,
- desc: "A fatal error was seen on an instruction fetch."
+ desc: "A `IMEM_INTG_VIOLATION` error was observed."
}
{ bits: "6",
- name: "fatal_dmem"
+ name: "dmem_intg_violation"
resval: 0,
- desc: "A fatal error was seen on a DMEM read."
+ desc: "A `DMEM_INTG_VIOLATION` error was observed."
}
{ bits: "7",
- name: "fatal_reg"
+ name: "reg_intg_violation"
resval: 0,
- desc: "A fatal error was seen on a GPR or WDR read."
+ desc: "A `REG_INTG_VIOLATION` error was observed."
}
{ bits: "8",
- name: "fatal_illegal_bus_access"
+ name: "illegal_bus_access"
resval: 0,
- desc: '''
- A bus-accessible register or memory was read or written while when
- it was not allowed.
- '''
+ desc: "An `ILLEGAL_BUS_ACCESS` error was observed."
}
{ bits: "9",
- name: "fatal_lifecycle_escalation"
+ name: "lifecycle_escalation"
resval: 0,
- desc: "OTBN received a life cycle escalation request from the system."
+ desc: "A `LIFECYCLE_ESCALATION` error was observed."
}
]
} // register : err_bits
@@ -364,7 +337,7 @@
} // register : start_addr
{ name: "FATAL_ALERT_CAUSE",
desc: '''
- The cause of a fatal alert.
+ Description of the error that caused a fatal alert.
The bits of this register correspond to errors that can cause a fatal
alert. Software can read these bits to see what went wrong. Once set,
@@ -374,40 +347,34 @@
hwaccess: "hwo",
fields: [
{ bits: "0",
- name: "bus_integrity_error",
+ name: "bus_intg_violation",
resval: 0,
- desc: '''
- Set by a failed integrity check on a bus access.
- Note that this can happen even when OTBN is not running.
- '''
+ desc: "A `BUS_INTG_VIOLATION` error was observed."
}
{ bits: "1",
- name: "imem_error",
+ name: "imem_intg_violation",
resval: 0,
- desc: "Set on any integrity error in IMEM"
+ desc: "A `IMEM_INTG_VIOLATION` error was observed."
}
{ bits: "2",
- name: "dmem_error",
+ name: "dmem_intg_violation",
resval: 0,
- desc: "Set on any integrity error in DMEM"
+ desc: "A `DMEM_INTG_VIOLATION` error was observed."
}
{ bits: "3",
- name: "reg_error",
+ name: "reg_intg_violation",
resval: 0,
- desc: "Set on any integrity error in a register file"
+ desc: "A `REG_INTG_VIOLATION` error was observed."
}
{ bits: "4",
name: "illegal_bus_access"
resval: 0,
- desc: '''
- A bus-accessible register or memory was read or written while when
- it was not allowed.
- '''
+ desc: "A `ILLEGAL_BUS_ACCESS` error was observed."
}
{ bits: "5",
name: "lifecycle_escalation"
resval: 0,
- desc: "OTBN received a life cycle escalation request from the system."
+ desc: "A `LIFECYCLE_ESCALATION` error was observed."
}
]
} // register : fatal_alert_cause
diff --git a/hw/ip/otbn/doc/_index.md b/hw/ip/otbn/doc/_index.md
index 2db6947..14bd57a 100644
--- a/hw/ip/otbn/doc/_index.md
+++ b/hw/ip/otbn/doc/_index.md
@@ -576,20 +576,23 @@
- OTBN transitions into the [idle state](#design-details-operational-states) (in case of a successful execution, or a recoverable error) or the locked state (in case of a fatal error).
This transition is signaled by raising the `done` interrupt ({{< regref "INTR_STATE.done" >}}), and reflected in the {{< regref "STATUS" >}} register.
-### Error Handling and Reporting {#design-details-error-handling-and-reporting}
+### Errors {#design-details-errors}
-OTBN is able to detect a range of errors.
+OTBN is able to detect a range of errors, which are classified as *software errors* or *fatal errors*.
+A software error is an error in the code that OTBN executes.
+In the absence of an attacker, these errors are due to a programmer's mistake.
+A fatal error is typically the violation of a security property.
+All errors and their classification are listed in the [List of Errors](#design-details-list-of-errors).
+
Whenever an error is detected, OTBN reacts locally, and informs the OpenTitan system about it by raising an alert.
-OTBN generally does not try to recover from errors, and provides no error handling support to code that runs on it.
+OTBN generally does not try to recover from errors itself, and provides no error handling support to code that runs on it.
-OTBN classifies errors as either *recoverable* or *fatal*.
-Errors which could be caused by a programmer's mistake are typically considered recoverable, while errors which are unlikely or impossible to result from a programmer's mistake are considered fatal.
-The description of the {{< regref "ERR_BITS" >}} register lists all possible error causes; those prefixed with `fatal_` are fatal errors.
+OTBN gives host software the option to recover from some errors by restarting the operation.
+All software errors are treated as recoverable and are handled as described in the section [Reaction to Recoverable Errors](#design-details-recoverable-errors).
-Recoverable errors terminate the currently active OTBN operation and return control to the host CPU.
-Fatal errors lock OTBN until it is reset.
+Fatal errors are treated as described in the section [Reaction to Fatal Errors](#design-details-fatal-errors).
-### Recoverable Errors {#design-details-recoverable-errors}
+### Reaction to Recoverable Errors {#design-details-recoverable-errors}
Recoverable errors can be the result of a programming error in OTBN software.
Recoverable errors can only occur during the execution of software on OTBN, and not in other situations in which OTBN might be busy.
@@ -606,7 +609,7 @@
The host software can start another operation on OTBN after a recoverable error was detected.
-### Fatal Errors {#design-details-fatal-errors}
+### Reaction to Fatal Errors {#design-details-fatal-errors}
Fatal errors are generally seen as a sign of an intrusion, resulting in more drastic measures to protect the secrets stored within OTBN.
Fatal errors can occur at any time, even when an OTBN operation isn't in progress.
@@ -630,10 +633,82 @@
This means that the cause will be reflected in {{< regref "FATAL_ALERT_CAUSE" >}}, as described below in [Alerts]({{< relref "#alerts" >}}).
This way, no alert is generated without setting an error code somewhere.
+### List of Errors {#design-details-list-of-errors}
+
+<table>
+ <thead>
+ <tr>
+ <th>Name</th>
+ <th>Class</th>
+ <th>Description</th>
+ </tr>
+ </thead>
+ <tbody>
+ <tr>
+ <td><code>BAD_DATA_ADDR<code></td>
+ <td>software</td>
+ <td>A data memory access occurred with an out of bounds or unaligned access.</td>
+ </tr>
+ <tr>
+ <td><code>BAD_INSN_ADDR<code></td>
+ <td>software</td>
+ <td>An instruction memory access occurred with an out of bounds or unaligned access.</td>
+ </tr>
+ <tr>
+ <td><code>CALL_STACK<code></td>
+ <td>software</td>
+ <td>An instruction tried to pop from an empty call stack or push to a full call stack.</td>
+ </tr>
+ <tr>
+ <td><code>ILLEGAL_INSN<code></td>
+ <td>software</td>
+ <td>
+ An illegal instruction was about to be executed.
+ </td>
+ <tr>
+ <td><code>LOOP<code></td>
+ <td>software</td>
+ <td>
+ A loop stack-related error was detected.
+ </td>
+ </tr>
+ <tr>
+ <td><code>IMEM_INTG_VIOLATION<code></td>
+ <td>fatal</td>
+ <td>Data read from the instruction memory failed the integrity checks.</td>
+ </tr>
+ <tr>
+ <td><code>DMEM_INTG_VIOLATION<code></td>
+ <td>fatal</td>
+ <td>Data read from the data memory failed the integrity checks.</td>
+ </tr>
+ <tr>
+ <td><code>REG_INTG_VIOLATION<code></td>
+ <td>fatal</td>
+ <td>Data read from a GPR or WDR failed the integrity checks.</td>
+ </tr>
+ <tr>
+ <td><code>BUS_INTG_VIOLATION<code></td>
+ <td>fatal</td>
+ <td>An incoming bus transaction failed the integrity checks.</td>
+ </tr>
+ <tr>
+ <td><code>ILLEGAL_BUS_ACCESS<code></td>
+ <td>fatal</td>
+ <td>A bus-accessible register or memory was accessed when not allowed.</td>
+ </tr>
+ <tr>
+ <td><code>LIFECYCLE_ESCALATION<code></td>
+ <td>fatal</td>
+ <td>A life cycle escalation request was received.</td>
+ </tr>
+ </tbody>
+</table>
+
### Alerts
+An alert is a reaction to an error that OTBN detected.
OTBN has two alerts, one recoverable and one fatal.
-The {{< regref "ERR_BITS" >}} register documentation has a detailed list of error conditions, those with 'fatal' in the name raise a **fatal alert**, otherwise they raise a **recoverable alert**.
A **recoverable alert** is a one-time triggered alert caused by [recoverable errors](#design-details-recoverable-errors).
The error that caused the alert can be determined by reading the {{< regref "ERR_BITS" >}} register.
diff --git a/hw/ip/otbn/dv/otbnsim/sim/constants.py b/hw/ip/otbn/dv/otbnsim/sim/constants.py
index a8b576f..a232e11 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/constants.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/constants.py
@@ -27,8 +27,8 @@
CALL_STACK = 1 << 2
ILLEGAL_INSN = 1 << 3
LOOP = 1 << 4
- FATAL_IMEM = 1 << 5
- FATAL_DMEM = 1 << 6
- FATAL_REG = 1 << 7
- FATAL_ILLEGAL_BUS_ACCESS = 1 << 8
- FATAL_LIFECYCLE_ESCALATION = 1 << 9
+ IMEM_INTG_VIOLATION = 1 << 5
+ DMEM_INTG_VIOLATION = 1 << 6
+ REG_INTG_VIOLATION = 1 << 7
+ ILLEGAL_BUS_ACCESS = 1 << 8
+ LIFECYCLE_ESCALATION = 1 << 9
diff --git a/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv b/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv
index bf0cd5e..b706be0 100644
--- a/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv
+++ b/hw/ip/otbn/dv/uvm/env/otbn_env_cfg.sv
@@ -57,7 +57,7 @@
model_agent_cfg = otbn_model_agent_cfg::type_id::create("model_agent_cfg");
super.initialize(csr_base_addr);
- tl_intg_alert_fields[ral.fatal_alert_cause.bus_integrity_error] = 1;
+ tl_intg_alert_fields[ral.fatal_alert_cause.bus_intg_violation] = 1;
endfunction
endclass
diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/otbn/rtl/otbn.sv
index 6c8a58c..834f3b6 100644
--- a/hw/ip/otbn/rtl/otbn.sv
+++ b/hw/ip/otbn/rtl/otbn.sv
@@ -186,7 +186,7 @@
logic imem_rvalid_bus;
logic [1:0] imem_rerror_bus;
- logic imem_bus_integrity_error;
+ logic imem_bus_intg_violation;
logic [ImemAddrWidth-1:0] imem_addr_core;
assign imem_index_core = imem_addr_core[ImemAddrWidth-1:2];
@@ -293,21 +293,21 @@
.EnableDataIntgPt (1)
) u_tlul_adapter_sram_imem (
.clk_i,
- .rst_ni (rst_n ),
- .tl_i (tl_win_h2d[TlWinImem] ),
- .tl_o (tl_win_d2h[TlWinImem] ),
- .en_ifetch_i (tlul_pkg::InstrDis ),
- .req_o (imem_req_bus ),
- .req_type_o ( ),
- .gnt_i (imem_gnt_bus ),
- .we_o (imem_write_bus ),
- .addr_o (imem_index_bus ),
- .wdata_o (imem_wdata_bus ),
- .wmask_o (imem_wmask_bus ),
- .intg_error_o(imem_bus_integrity_error),
- .rdata_i (imem_rdata_bus ),
- .rvalid_i (imem_rvalid_bus ),
- .rerror_i (imem_rerror_bus )
+ .rst_ni (rst_n ),
+ .tl_i (tl_win_h2d[TlWinImem] ),
+ .tl_o (tl_win_d2h[TlWinImem] ),
+ .en_ifetch_i (tlul_pkg::InstrDis ),
+ .req_o (imem_req_bus ),
+ .req_type_o ( ),
+ .gnt_i (imem_gnt_bus ),
+ .we_o (imem_write_bus ),
+ .addr_o (imem_index_bus ),
+ .wdata_o (imem_wdata_bus ),
+ .wmask_o (imem_wmask_bus ),
+ .intg_error_o(imem_bus_intg_violation),
+ .rdata_i (imem_rdata_bus ),
+ .rvalid_i (imem_rvalid_bus ),
+ .rerror_i (imem_rerror_bus )
);
@@ -402,7 +402,7 @@
logic dmem_rvalid_bus;
logic [1:0] dmem_rerror_bus;
- logic dmem_bus_integrity_error;
+ logic dmem_bus_intg_violation;
logic [DmemAddrWidth-1:0] dmem_addr_core;
assign dmem_index_core = dmem_addr_core[DmemAddrWidth-1:DmemAddrWidth-DmemIndexWidth];
@@ -491,21 +491,21 @@
.EnableDataIntgPt (1)
) u_tlul_adapter_sram_dmem (
.clk_i,
- .rst_ni (rst_n ),
- .tl_i (tl_win_h2d[TlWinDmem] ),
- .tl_o (tl_win_d2h[TlWinDmem] ),
- .en_ifetch_i (tlul_pkg::InstrDis ),
- .req_o (dmem_req_bus ),
- .req_type_o ( ),
- .gnt_i (dmem_gnt_bus ),
- .we_o (dmem_write_bus ),
- .addr_o (dmem_index_bus ),
- .wdata_o (dmem_wdata_bus ),
- .wmask_o (dmem_wmask_bus ),
- .intg_error_o(dmem_bus_integrity_error),
- .rdata_i (dmem_rdata_bus ),
- .rvalid_i (dmem_rvalid_bus ),
- .rerror_i (dmem_rerror_bus )
+ .rst_ni (rst_n ),
+ .tl_i (tl_win_h2d[TlWinDmem] ),
+ .tl_o (tl_win_d2h[TlWinDmem] ),
+ .en_ifetch_i (tlul_pkg::InstrDis ),
+ .req_o (dmem_req_bus ),
+ .req_type_o ( ),
+ .gnt_i (dmem_gnt_bus ),
+ .we_o (dmem_write_bus ),
+ .addr_o (dmem_index_bus ),
+ .wdata_o (dmem_wdata_bus ),
+ .wmask_o (dmem_wmask_bus ),
+ .intg_error_o(dmem_bus_intg_violation),
+ .rdata_i (dmem_rdata_bus ),
+ .rvalid_i (dmem_rvalid_bus ),
+ .rerror_i (dmem_rerror_bus )
);
// Mux core and bus access into dmem
@@ -550,7 +550,7 @@
// Registers =================================================================
- logic reg_bus_integrity_error;
+ logic reg_bus_intg_violation;
otbn_reg_top u_reg (
.clk_i,
@@ -563,13 +563,13 @@
.reg2hw,
.hw2reg,
- .intg_err_o(reg_bus_integrity_error),
+ .intg_err_o(reg_bus_intg_violation),
.devmode_i (1'b1)
);
- logic bus_integrity_error;
- assign bus_integrity_error = (imem_bus_integrity_error | dmem_bus_integrity_error |
- reg_bus_integrity_error);
+ logic bus_intg_violation;
+ assign bus_intg_violation = (imem_bus_intg_violation | dmem_bus_intg_violation |
+ reg_bus_intg_violation);
// CMD register
// start is flopped to avoid long timing paths from the TL fabric into OTBN internals.
@@ -615,20 +615,20 @@
assign hw2reg.err_bits.loop.de = done;
assign hw2reg.err_bits.loop.d = err_bits.loop;
- assign hw2reg.err_bits.fatal_imem.de = done;
- assign hw2reg.err_bits.fatal_imem.d = err_bits.fatal_imem;
+ assign hw2reg.err_bits.imem_intg_violation.de = done;
+ assign hw2reg.err_bits.imem_intg_violation.d = err_bits.imem_intg_violation;
- assign hw2reg.err_bits.fatal_dmem.de = done;
- assign hw2reg.err_bits.fatal_dmem.d = err_bits.fatal_dmem;
+ assign hw2reg.err_bits.dmem_intg_violation.de = done;
+ assign hw2reg.err_bits.dmem_intg_violation.d = err_bits.dmem_intg_violation;
- assign hw2reg.err_bits.fatal_reg.de = done;
- assign hw2reg.err_bits.fatal_reg.d = err_bits.fatal_reg;
+ assign hw2reg.err_bits.reg_intg_violation.de = done;
+ assign hw2reg.err_bits.reg_intg_violation.d = err_bits.reg_intg_violation;
- assign hw2reg.err_bits.fatal_illegal_bus_access.de = done;
- assign hw2reg.err_bits.fatal_illegal_bus_access.d = err_bits.fatal_illegal_bus_access;
+ assign hw2reg.err_bits.illegal_bus_access.de = done;
+ assign hw2reg.err_bits.illegal_bus_access.d = err_bits.illegal_bus_access;
- assign hw2reg.err_bits.fatal_lifecycle_escalation.de = done;
- assign hw2reg.err_bits.fatal_lifecycle_escalation.d = err_bits.fatal_lifecycle_escalation;
+ assign hw2reg.err_bits.lifecycle_escalation.de = done;
+ assign hw2reg.err_bits.lifecycle_escalation.d = err_bits.lifecycle_escalation;
// START_ADDR register
assign start_addr = reg2hw.start_addr.q[ImemAddrWidth-1:0];
@@ -637,15 +637,15 @@
// FATAL_ALERT_CAUSE register. The .de and .d values are equal for each bit, so that it can only
// be set, not cleared.
- assign hw2reg.fatal_alert_cause.bus_integrity_error.de = bus_integrity_error;
- assign hw2reg.fatal_alert_cause.bus_integrity_error.d = bus_integrity_error;
- assign hw2reg.fatal_alert_cause.imem_error.de = imem_rerror;
- assign hw2reg.fatal_alert_cause.imem_error.d = imem_rerror;
- assign hw2reg.fatal_alert_cause.dmem_error.de = dmem_rerror;
- assign hw2reg.fatal_alert_cause.dmem_error.d = dmem_rerror;
+ assign hw2reg.fatal_alert_cause.bus_intg_violation.de = bus_intg_violation;
+ assign hw2reg.fatal_alert_cause.bus_intg_violation.d = bus_intg_violation;
+ assign hw2reg.fatal_alert_cause.imem_intg_violation.de = imem_rerror;
+ assign hw2reg.fatal_alert_cause.imem_intg_violation.d = imem_rerror;
+ assign hw2reg.fatal_alert_cause.dmem_intg_violation.de = dmem_rerror;
+ assign hw2reg.fatal_alert_cause.dmem_intg_violation.d = dmem_rerror;
// TODO: Register file errors
- assign hw2reg.fatal_alert_cause.reg_error.de = 0;
- assign hw2reg.fatal_alert_cause.reg_error.d = 0;
+ assign hw2reg.fatal_alert_cause.reg_intg_violation.de = 0;
+ assign hw2reg.fatal_alert_cause.reg_intg_violation.d = 0;
assign hw2reg.fatal_alert_cause.illegal_bus_access.de = illegal_bus_access_d;
assign hw2reg.fatal_alert_cause.illegal_bus_access.d = illegal_bus_access_d;
assign hw2reg.fatal_alert_cause.lifecycle_escalation.de = lifecycle_escalation;
@@ -665,7 +665,7 @@
logic [NumAlerts-1:0] alerts;
assign alerts[AlertFatal] = illegal_bus_access_d |
- bus_integrity_error |
+ bus_intg_violation |
imem_rerror |
dmem_rerror;
assign alerts[AlertRecov] = 1'b0; // TODO: Implement
diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/otbn/rtl/otbn_controller.sv
index 7aaabd4..436a039 100644
--- a/hw/ip/otbn/rtl/otbn_controller.sv
+++ b/hw/ip/otbn/rtl/otbn_controller.sv
@@ -336,16 +336,16 @@
// or illegal WSR/CSR referenced).
assign illegal_insn_static = insn_illegal_i | ispr_err;
- assign err_bits_o.fatal_lifecycle_escalation = lifecycle_escalation_i;
- assign err_bits_o.fatal_illegal_bus_access = illegal_bus_access_i;
- assign err_bits_o.fatal_reg = rf_base_rd_data_err_i | rf_bignum_rd_data_err_i;
- assign err_bits_o.fatal_imem = insn_fetch_err_i;
- assign err_bits_o.fatal_dmem = lsu_rdata_err_i;
- assign err_bits_o.illegal_insn = illegal_insn_static | rf_indirect_err;
- assign err_bits_o.bad_data_addr = dmem_addr_err;
- assign err_bits_o.loop = loop_err;
- assign err_bits_o.call_stack = rf_base_call_stack_err_i;
- assign err_bits_o.bad_insn_addr = imem_addr_err;
+ assign err_bits_o.lifecycle_escalation = lifecycle_escalation_i;
+ assign err_bits_o.illegal_bus_access = illegal_bus_access_i;
+ assign err_bits_o.reg_intg_violation = rf_base_rd_data_err_i | rf_bignum_rd_data_err_i;
+ assign err_bits_o.imem_intg_violation = insn_fetch_err_i;
+ assign err_bits_o.dmem_intg_violation = lsu_rdata_err_i;
+ assign err_bits_o.illegal_insn = illegal_insn_static | rf_indirect_err;
+ assign err_bits_o.bad_data_addr = dmem_addr_err;
+ assign err_bits_o.loop = loop_err;
+ assign err_bits_o.call_stack = rf_base_call_stack_err_i;
+ assign err_bits_o.bad_insn_addr = imem_addr_err;
assign err = |err_bits_o;
diff --git a/hw/ip/otbn/rtl/otbn_pkg.sv b/hw/ip/otbn/rtl/otbn_pkg.sv
index f90ea1f..47f970a 100644
--- a/hw/ip/otbn/rtl/otbn_pkg.sv
+++ b/hw/ip/otbn/rtl/otbn_pkg.sv
@@ -70,11 +70,11 @@
//
// Note: These errors are duplicated in other places. If updating them here, update those too.
typedef struct packed {
- logic fatal_lifecycle_escalation;
- logic fatal_illegal_bus_access;
- logic fatal_reg;
- logic fatal_dmem;
- logic fatal_imem;
+ logic lifecycle_escalation;
+ logic illegal_bus_access;
+ logic reg_intg_violation;
+ logic dmem_intg_violation;
+ logic imem_intg_violation;
logic loop;
logic illegal_insn;
logic call_stack;
diff --git a/hw/ip/otbn/rtl/otbn_reg_pkg.sv b/hw/ip/otbn/rtl/otbn_reg_pkg.sv
index de8fab8..5c9fce7 100644
--- a/hw/ip/otbn/rtl/otbn_reg_pkg.sv
+++ b/hw/ip/otbn/rtl/otbn_reg_pkg.sv
@@ -82,42 +82,42 @@
struct packed {
logic d;
logic de;
- } fatal_imem;
+ } imem_intg_violation;
struct packed {
logic d;
logic de;
- } fatal_dmem;
+ } dmem_intg_violation;
struct packed {
logic d;
logic de;
- } fatal_reg;
+ } reg_intg_violation;
struct packed {
logic d;
logic de;
- } fatal_illegal_bus_access;
+ } illegal_bus_access;
struct packed {
logic d;
logic de;
- } fatal_lifecycle_escalation;
+ } lifecycle_escalation;
} otbn_hw2reg_err_bits_reg_t;
typedef struct packed {
struct packed {
logic d;
logic de;
- } bus_integrity_error;
+ } bus_intg_violation;
struct packed {
logic d;
logic de;
- } imem_error;
+ } imem_intg_violation;
struct packed {
logic d;
logic de;
- } dmem_error;
+ } dmem_intg_violation;
struct packed {
logic d;
logic de;
- } reg_error;
+ } reg_intg_violation;
struct packed {
logic d;
logic de;
diff --git a/hw/ip/otbn/rtl/otbn_reg_top.sv b/hw/ip/otbn/rtl/otbn_reg_top.sv
index a8fc8cb..09284ac 100644
--- a/hw/ip/otbn/rtl/otbn_reg_top.sv
+++ b/hw/ip/otbn/rtl/otbn_reg_top.sv
@@ -181,17 +181,17 @@
logic err_bits_call_stack_qs;
logic err_bits_illegal_insn_qs;
logic err_bits_loop_qs;
- logic err_bits_fatal_imem_qs;
- logic err_bits_fatal_dmem_qs;
- logic err_bits_fatal_reg_qs;
- logic err_bits_fatal_illegal_bus_access_qs;
- logic err_bits_fatal_lifecycle_escalation_qs;
+ logic err_bits_imem_intg_violation_qs;
+ logic err_bits_dmem_intg_violation_qs;
+ logic err_bits_reg_intg_violation_qs;
+ logic err_bits_illegal_bus_access_qs;
+ logic err_bits_lifecycle_escalation_qs;
logic start_addr_we;
logic [31:0] start_addr_wd;
- logic fatal_alert_cause_bus_integrity_error_qs;
- logic fatal_alert_cause_imem_error_qs;
- logic fatal_alert_cause_dmem_error_qs;
- logic fatal_alert_cause_reg_error_qs;
+ logic fatal_alert_cause_bus_intg_violation_qs;
+ logic fatal_alert_cause_imem_intg_violation_qs;
+ logic fatal_alert_cause_dmem_intg_violation_qs;
+ logic fatal_alert_cause_reg_intg_violation_qs;
logic fatal_alert_cause_illegal_bus_access_qs;
logic fatal_alert_cause_lifecycle_escalation_qs;
logic insn_cnt_re;
@@ -451,12 +451,12 @@
.qs (err_bits_loop_qs)
);
- // F[fatal_imem]: 5:5
+ // F[imem_intg_violation]: 5:5
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_err_bits_fatal_imem (
+ ) u_err_bits_imem_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -465,23 +465,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.err_bits.fatal_imem.de),
- .d (hw2reg.err_bits.fatal_imem.d),
+ .de (hw2reg.err_bits.imem_intg_violation.de),
+ .d (hw2reg.err_bits.imem_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (err_bits_fatal_imem_qs)
+ .qs (err_bits_imem_intg_violation_qs)
);
- // F[fatal_dmem]: 6:6
+ // F[dmem_intg_violation]: 6:6
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_err_bits_fatal_dmem (
+ ) u_err_bits_dmem_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -490,23 +490,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.err_bits.fatal_dmem.de),
- .d (hw2reg.err_bits.fatal_dmem.d),
+ .de (hw2reg.err_bits.dmem_intg_violation.de),
+ .d (hw2reg.err_bits.dmem_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (err_bits_fatal_dmem_qs)
+ .qs (err_bits_dmem_intg_violation_qs)
);
- // F[fatal_reg]: 7:7
+ // F[reg_intg_violation]: 7:7
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_err_bits_fatal_reg (
+ ) u_err_bits_reg_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -515,23 +515,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.err_bits.fatal_reg.de),
- .d (hw2reg.err_bits.fatal_reg.d),
+ .de (hw2reg.err_bits.reg_intg_violation.de),
+ .d (hw2reg.err_bits.reg_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (err_bits_fatal_reg_qs)
+ .qs (err_bits_reg_intg_violation_qs)
);
- // F[fatal_illegal_bus_access]: 8:8
+ // F[illegal_bus_access]: 8:8
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_err_bits_fatal_illegal_bus_access (
+ ) u_err_bits_illegal_bus_access (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -540,23 +540,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.err_bits.fatal_illegal_bus_access.de),
- .d (hw2reg.err_bits.fatal_illegal_bus_access.d),
+ .de (hw2reg.err_bits.illegal_bus_access.de),
+ .d (hw2reg.err_bits.illegal_bus_access.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (err_bits_fatal_illegal_bus_access_qs)
+ .qs (err_bits_illegal_bus_access_qs)
);
- // F[fatal_lifecycle_escalation]: 9:9
+ // F[lifecycle_escalation]: 9:9
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_err_bits_fatal_lifecycle_escalation (
+ ) u_err_bits_lifecycle_escalation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -565,15 +565,15 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.err_bits.fatal_lifecycle_escalation.de),
- .d (hw2reg.err_bits.fatal_lifecycle_escalation.d),
+ .de (hw2reg.err_bits.lifecycle_escalation.de),
+ .d (hw2reg.err_bits.lifecycle_escalation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (err_bits_fatal_lifecycle_escalation_qs)
+ .qs (err_bits_lifecycle_escalation_qs)
);
@@ -604,12 +604,12 @@
// R[fatal_alert_cause]: V(False)
- // F[bus_integrity_error]: 0:0
+ // F[bus_intg_violation]: 0:0
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_fatal_alert_cause_bus_integrity_error (
+ ) u_fatal_alert_cause_bus_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -618,23 +618,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.fatal_alert_cause.bus_integrity_error.de),
- .d (hw2reg.fatal_alert_cause.bus_integrity_error.d),
+ .de (hw2reg.fatal_alert_cause.bus_intg_violation.de),
+ .d (hw2reg.fatal_alert_cause.bus_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (fatal_alert_cause_bus_integrity_error_qs)
+ .qs (fatal_alert_cause_bus_intg_violation_qs)
);
- // F[imem_error]: 1:1
+ // F[imem_intg_violation]: 1:1
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_fatal_alert_cause_imem_error (
+ ) u_fatal_alert_cause_imem_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -643,23 +643,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.fatal_alert_cause.imem_error.de),
- .d (hw2reg.fatal_alert_cause.imem_error.d),
+ .de (hw2reg.fatal_alert_cause.imem_intg_violation.de),
+ .d (hw2reg.fatal_alert_cause.imem_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (fatal_alert_cause_imem_error_qs)
+ .qs (fatal_alert_cause_imem_intg_violation_qs)
);
- // F[dmem_error]: 2:2
+ // F[dmem_intg_violation]: 2:2
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_fatal_alert_cause_dmem_error (
+ ) u_fatal_alert_cause_dmem_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -668,23 +668,23 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.fatal_alert_cause.dmem_error.de),
- .d (hw2reg.fatal_alert_cause.dmem_error.d),
+ .de (hw2reg.fatal_alert_cause.dmem_intg_violation.de),
+ .d (hw2reg.fatal_alert_cause.dmem_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (fatal_alert_cause_dmem_error_qs)
+ .qs (fatal_alert_cause_dmem_intg_violation_qs)
);
- // F[reg_error]: 3:3
+ // F[reg_intg_violation]: 3:3
prim_subreg #(
.DW (1),
.SwAccess(prim_subreg_pkg::SwAccessRO),
.RESVAL (1'h0)
- ) u_fatal_alert_cause_reg_error (
+ ) u_fatal_alert_cause_reg_intg_violation (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -693,15 +693,15 @@
.wd ('0),
// from internal hardware
- .de (hw2reg.fatal_alert_cause.reg_error.de),
- .d (hw2reg.fatal_alert_cause.reg_error.d),
+ .de (hw2reg.fatal_alert_cause.reg_intg_violation.de),
+ .d (hw2reg.fatal_alert_cause.reg_intg_violation.d),
// to internal hardware
.qe (),
.q (),
// to register interface (read)
- .qs (fatal_alert_cause_reg_error_qs)
+ .qs (fatal_alert_cause_reg_intg_violation_qs)
);
// F[illegal_bus_access]: 4:4
@@ -860,11 +860,11 @@
reg_rdata_next[2] = err_bits_call_stack_qs;
reg_rdata_next[3] = err_bits_illegal_insn_qs;
reg_rdata_next[4] = err_bits_loop_qs;
- reg_rdata_next[5] = err_bits_fatal_imem_qs;
- reg_rdata_next[6] = err_bits_fatal_dmem_qs;
- reg_rdata_next[7] = err_bits_fatal_reg_qs;
- reg_rdata_next[8] = err_bits_fatal_illegal_bus_access_qs;
- reg_rdata_next[9] = err_bits_fatal_lifecycle_escalation_qs;
+ reg_rdata_next[5] = err_bits_imem_intg_violation_qs;
+ reg_rdata_next[6] = err_bits_dmem_intg_violation_qs;
+ reg_rdata_next[7] = err_bits_reg_intg_violation_qs;
+ reg_rdata_next[8] = err_bits_illegal_bus_access_qs;
+ reg_rdata_next[9] = err_bits_lifecycle_escalation_qs;
end
addr_hit[7]: begin
@@ -872,10 +872,10 @@
end
addr_hit[8]: begin
- reg_rdata_next[0] = fatal_alert_cause_bus_integrity_error_qs;
- reg_rdata_next[1] = fatal_alert_cause_imem_error_qs;
- reg_rdata_next[2] = fatal_alert_cause_dmem_error_qs;
- reg_rdata_next[3] = fatal_alert_cause_reg_error_qs;
+ reg_rdata_next[0] = fatal_alert_cause_bus_intg_violation_qs;
+ reg_rdata_next[1] = fatal_alert_cause_imem_intg_violation_qs;
+ reg_rdata_next[2] = fatal_alert_cause_dmem_intg_violation_qs;
+ reg_rdata_next[3] = fatal_alert_cause_reg_intg_violation_qs;
reg_rdata_next[4] = fatal_alert_cause_illegal_bus_access_qs;
reg_rdata_next[5] = fatal_alert_cause_lifecycle_escalation_qs;
end
diff --git a/sw/device/lib/dif/dif_otbn.c b/sw/device/lib/dif/dif_otbn.c
index 44d0e21..0188f5e 100644
--- a/sw/device/lib/dif/dif_otbn.c
+++ b/sw/device/lib/dif/dif_otbn.c
@@ -23,17 +23,20 @@
"Layout of error bits changed.");
static_assert(kDifOtbnErrBitsLoop == (1 << OTBN_ERR_BITS_LOOP_BIT),
"Layout of error bits changed.");
-static_assert(kDifOtbnErrBitsFatalImem == (1 << OTBN_ERR_BITS_FATAL_IMEM_BIT),
+static_assert(kDifOtbnErrBitsImemIntgViolation ==
+ (1 << OTBN_ERR_BITS_IMEM_INTG_VIOLATION_BIT),
"Layout of error bits changed.");
-static_assert(kDifOtbnErrBitsFatalDmem == (1 << OTBN_ERR_BITS_FATAL_DMEM_BIT),
+static_assert(kDifOtbnErrBitsDmemIntgViolation ==
+ (1 << OTBN_ERR_BITS_DMEM_INTG_VIOLATION_BIT),
"Layout of error bits changed.");
-static_assert(kDifOtbnErrBitsFatalReg == (1 << OTBN_ERR_BITS_FATAL_REG_BIT),
+static_assert(kDifOtbnErrBitsRegIntgViolation ==
+ (1 << OTBN_ERR_BITS_REG_INTG_VIOLATION_BIT),
"Layout of error bits changed.");
-static_assert(kDifOtbnErrBitsFatalIllegalBusAccess ==
- (1 << OTBN_ERR_BITS_FATAL_ILLEGAL_BUS_ACCESS_BIT),
+static_assert(kDifOtbnErrBitsIllegalBusAccess ==
+ (1 << OTBN_ERR_BITS_ILLEGAL_BUS_ACCESS_BIT),
"Layout of error bits changed.");
-static_assert(kDifOtbnErrBitsFatalLifecycleEscalation ==
- (1 << OTBN_ERR_BITS_FATAL_LIFECYCLE_ESCALATION_BIT),
+static_assert(kDifOtbnErrBitsLifecycleEscalation ==
+ (1 << OTBN_ERR_BITS_LIFECYCLE_ESCALATION_BIT),
"Layout of error bits changed.");
/**
diff --git a/sw/device/lib/dif/dif_otbn.h b/sw/device/lib/dif/dif_otbn.h
index c7323be..f67620c 100644
--- a/sw/device/lib/dif/dif_otbn.h
+++ b/sw/device/lib/dif/dif_otbn.h
@@ -94,29 +94,26 @@
*/
typedef enum dif_otbn_err_bits {
kDifOtbnErrBitsNoError = 0,
- /** Load or store to invalid address. */
+ /** A BAD_DATA_ADDR error was observed. */
kDifOtbnErrBitsBadDataAddr = (1 << 0),
- /** Instruction fetch from invalid address. */
+ /** A BAD_INSN_ADDR error was observed. */
kDifOtbnErrBitsBadInsnAddr = (1 << 1),
- /** Call stack underflow or overflow. */
+ /** A CALL_STACK error was observed. */
kDifOtbnErrBitsCallStack = (1 << 2),
- /** Illegal instruction execution attempted */
+ /** An ILLEGAL_INSN error was observed. */
kDifOtbnErrBitsIllegalInsn = (1 << 3),
- /** LOOP[I] related error */
+ /** A LOOP error was observed. */
kDifOtbnErrBitsLoop = (1 << 4),
- /** Error seen in Imem read */
- kDifOtbnErrBitsFatalImem = (1 << 5),
- /** Error seen in Dmem read */
- kDifOtbnErrBitsFatalDmem = (1 << 6),
- /** Error seen in RF read */
- kDifOtbnErrBitsFatalReg = (1 << 7),
- /**
- * A bus-accessible register or memory was read or written while when it was
- * not allowed.
- */
- kDifOtbnErrBitsFatalIllegalBusAccess = (1 << 8),
- /** OTBN received a life cycle escalation request from the system */
- kDifOtbnErrBitsFatalLifecycleEscalation = (1 << 9),
+ /** A IMEM_INTG_VIOLATION error was observed. */
+ kDifOtbnErrBitsImemIntgViolation = (1 << 5),
+ /** A DMEM_INTG_VIOLATION error was observed. */
+ kDifOtbnErrBitsDmemIntgViolation = (1 << 6),
+ /** A REG_INTG_VIOLATION error was observed. */
+ kDifOtbnErrBitsRegIntgViolation = (1 << 7),
+ /** An ILLEGAL_BUS_ACCESS error was observed. */
+ kDifOtbnErrBitsIllegalBusAccess = (1 << 8),
+ /** A LIFECYCLE_ESCALATION error was observed. */
+ kDifOtbnErrBitsLifecycleEscalation = (1 << 9),
} dif_otbn_err_bits_t;
/**
diff --git a/sw/device/lib/dif/dif_otbn_unittest.cc b/sw/device/lib/dif/dif_otbn_unittest.cc
index ec54df1..b7dc556 100644
--- a/sw/device/lib/dif/dif_otbn_unittest.cc
+++ b/sw/device/lib/dif/dif_otbn_unittest.cc
@@ -276,11 +276,12 @@
TEST_F(GetErrBitsTest, Success) {
EXPECT_READ32(OTBN_ERR_BITS_REG_OFFSET,
- kDifOtbnErrBitsIllegalInsn | kDifOtbnErrBitsFatalReg);
+ kDifOtbnErrBitsIllegalInsn | kDifOtbnErrBitsRegIntgViolation);
dif_otbn_err_bits_t err_bits;
EXPECT_EQ(dif_otbn_get_err_bits(&dif_otbn_, &err_bits), kDifOtbnOk);
- EXPECT_EQ(err_bits, kDifOtbnErrBitsIllegalInsn | kDifOtbnErrBitsFatalReg);
+ EXPECT_EQ(err_bits,
+ kDifOtbnErrBitsIllegalInsn | kDifOtbnErrBitsRegIntgViolation);
}
class GetInsnCntTest : public OtbnTest {};
diff --git a/sw/device/silicon_creator/lib/drivers/otbn.c b/sw/device/silicon_creator/lib/drivers/otbn.c
index d1c21a2..7c9326e 100644
--- a/sw/device/silicon_creator/lib/drivers/otbn.c
+++ b/sw/device/silicon_creator/lib/drivers/otbn.c
@@ -24,13 +24,16 @@
ASSERT_ERR_BIT_MATCH(kOtbnErrBitsCallStack, OTBN_ERR_BITS_CALL_STACK_BIT);
ASSERT_ERR_BIT_MATCH(kOtbnErrBitsIllegalInsn, OTBN_ERR_BITS_ILLEGAL_INSN_BIT);
ASSERT_ERR_BIT_MATCH(kOtbnErrBitsLoop, OTBN_ERR_BITS_LOOP_BIT);
-ASSERT_ERR_BIT_MATCH(kOtbnErrBitsFatalImem, OTBN_ERR_BITS_FATAL_IMEM_BIT);
-ASSERT_ERR_BIT_MATCH(kOtbnErrBitsFatalDmem, OTBN_ERR_BITS_FATAL_DMEM_BIT);
-ASSERT_ERR_BIT_MATCH(kOtbnErrBitsFatalReg, OTBN_ERR_BITS_FATAL_REG_BIT);
-ASSERT_ERR_BIT_MATCH(kOtbnErrBitsFatalIllegalBusAccess,
- OTBN_ERR_BITS_FATAL_ILLEGAL_BUS_ACCESS_BIT);
-ASSERT_ERR_BIT_MATCH(kOtbnErrBitsFatalLifecycleEscalation,
- OTBN_ERR_BITS_FATAL_LIFECYCLE_ESCALATION_BIT);
+ASSERT_ERR_BIT_MATCH(kOtbnErrBitsImemIntgViolation,
+ OTBN_ERR_BITS_IMEM_INTG_VIOLATION_BIT);
+ASSERT_ERR_BIT_MATCH(kOtbnErrBitsDmemIntgViolation,
+ OTBN_ERR_BITS_DMEM_INTG_VIOLATION_BIT);
+ASSERT_ERR_BIT_MATCH(kOtbnErrBitsRegIntgViolation,
+ OTBN_ERR_BITS_REG_INTG_VIOLATION_BIT);
+ASSERT_ERR_BIT_MATCH(kOtbnErrBitsIllegalBusAccess,
+ OTBN_ERR_BITS_ILLEGAL_BUS_ACCESS_BIT);
+ASSERT_ERR_BIT_MATCH(kOtbnErrBitsLifecycleEscalation,
+ OTBN_ERR_BITS_LIFECYCLE_ESCALATION_BIT);
const size_t kOtbnDMemSizeBytes = OTBN_DMEM_SIZE_BYTES;
const size_t kOtbnIMemSizeBytes = OTBN_IMEM_SIZE_BYTES;
diff --git a/sw/device/silicon_creator/lib/drivers/otbn.h b/sw/device/silicon_creator/lib/drivers/otbn.h
index fd1ed27..e5067a4 100644
--- a/sw/device/silicon_creator/lib/drivers/otbn.h
+++ b/sw/device/silicon_creator/lib/drivers/otbn.h
@@ -70,29 +70,26 @@
*/
typedef enum otbn_err_bits {
kOtbnErrBitsNoError = 0,
- /** Load or store to invalid address. */
+ /** A BAD_DATA_ADDR error was observed. */
kOtbnErrBitsBadDataAddr = (1 << 0),
- /** Instruction fetch from invalid address. */
+ /** A BAD_INSN_ADDR error was observed. */
kOtbnErrBitsBadInsnAddr = (1 << 1),
- /** Call stack underflow or overflow. */
+ /** A CALL_STACK error was observed. */
kOtbnErrBitsCallStack = (1 << 2),
- /** Illegal instruction execution attempted */
+ /** An ILLEGAL_INSN error was observed. */
kOtbnErrBitsIllegalInsn = (1 << 3),
- /** LOOP[I] related error */
+ /** A LOOP error was observed. */
kOtbnErrBitsLoop = (1 << 4),
- /** Error seen in Imem read */
- kOtbnErrBitsFatalImem = (1 << 5),
- /** Error seen in Dmem read */
- kOtbnErrBitsFatalDmem = (1 << 6),
- /** Error seen in RF read */
- kOtbnErrBitsFatalReg = (1 << 7),
- /**
- * A bus-accessible register or memory was read or written while when it was
- * not allowed.
- */
- kOtbnErrBitsFatalIllegalBusAccess = (1 << 8),
- /** OTBN received a life cycle escalation request from the system */
- kOtbnErrBitsFatalLifecycleEscalation = (1 << 9),
+ /** A IMEM_INTG_VIOLATION error was observed. */
+ kOtbnErrBitsImemIntgViolation = (1 << 5),
+ /** A DMEM_INTG_VIOLATION error was observed. */
+ kOtbnErrBitsDmemIntgViolation = (1 << 6),
+ /** A REG_INTG_VIOLATION error was observed. */
+ kOtbnErrBitsRegIntgViolation = (1 << 7),
+ /** An ILLEGAL_BUS_ACCESS error was observed. */
+ kOtbnErrBitsIllegalBusAccess = (1 << 8),
+ /** A LIFECYCLE_ESCALATION error was observed. */
+ kOtbnErrBitsLifecycleEscalation = (1 << 9),
} otbn_err_bits_t;
/**
diff --git a/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc b/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc
index 73b2273..fb9adfb 100644
--- a/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc
+++ b/sw/device/silicon_creator/lib/drivers/otbn_unittest.cc
@@ -61,11 +61,11 @@
TEST_F(GetErrBitsTest, Success) {
EXPECT_ABS_READ32(base_ + OTBN_ERR_BITS_REG_OFFSET,
- kOtbnErrBitsIllegalInsn | kOtbnErrBitsFatalReg);
+ kOtbnErrBitsIllegalInsn | kOtbnErrBitsRegIntgViolation);
otbn_err_bits_t err_bits;
otbn_get_err_bits(&err_bits);
- EXPECT_EQ(err_bits, kOtbnErrBitsIllegalInsn | kOtbnErrBitsFatalReg);
+ EXPECT_EQ(err_bits, kOtbnErrBitsIllegalInsn | kOtbnErrBitsRegIntgViolation);
}
class ImemWriteTest : public OtbnTest {};
