| commit | 755ea76e80583f4bb41aa0b02ad2a40a60eaa48f | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Oct 22 15:21:23 2021 +0100 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Wed Nov 03 15:12:35 2021 -0700 |
| tree | c21cadb41bfce4a79c30e19791bd4f85d492c384 | |
| parent | 5a51d3afa553aceb4dad22407a61089833ba55e9 [diff] |
[dv] Massively shorten FOO_csr_mem_rw_with_rand_reset tests These tests are intended to mess around with memory and then suddenly pull the reset line at unexpected times. Since the device is quiescent otherwise, the "time constant" for the sort of state we're trying to hit edge cases in is only a few TL transactions' worth. Since a TL transaction only takes ~10 cycles, there's no real need to delay millions of cycles before injecting the reset. However, we don't also want to shorten the delay to reset for the stress_all_with_rand_reset tests, because that would mean we hardly did any transactions between each reset. So we leave the existing constraint unchanged (except slightly changing the name to make it describe what's going on better), but allow a caller of run_stress_all_with_rand_reset_vseq() to pass an argument called reset_delay_bound. This defaults to a massive number so will have no effect unless provided. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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