[I2C/DV] Host Test Name Change
- Modified Host Testcase Name
- Removed Test host_rw_loopback Not Possible
- Host Test i2c_host_TestName Target Test i2c_target_TestName
Signed-off-by: Viswanadha Bazawada <viswanadha.bazawada@ensilica.com>
diff --git a/hw/ip/i2c/data/i2c_testplan.hjson b/hw/ip/i2c/data/i2c_testplan.hjson
index cf35401..7dff438 100644
--- a/hw/ip/i2c/data/i2c_testplan.hjson
+++ b/hw/ip/i2c/data/i2c_testplan.hjson
@@ -32,7 +32,7 @@
- Read and write transfer matching
'''
milestone: V1
- tests: ["i2c_smoke"]
+ tests: ["i2c_host_smoke"]
}
{
name: host_error_intr
@@ -56,7 +56,7 @@
- Ensure IP operation get back normal after on-the-fly reset finished
'''
milestone: V2
- tests: ["i2c_error_intr"]
+ tests: ["i2c_host_error_intr"]
}
{
name: host_stress_all
@@ -66,7 +66,7 @@
Stimulus:
- Configure DUT/Agent to Host/Target mode respectively
- Combine above sequences in one test to run sequentially
- except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
+ except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
- Randomly add reset between each sequence
Checking:
@@ -74,7 +74,7 @@
- Ensure reset is handled correctly
'''
milestone: V2
- tests: ["i2c_stress_all"]
+ tests: ["i2c_host_stress_all"]
}
{
name: host_stress_all_with_rand_reset
@@ -84,7 +84,7 @@
Stimulus:
- Configure DUT/Agent to Host/Target mode respectively
- Combine above sequences in one test to run sequentially
- except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
+ except csr sequence and i2c_host_rx_oversample_vseq (requires zero_delays)
- Randomly add reset within the sequences then switch to another one
Checking:
@@ -92,7 +92,7 @@
- Ensure reset is handled correctly
'''
milestone: V2
- tests: ["i2c_stress_all_with_rand_reset"]
+ tests: ["i2c_host_stress_all_with_rand_reset"]
}
{
name: host_perf
@@ -110,7 +110,7 @@
- Ensure transactions are transmitted/received correctly
'''
milestone: V2
- tests: ["i2c_perf"]
+ tests: ["i2c_host_perf"]
}
{
name: host_override
@@ -125,7 +125,7 @@
- Ensure scl_o, sda_o are overridden
'''
milestone: V2
- tests: ["i2c_override"]
+ tests: ["i2c_host_override"]
}
{
name: host_fifo_watermark
@@ -143,7 +143,7 @@
- Ensure receving correct number of fmt_fifo and rx_fifo watermark interrupts
'''
milestone: V2
- tests: ["i2c_fifo_watermark"]
+ tests: ["i2c_host_fifo_watermark"]
}
{
name: host_fifo_overflow
@@ -160,7 +160,7 @@
- Ensure fmt_overflow and rx_overflow interrupt are asserted
'''
milestone: V2
- tests: ["i2c_fifo_overflow"]
+ tests: ["i2c_host_fifo_overflow"]
}
{
name: host_fifo_reset
@@ -176,7 +176,7 @@
- Ensure the remaining entries are not show up after fmt_fifo is reset
'''
milestone: V2
- tests: ["i2c_fifo_reset_fmt", "i2c_fifo_reset_rx", "i2c_host_fifo_fmt_empty"]
+ tests: ["i2c_host_fifo_reset_fmt", "i2c_host_fifo_reset_rx", "i2c_host_fifo_fmt_empty"]
}
{
name: host_fifo_full
@@ -192,7 +192,7 @@
- Check fifo full states by reading status register
'''
milestone: V2
- tests: ["i2c_fifo_full"]
+ tests: ["i2c_host_fifo_full"]
}
{
name: host_timeout
@@ -211,7 +211,7 @@
'''
milestone: V2
- tests: ["i2c_timeout"]
+ tests: ["i2c_host_timeout"]
}
{
name: host_rx_oversample
@@ -226,21 +226,7 @@
- Read rx data oversampled value and ensure it is same as driven value
'''
milestone: V2
- tests: ["i2c_rx_oversample"]
- }
- {
- name: host_rw_loopback
- desc: '''
- Host and Target mode: do write data, read loopback, and compare.
-
- Stimulus:
- - Drive DUT/Agent to write data to the Agent/DUT then read loopback
-
- Checking:
- - Ensure read data is matched with write data
- '''
- milestone: V2
- tests: []
+ tests: ["i2c_host_rx_oversample"]
}
//-----------------------------------------------
@@ -266,7 +252,7 @@
- Read and write transfer matching
'''
milestone: V1
- tests: ["i2c_smoke"]
+ tests: [""]
}
{
name: target_error_intr
@@ -282,7 +268,7 @@
- Ensure IP operation get back normal after on-the-fly reset finished
'''
milestone: V2
- tests: ["i2c_error_intr"]
+ tests: [""]
}
{
name: target_stress_all
@@ -299,7 +285,7 @@
- Ensure reset is handled correctly
'''
milestone: V2
- tests: ["i2c_stress_all"]
+ tests: [""]
}
{
name: target_stress_all_with_rand_reset
@@ -309,7 +295,7 @@
Stimulus:
- Configure DUT/Agent to Target/Host mode respectively
- Combine above sequences in one test to run sequentially
- except csr sequence and i2c_rx_oversample_vseq (requires zero_delays)
+ except csr sequence
- Randomly add reset within the sequences then switch to another one
Checking:
@@ -317,7 +303,7 @@
- Ensure reset is handled correctly
'''
milestone: V2
- tests: ["i2c_stress_all_with_rand_reset"]
+ tests: [""]
}
{
name: target_perf
@@ -335,7 +321,7 @@
- Ensure transactions are transmitted/received correctly
'''
milestone: V2
- tests: ["i2c_perf"]
+ tests: [""]
}
{
name: target_fifo_overflow
@@ -352,7 +338,7 @@
- Ensure tx_overflow and acq_overflow interrupt are asserted
'''
milestone: V2
- tests: ["i2c_fifo_overflow"]
+ tests: [""]
}
{
name: target_fifo_empty
@@ -401,7 +387,7 @@
- Check fifo full states by reading status register
'''
milestone: V2
- tests: ["i2c_fifo_full"]
+ tests: [""]
}
{
name: target_timeout
@@ -418,7 +404,7 @@
'''
milestone: V2
- tests: []
+ tests: [""]
}
]
}
diff --git a/hw/ip/i2c/doc/dv/index.md b/hw/ip/i2c/doc/dv/index.md
index ad248f7..5149361 100644
--- a/hw/ip/i2c/doc/dv/index.md
+++ b/hw/ip/i2c/doc/dv/index.md
@@ -94,7 +94,7 @@
Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
Here's how to run a smoke test:
```console
-$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_smoke
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/i2c/dv/i2c_sim_cfg.hjson -i i2c_host_smoke
```
## Testplan
diff --git a/hw/ip/i2c/dv/env/i2c_env.core b/hw/ip/i2c/dv/env/i2c_env.core
index 7f242d2..8c19b1e 100644
--- a/hw/ip/i2c/dv/env/i2c_env.core
+++ b/hw/ip/i2c/dv/env/i2c_env.core
@@ -23,20 +23,20 @@
- seq_lib/i2c_base_vseq.sv: {is_include_file: true}
- seq_lib/i2c_common_vseq.sv: {is_include_file: true}
- seq_lib/i2c_rx_tx_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_smoke_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_override_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_rx_oversample_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_fifo_watermark_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_fifo_overflow_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_fifo_reset_fmt_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_smoke_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_override_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_rx_oversample_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_fifo_watermark_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_fifo_overflow_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_fifo_reset_fmt_vseq.sv: {is_include_file: true}
- seq_lib/i2c_host_fifo_fmt_empty_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_fifo_reset_rx_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_timeout_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_fifo_full_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_perf_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_stretch_timeout_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_error_intr_vseq.sv: {is_include_file: true}
- - seq_lib/i2c_stress_all_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_fifo_reset_rx_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_timeout_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_fifo_full_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_perf_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_stretch_timeout_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_error_intr_vseq.sv: {is_include_file: true}
+ - seq_lib/i2c_host_stress_all_vseq.sv: {is_include_file: true}
file_type: systemVerilogSource
generate:
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_error_intr_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_error_intr_vseq.sv
similarity index 91%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_error_intr_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_error_intr_vseq.sv
index 3dda704..e94f735 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_error_intr_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_error_intr_vseq.sv
@@ -7,8 +7,8 @@
// such as sda_interference, scl_interference, sda_unstable irqs
// - do on-the-fly reset dut and dv if error irqs are asserted
// - continue sending transactions and verify dut works as normal
-class i2c_error_intr_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_error_intr_vseq)
+class i2c_host_error_intr_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_error_intr_vseq)
`uvm_object_new
local bit do_reset = 1'b0;
@@ -27,7 +27,7 @@
endtask : pre_start
virtual task body();
- `uvm_info(`gfn, "\n--> start of i2c_error_intr_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_error_intr_vseq", UVM_DEBUG)
initialization(.mode(Host));
for (int i = 1; i <= num_runs; i++) begin
`uvm_info(`gfn, $sformatf("\n run simulation %0d/%0d", i, num_runs), UVM_DEBUG)
@@ -61,7 +61,7 @@
end
join
end
- `uvm_info(`gfn, "\n--> end of i2c_error_intr_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_error_intr_vseq", UVM_DEBUG)
endtask : body
virtual task process_error_interrupts();
@@ -82,4 +82,4 @@
end
endtask : process_error_interrupts
-endclass : i2c_error_intr_vseq
+endclass : i2c_host_error_intr_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_full_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_full_vseq.sv
similarity index 91%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_fifo_full_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_full_vseq.sv
index 274212a..70e7d19 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_full_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_full_vseq.sv
@@ -3,8 +3,8 @@
// SPDX-License-Identifier: Apache-2.0
// basic fifo_full test vseq
-class i2c_fifo_full_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_fifo_full_vseq)
+class i2c_host_fifo_full_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_fifo_full_vseq)
`uvm_object_new
// fast write data to fmt_fifo to quickly trigger fmt_watermark interrupt
@@ -33,7 +33,7 @@
virtual task body();
initialization(.mode(Host));
- `uvm_info(`gfn, "\n--> start of i2c_fifo_full_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_fifo_full_vseq", UVM_DEBUG)
fork
begin
while (!cfg.under_reset && check_fifo_full) process_fifo_full_status();
@@ -43,7 +43,7 @@
check_fifo_full = 1'b0; // gracefully stop process_fifo_full_status
end
join
- `uvm_info(`gfn, "\n--> end of i2c_fifo_full_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_fifo_full_vseq", UVM_DEBUG)
endtask : body
// TODO: weicai suggested corner tests: send N + 1 items (N is fifo depth), configure agent
@@ -81,4 +81,4 @@
end
endtask : process_fifo_full_status
-endclass : i2c_fifo_full_vseq
+endclass : i2c_host_fifo_full_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_overflow_vseq.sv
similarity index 95%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_overflow_vseq.sv
index dd8b9be..6ff8879 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_overflow_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_overflow_vseq.sv
@@ -3,8 +3,8 @@
// SPDX-License-Identifier: Apache-2.0
// basic fifo_overflow test vseq
-class i2c_fifo_overflow_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_fifo_overflow_vseq)
+class i2c_host_fifo_overflow_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_fifo_overflow_vseq)
`uvm_object_new
// fast write data to fmt_fifo to quickly trigger fmt_watermark interrupt
@@ -40,7 +40,7 @@
bit rxempty = 1'b0;
initialization(.mode(Host));
- `uvm_info(`gfn, "\n--> start of i2c_fifo_overflow_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_fifo_overflow_vseq", UVM_DEBUG)
for (int i = 1; i <= num_trans; i++) begin
check_fmt_overflow = 1'b1; // set to gracefully stop process_fmt_overflow_intr
check_rx_overflow = 1'b1; // set to gracefully stop process_rx_overflow_intr
@@ -118,4 +118,4 @@
end
endtask : process_rx_overflow_intr
-endclass : i2c_fifo_overflow_vseq
+endclass : i2c_host_fifo_overflow_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_reset_fmt_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_reset_fmt_vseq.sv
similarity index 88%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_fifo_reset_fmt_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_reset_fmt_vseq.sv
index e175141..3df6c2b 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_reset_fmt_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_reset_fmt_vseq.sv
@@ -5,8 +5,8 @@
// i2c_fifo_reset_fmt test vseq
// this sequence fills fmt fifo with random bytes and resets fmt fifo.
// checks for fifo empty high
-class i2c_fifo_reset_fmt_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_fifo_reset_fmt_vseq)
+class i2c_host_fifo_reset_fmt_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_fifo_reset_fmt_vseq)
`uvm_object_new
i2c_item fmt_item;
@@ -21,7 +21,7 @@
last_tran = 1'b1;
initialization(.mode(Host));
fmt_item = new("fmt_item");
- `uvm_info(`gfn, "\n--> start of i2c_fifo_reset_fmt_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_fifo_reset_fmt_vseq", UVM_DEBUG)
`uvm_info(`gfn, $sformatf("number of runs is %0d ", num_runs), UVM_HIGH)
for (int i = 1; i <= num_runs; i++) begin
`DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_wr_bytes)
@@ -55,7 +55,7 @@
reset_fmt_fifo();
csr_rd_check(.ptr(ral.status.fmtempty), .compare_value(1));
end // for num runs
- `uvm_info(`gfn, "\n--> end of i2c_fifo_reset_fmt_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_fifo_reset_fmt_vseq", UVM_DEBUG)
endtask : body
-endclass : i2c_fifo_reset_fmt_vseq
+endclass : i2c_host_fifo_reset_fmt_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_reset_rx_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_reset_rx_vseq.sv
similarity index 90%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_fifo_reset_rx_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_reset_rx_vseq.sv
index 06e55fd..027c270 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_reset_rx_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_reset_rx_vseq.sv
@@ -5,8 +5,8 @@
// i2c_fifo_reset_rx test vseq
// this sequence waits for rx fifo full and resets rx fifo.
// checks for fifo empty high and rx lvl is 0
-class i2c_fifo_reset_rx_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_fifo_reset_rx_vseq)
+class i2c_host_fifo_reset_rx_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_fifo_reset_rx_vseq)
`uvm_object_new
// fast write data to fmt_fifo to quickly trigger fmt_watermark interrupt
@@ -37,7 +37,7 @@
virtual task body();
initialization(.mode(Host));
read = 1'b0;
- `uvm_info(`gfn, "\n--> start of i2c_fifo_reset_rx_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_fifo_reset_rx_vseq", UVM_DEBUG)
fork
begin
while (!cfg.under_reset && check_fifo_full) process_fifo_full_status();
@@ -47,7 +47,7 @@
check_fifo_full = 1'b0; // gracefully stop process_fifo_full_status
end
join
- `uvm_info(`gfn, "\n--> end of i2c_fifo_reset_rx_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_fifo_reset_rx_vseq", UVM_DEBUG)
endtask : body
task process_fifo_full_status();
@@ -78,4 +78,4 @@
if (rx_empty) `DV_CHECK_EQ(rx_lvl, 0);
end
endtask : process_fifo_full_status
-endclass : i2c_fifo_reset_rx_vseq
+endclass : i2c_host_fifo_reset_rx_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_watermark_vseq.sv
similarity index 95%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_watermark_vseq.sv
index 9a2076e..567f41f 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_fifo_watermark_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_fifo_watermark_vseq.sv
@@ -5,8 +5,8 @@
// test the watermark interrupt of fmt_fifo and rx_fifo
// TODO: Weicai's comments in PR #3128: consider constraining rx_fifo_access_dly
// to test watermark irq
-class i2c_fifo_watermark_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_fifo_watermark_vseq)
+class i2c_host_fifo_watermark_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_fifo_watermark_vseq)
`uvm_object_new
// fast write data to fmt_fifo to quickly trigger fmt_watermark interrupt
@@ -33,7 +33,7 @@
bit check_fmt_watermark, check_rx_watermark;
initialization(.mode(Host));
- `uvm_info(`gfn, "\n--> start of i2c_fifo_watermark_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_fifo_watermark_vseq", UVM_DEBUG)
for (int i = 1; i <= num_trans; i++) begin
check_fmt_watermark = 1'b1;
check_rx_watermark = 1'b1;
@@ -96,7 +96,7 @@
end
join
end
- `uvm_info(`gfn, "\n--> end of i2c_fifo_watermark_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_fifo_watermark_vseq", UVM_DEBUG)
endtask : body
task process_fmt_watermark_intr();
@@ -151,6 +151,5 @@
clear_interrupt(RxWatermark);
end
endtask : process_rx_watermark_intr
-
-endclass : i2c_fifo_watermark_vseq
+endclass : i2c_host_fifo_watermark_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_override_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_override_vseq.sv
similarity index 86%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_override_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_override_vseq.sv
index 0591d0e..b1fbb54 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_override_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_override_vseq.sv
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-class i2c_override_vseq extends i2c_base_vseq;
- `uvm_object_utils(i2c_override_vseq)
+class i2c_host_override_vseq extends i2c_base_vseq;
+ `uvm_object_utils(i2c_host_override_vseq)
`uvm_object_new
local rand bit sclval;
@@ -23,7 +23,7 @@
task body();
initialization(.mode(Host));
- `uvm_info(`gfn, "\n--> start of i2c_override_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_override_vseq", UVM_DEBUG)
for (uint i = 1; i <= num_trans; i++) begin
`uvm_info(`gfn, $sformatf("\n run simulation %0d/%0d", i, num_trans), UVM_DEBUG)
// program to enable OVRD reg
@@ -48,7 +48,7 @@
end
end
end
- `uvm_info(`gfn, "\n--> end of i2c_override_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_override_vseq", UVM_DEBUG)
endtask : body
-endclass : i2c_override_vseq
+endclass : i2c_host_override_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_perf_vseq.sv
similarity index 91%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_perf_vseq.sv
index aa256c4..5e65ee9 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_perf_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_perf_vseq.sv
@@ -3,8 +3,8 @@
// SPDX-License-Identifier: Apache-2.0
// performance test vseq
-class i2c_perf_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_perf_vseq)
+class i2c_host_perf_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_perf_vseq)
`uvm_object_new
// should have few long transactions
@@ -25,10 +25,10 @@
[9:32] :/ 1
};
}
-
+
// clear interrupt immediately
constraint clear_intr_dly_c { clear_intr_dly == 0; }
-
+
// set latency to zero values for fatest access fmt_fifo and rx_fifo
constraint fmt_fifo_access_dly_c { fmt_fifo_access_dly == 0;}
constraint rx_fifo_access_dly_c { rx_fifo_access_dly == 0;}
@@ -49,4 +49,4 @@
t_buf == 1; // min: (tsu_sta - t_r + 1)
}
-endclass : i2c_perf_vseq
+endclass : i2c_host_perf_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_rx_oversample_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_rx_oversample_vseq.sv
similarity index 93%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_rx_oversample_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_rx_oversample_vseq.sv
index 328fcca..e44815d 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_rx_oversample_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_rx_oversample_vseq.sv
@@ -3,8 +3,8 @@
// SPDX-License-Identifier: Apache-2.0
// basic smoke test vseq
-class i2c_rx_oversample_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_rx_oversample_vseq)
+class i2c_host_rx_oversample_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_rx_oversample_vseq)
`uvm_object_new
constraint num_trans_c {
@@ -61,4 +61,4 @@
end
endtask : body
-endclass : i2c_rx_oversample_vseq
+endclass : i2c_host_rx_oversample_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_smoke_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_smoke_vseq.sv
similarity index 71%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_smoke_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_smoke_vseq.sv
index 562876f..2a9bf84 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_smoke_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_smoke_vseq.sv
@@ -3,11 +3,11 @@
// SPDX-License-Identifier: Apache-2.0
// basic smoke test vseq
-class i2c_smoke_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_smoke_vseq)
+class i2c_host_smoke_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_smoke_vseq)
`uvm_object_new
// increase num_trans to cover all transaction types
constraint num_trans_c { num_trans inside {[50 : 100]}; }
-endclass : i2c_smoke_vseq
+endclass : i2c_host_smoke_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_stress_all_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_stress_all_vseq.sv
similarity index 88%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_stress_all_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_stress_all_vseq.sv
index 29bcd67..6fab63c 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_stress_all_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_stress_all_vseq.sv
@@ -8,8 +8,8 @@
// 3. i2c_error_intr_vseq can issue internal reset
// so it is excluded/included w.r.t stress_all_with_rand_reset/stress_all test
-class i2c_stress_all_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_stress_all_vseq)
+class i2c_host_stress_all_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_stress_all_vseq)
`uvm_object_new
@@ -18,12 +18,12 @@
string seq_names[$] = {
"i2c_common_vseq", // for intr_test
- "i2c_smoke_vseq",
- "i2c_fifo_full_vseq",
- "i2c_fifo_overflow_vseq",
- "i2c_fifo_watermark_vseq",
- "i2c_stretch_timeout_vseq",
- "i2c_perf_vseq"
+ "i2c_host_smoke_vseq",
+ "i2c_host_fifo_full_vseq",
+ "i2c_host_fifo_overflow_vseq",
+ "i2c_host_fifo_watermark_vseq",
+ "i2c_host_stretch_timeout_vseq",
+ "i2c_host_perf_vseq"
};
virtual task pre_start();
@@ -37,7 +37,7 @@
endtask : pre_start
virtual task body();
- `uvm_info(`gfn, "\n\n=> start i2c_stress_all_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n\n=> start i2c_host_stress_all_vseq", UVM_DEBUG)
print_seq_names(seq_names);
initialization(.mode(Host));
for (int i = 1; i <= seq_names.size(); i++) begin
@@ -91,7 +91,7 @@
wait(cfg.m_i2c_agent_cfg.vif.rst_ni);
end
wait_host_for_idle();
- `uvm_info(`gfn, "\n=> end of i2c_stress_all_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n=> end of i2c_host_stress_all_vseq", UVM_DEBUG)
// get the histogram of vseq running
str = {str, "\n\n=> vseq run histogram:"};
@@ -112,4 +112,4 @@
`uvm_info(`gfn, $sformatf("%s", str), UVM_DEBUG)
endfunction : print_seq_names
-endclass : i2c_stress_all_vseq
+endclass : i2c_host_stress_all_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_stretch_timeout_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_stretch_timeout_vseq.sv
similarity index 89%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_stretch_timeout_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_stretch_timeout_vseq.sv
index dbdb947..1638f76 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_stretch_timeout_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_stretch_timeout_vseq.sv
@@ -3,8 +3,8 @@
// SPDX-License-Identifier: Apache-2.0
// basic stretch_timeout test vseq
-class i2c_stretch_timeout_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_stretch_timeout_vseq)
+class i2c_host_stretch_timeout_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_stretch_timeout_vseq)
`uvm_object_new
// set timeout field to minimum value to ensure
@@ -20,7 +20,7 @@
local bit check_rd_stretch;
virtual task body();
- `uvm_info(`gfn, "\n--> start of i2c_stretch_timeout_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> start of i2c_host_stretch_timeout_vseq", UVM_DEBUG)
initialization(.mode(Host));
for (int i = 1; i <= num_trans; i++) begin
cnt_wr_stretch = 0;
@@ -56,7 +56,7 @@
end
join
end
- `uvm_info(`gfn, "\n--> end of i2c_stretch_timeout_vseq", UVM_DEBUG)
+ `uvm_info(`gfn, "\n--> end of i2c_host_stretch_timeout_vseq", UVM_DEBUG)
endtask : body
task process_stretch_timeout_intr();
@@ -77,4 +77,4 @@
end
endtask : process_stretch_timeout_intr
-endclass : i2c_stretch_timeout_vseq
+endclass : i2c_host_stretch_timeout_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_timeout_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_host_timeout_vseq.sv
similarity index 84%
rename from hw/ip/i2c/dv/env/seq_lib/i2c_timeout_vseq.sv
rename to hw/ip/i2c/dv/env/seq_lib/i2c_host_timeout_vseq.sv
index a0c0c4e..7a4cd30 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_timeout_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_host_timeout_vseq.sv
@@ -7,8 +7,8 @@
// runs random i2c transactions agent is configured to pull down clock
// host will trigger an interrupt stretch timeout when count exceeds the programmed
// value in timeout control reg
-class i2c_timeout_vseq extends i2c_rx_tx_vseq;
- `uvm_object_utils(i2c_timeout_vseq)
+class i2c_host_timeout_vseq extends i2c_rx_tx_vseq;
+ `uvm_object_utils(i2c_host_timeout_vseq)
`uvm_object_new
// increase num_trans to cover all transaction types
@@ -18,4 +18,4 @@
constraint t_timeout_c { t_timeout == cfg.seq_cfg.i2c_max_timing; }
constraint e_timeout_c { e_timeout == 1'b1; }
-endclass : i2c_timeout_vseq
+endclass : i2c_host_timeout_vseq
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_vseq_list.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_vseq_list.sv
index 9866f8d..2defb44 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_vseq_list.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_vseq_list.sv
@@ -5,18 +5,18 @@
`include "i2c_base_vseq.sv"
`include "i2c_common_vseq.sv"
`include "i2c_rx_tx_vseq.sv"
-`include "i2c_smoke_vseq.sv"
+`include "i2c_host_smoke_vseq.sv"
-`include "i2c_override_vseq.sv"
-`include "i2c_fifo_watermark_vseq.sv"
-`include "i2c_fifo_overflow_vseq.sv"
-`include "i2c_fifo_reset_fmt_vseq.sv"
+`include "i2c_host_override_vseq.sv"
+`include "i2c_host_fifo_watermark_vseq.sv"
+`include "i2c_host_fifo_overflow_vseq.sv"
+`include "i2c_host_fifo_reset_fmt_vseq.sv"
`include "i2c_host_fifo_fmt_empty_vseq.sv"
-`include "i2c_fifo_reset_rx_vseq.sv"
-`include "i2c_timeout_vseq.sv"
-`include "i2c_rx_oversample_vseq.sv"
-`include "i2c_fifo_full_vseq.sv"
-`include "i2c_perf_vseq.sv"
-`include "i2c_stretch_timeout_vseq.sv"
-`include "i2c_error_intr_vseq.sv"
-`include "i2c_stress_all_vseq.sv"
+`include "i2c_host_fifo_reset_rx_vseq.sv"
+`include "i2c_host_timeout_vseq.sv"
+`include "i2c_host_rx_oversample_vseq.sv"
+`include "i2c_host_fifo_full_vseq.sv"
+`include "i2c_host_perf_vseq.sv"
+`include "i2c_host_stretch_timeout_vseq.sv"
+`include "i2c_host_error_intr_vseq.sv"
+`include "i2c_host_stress_all_vseq.sv"
diff --git a/hw/ip/i2c/dv/i2c_sim_cfg.hjson b/hw/ip/i2c/dv/i2c_sim_cfg.hjson
index 1ef93d1..3b47e21 100644
--- a/hw/ip/i2c/dv/i2c_sim_cfg.hjson
+++ b/hw/ip/i2c/dv/i2c_sim_cfg.hjson
@@ -46,35 +46,35 @@
// List of test specifications.
tests: [
{
- name: i2c_smoke
- uvm_test_seq: i2c_smoke_vseq
+ name: i2c_host_smoke
+ uvm_test_seq: i2c_host_smoke_vseq
}
{
- name: i2c_override
- uvm_test_seq: i2c_override_vseq
+ name: i2c_host_override
+ uvm_test_seq: i2c_host_override_vseq
run_opts: ["+en_scb=0"]
}
{
- name: i2c_rx_oversample
- uvm_test_seq: i2c_rx_oversample_vseq
+ name: i2c_host_rx_oversample
+ uvm_test_seq: i2c_host_rx_oversample_vseq
run_opts: ["+test_timeout_ns=10_000_000"]
}
{
- name: i2c_fifo_watermark
- uvm_test_seq: i2c_fifo_watermark_vseq
+ name: i2c_host_fifo_watermark
+ uvm_test_seq: i2c_host_fifo_watermark_vseq
}
{
- name: i2c_fifo_overflow
- uvm_test_seq: i2c_fifo_overflow_vseq
+ name: i2c_host_fifo_overflow
+ uvm_test_seq: i2c_host_fifo_overflow_vseq
}
{
- name: i2c_fifo_reset_fmt
- uvm_test_seq: i2c_fifo_reset_fmt_vseq
+ name: i2c_host_fifo_reset_fmt
+ uvm_test_seq: i2c_host_fifo_reset_fmt_vseq
run_opts: ["+test_timeout_ns=10_000_000"]
}
@@ -85,34 +85,39 @@
}
{
- name: i2c_fifo_reset_rx
- uvm_test_seq: i2c_fifo_reset_rx_vseq
+ name: i2c_host_fifo_reset_rx
+ uvm_test_seq: i2c_host_fifo_reset_rx_vseq
run_opts: ["+test_timeout_ns=10_000_000"]
}
{
- name: i2c_timeout
- uvm_test_seq: i2c_timeout_vseq
+ name: i2c_host_timeout
+ uvm_test_seq: i2c_host_timeout_vseq
}
{
- name: i2c_fifo_full
- uvm_test_seq: i2c_fifo_full_vseq
+ name: i2c_host_fifo_full
+ uvm_test_seq: i2c_host_fifo_full_vseq
}
{
- name: i2c_perf
- uvm_test_seq: i2c_perf_vseq
+ name: i2c_host_perf
+ uvm_test_seq: i2c_host_perf_vseq
}
{
- name: i2c_stretch_timeout
- uvm_test_seq: i2c_stretch_timeout_vseq
+ name: i2c_host_stretch_timeout
+ uvm_test_seq: i2c_host_stretch_timeout_vseq
}
{
- name: i2c_error_intr
- uvm_test_seq: i2c_error_intr_vseq
+ name: i2c_host_error_intr
+ uvm_test_seq: i2c_host_error_intr_vseq
+ }
+
+ {
+ name: i2c_host_stress_all
+ uvm_test_seq: i2c_host_stress_all_vseq
}
]
@@ -120,7 +125,7 @@
regressions: [
{
name: smoke
- tests: ["i2c_smoke"]
+ tests: ["i2c_host_smoke"]
}
]
}
