[topgen] Rework pinmux datastructure and templatize tops
This is a complete overhaul of the pinmux / padctrl configuration
datastructure in the top Hjson.
The new datastructures are used to provide more control over the
DIO/MIO configuration, pinout and target-specific differences
(ASIC vs FPGA vs Verilator).
The chip-level files are now generated from one common template,
and all regular DIO/MIO connections are made automatically.
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 57bcb35..b83dc34 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -450,31 +450,250 @@
*/
parameter int unsigned TOP_EARLGREY_EFLASH_SIZE_BYTES = 32'h100000;
- // Enumeration for DIO pins.
+
+ // Enumeration of IO power domains.
+ // Only used in ASIC target.
typedef enum {
- TopEarlgreyDioPinUsbdevDn = 0,
- TopEarlgreyDioPinUsbdevDp = 1,
- TopEarlgreyDioPinUsbdevD = 2,
- TopEarlgreyDioPinUsbdevSuspend = 3,
- TopEarlgreyDioPinUsbdevTxModeSe = 4,
- TopEarlgreyDioPinUsbdevDnPullup = 5,
- TopEarlgreyDioPinUsbdevDpPullup = 6,
- TopEarlgreyDioPinUsbdevSe0 = 7,
- TopEarlgreyDioPinUsbdevSense = 8,
- TopEarlgreyDioPinSpiHost0Sd0 = 9,
- TopEarlgreyDioPinSpiHost0Sd1 = 10,
- TopEarlgreyDioPinSpiHost0Sd2 = 11,
- TopEarlgreyDioPinSpiHost0Sd3 = 12,
- TopEarlgreyDioPinSpiHost0Csb = 13,
- TopEarlgreyDioPinSpiHost0Sck = 14,
- TopEarlgreyDioPinSpiDeviceSd0 = 15,
- TopEarlgreyDioPinSpiDeviceSd1 = 16,
- TopEarlgreyDioPinSpiDeviceSd2 = 17,
- TopEarlgreyDioPinSpiDeviceSd3 = 18,
- TopEarlgreyDioPinSpiDeviceCsb = 19,
- TopEarlgreyDioPinSpiDeviceSck = 20,
- TopEarlgreyDioPinCount = 21
- } top_earlgrey_dio_pin_e;
+ IoBankVcc = 0,
+ IoBankAvcc = 1,
+ IoBankVioa = 2,
+ IoBankViob = 3,
+ IoBankCount = 4
+ } pwr_dom_e;
+
+ // Enumeration for MIO signals on the top-level.
+ typedef enum {
+ MioInGpioGpio0 = 0,
+ MioInGpioGpio1 = 1,
+ MioInGpioGpio2 = 2,
+ MioInGpioGpio3 = 3,
+ MioInGpioGpio4 = 4,
+ MioInGpioGpio5 = 5,
+ MioInGpioGpio6 = 6,
+ MioInGpioGpio7 = 7,
+ MioInGpioGpio8 = 8,
+ MioInGpioGpio9 = 9,
+ MioInGpioGpio10 = 10,
+ MioInGpioGpio11 = 11,
+ MioInGpioGpio12 = 12,
+ MioInGpioGpio13 = 13,
+ MioInGpioGpio14 = 14,
+ MioInGpioGpio15 = 15,
+ MioInGpioGpio16 = 16,
+ MioInGpioGpio17 = 17,
+ MioInGpioGpio18 = 18,
+ MioInGpioGpio19 = 19,
+ MioInGpioGpio20 = 20,
+ MioInGpioGpio21 = 21,
+ MioInGpioGpio22 = 22,
+ MioInGpioGpio23 = 23,
+ MioInGpioGpio24 = 24,
+ MioInGpioGpio25 = 25,
+ MioInGpioGpio26 = 26,
+ MioInGpioGpio27 = 27,
+ MioInGpioGpio28 = 28,
+ MioInGpioGpio29 = 29,
+ MioInGpioGpio30 = 30,
+ MioInGpioGpio31 = 31,
+ MioInI2c0Sda = 32,
+ MioInI2c0Scl = 33,
+ MioInI2c1Sda = 34,
+ MioInI2c1Scl = 35,
+ MioInI2c2Sda = 36,
+ MioInI2c2Scl = 37,
+ MioInSpiHost1Sd0 = 38,
+ MioInSpiHost1Sd1 = 39,
+ MioInSpiHost1Sd2 = 40,
+ MioInSpiHost1Sd3 = 41,
+ MioInUart0Rx = 42,
+ MioInUart1Rx = 43,
+ MioInUart2Rx = 44,
+ MioInUart3Rx = 45,
+ MioInFlashCtrlTck = 46,
+ MioInFlashCtrlTms = 47,
+ MioInFlashCtrlTdi = 48,
+ MioInSensorCtrlAonAstDebugIn0 = 49,
+ MioInSensorCtrlAonAstDebugIn1 = 50,
+ MioInSensorCtrlAonAstDebugIn2 = 51,
+ MioInSensorCtrlAonAstDebugIn3 = 52,
+ MioInSensorCtrlAonAstDebugIn4 = 53,
+ MioInSensorCtrlAonAstDebugIn5 = 54,
+ MioInSensorCtrlAonAstDebugIn6 = 55,
+ MioInSensorCtrlAonAstDebugIn7 = 56,
+ MioInSensorCtrlAonAstDebugIn8 = 57,
+ MioInSensorCtrlAonAstDebugIn9 = 58,
+ MioInCount = 59
+ } mio_in_e;
+
+ typedef enum {
+ MioOutGpioGpio0 = 0,
+ MioOutGpioGpio1 = 1,
+ MioOutGpioGpio2 = 2,
+ MioOutGpioGpio3 = 3,
+ MioOutGpioGpio4 = 4,
+ MioOutGpioGpio5 = 5,
+ MioOutGpioGpio6 = 6,
+ MioOutGpioGpio7 = 7,
+ MioOutGpioGpio8 = 8,
+ MioOutGpioGpio9 = 9,
+ MioOutGpioGpio10 = 10,
+ MioOutGpioGpio11 = 11,
+ MioOutGpioGpio12 = 12,
+ MioOutGpioGpio13 = 13,
+ MioOutGpioGpio14 = 14,
+ MioOutGpioGpio15 = 15,
+ MioOutGpioGpio16 = 16,
+ MioOutGpioGpio17 = 17,
+ MioOutGpioGpio18 = 18,
+ MioOutGpioGpio19 = 19,
+ MioOutGpioGpio20 = 20,
+ MioOutGpioGpio21 = 21,
+ MioOutGpioGpio22 = 22,
+ MioOutGpioGpio23 = 23,
+ MioOutGpioGpio24 = 24,
+ MioOutGpioGpio25 = 25,
+ MioOutGpioGpio26 = 26,
+ MioOutGpioGpio27 = 27,
+ MioOutGpioGpio28 = 28,
+ MioOutGpioGpio29 = 29,
+ MioOutGpioGpio30 = 30,
+ MioOutGpioGpio31 = 31,
+ MioOutI2c0Sda = 32,
+ MioOutI2c0Scl = 33,
+ MioOutI2c1Sda = 34,
+ MioOutI2c1Scl = 35,
+ MioOutI2c2Sda = 36,
+ MioOutI2c2Scl = 37,
+ MioOutSpiHost1Sd0 = 38,
+ MioOutSpiHost1Sd1 = 39,
+ MioOutSpiHost1Sd2 = 40,
+ MioOutSpiHost1Sd3 = 41,
+ MioOutUart0Tx = 42,
+ MioOutUart1Tx = 43,
+ MioOutUart2Tx = 44,
+ MioOutUart3Tx = 45,
+ MioOutPattgenPda0Tx = 46,
+ MioOutPattgenPcl0Tx = 47,
+ MioOutPattgenPda1Tx = 48,
+ MioOutPattgenPcl1Tx = 49,
+ MioOutSpiHost1Sck = 50,
+ MioOutSpiHost1Csb = 51,
+ MioOutFlashCtrlTdo = 52,
+ MioOutSensorCtrlAonAstDebugOut0 = 53,
+ MioOutSensorCtrlAonAstDebugOut1 = 54,
+ MioOutSensorCtrlAonAstDebugOut2 = 55,
+ MioOutSensorCtrlAonAstDebugOut3 = 56,
+ MioOutSensorCtrlAonAstDebugOut4 = 57,
+ MioOutSensorCtrlAonAstDebugOut5 = 58,
+ MioOutSensorCtrlAonAstDebugOut6 = 59,
+ MioOutSensorCtrlAonAstDebugOut7 = 60,
+ MioOutSensorCtrlAonAstDebugOut8 = 61,
+ MioOutSensorCtrlAonAstDebugOut9 = 62,
+ MioOutCount = 63
+ } mio_out_e;
+
+ // Enumeration for DIO signals, used on both the top and chip-levels.
+ typedef enum {
+ DioSpiHost0Sd0 = 0,
+ DioSpiHost0Sd1 = 1,
+ DioSpiHost0Sd2 = 2,
+ DioSpiHost0Sd3 = 3,
+ DioSpiDeviceSd0 = 4,
+ DioSpiDeviceSd1 = 5,
+ DioSpiDeviceSd2 = 6,
+ DioSpiDeviceSd3 = 7,
+ DioUsbdevD = 8,
+ DioUsbdevDp = 9,
+ DioUsbdevDn = 10,
+ DioSpiDeviceSck = 11,
+ DioSpiDeviceCsb = 12,
+ DioUsbdevSense = 13,
+ DioSpiHost0Sck = 14,
+ DioSpiHost0Csb = 15,
+ DioUsbdevSe0 = 16,
+ DioUsbdevDpPullup = 17,
+ DioUsbdevDnPullup = 18,
+ DioUsbdevTxModeSe = 19,
+ DioUsbdevSuspend = 20,
+ DioCount = 21
+ } dio_e;
+
+ // Raw MIO/DIO input array indices on chip-level.
+ // TODO: Does not account for target specific stubbed/added pads.
+ // Need to make a target-specific package for those.
+ typedef enum {
+ MioPadIoa0 = 0,
+ MioPadIoa1 = 1,
+ MioPadIoa2 = 2,
+ MioPadIoa3 = 3,
+ MioPadIoa4 = 4,
+ MioPadIoa5 = 5,
+ MioPadIob0 = 6,
+ MioPadIob1 = 7,
+ MioPadIob2 = 8,
+ MioPadIob3 = 9,
+ MioPadIob4 = 10,
+ MioPadIob5 = 11,
+ MioPadIob6 = 12,
+ MioPadIob7 = 13,
+ MioPadIob8 = 14,
+ MioPadIob9 = 15,
+ MioPadIob10 = 16,
+ MioPadIob11 = 17,
+ MioPadIoc0 = 18,
+ MioPadIoc1 = 19,
+ MioPadIoc2 = 20,
+ MioPadIoc3 = 21,
+ MioPadIoc4 = 22,
+ MioPadIoc5 = 23,
+ MioPadIoc6 = 24,
+ MioPadIoc7 = 25,
+ MioPadIoc8 = 26,
+ MioPadIoc9 = 27,
+ MioPadIoc10 = 28,
+ MioPadIoc11 = 29,
+ MioPadIor0 = 30,
+ MioPadIor1 = 31,
+ MioPadIor2 = 32,
+ MioPadIor3 = 33,
+ MioPadIor4 = 34,
+ MioPadIor5 = 35,
+ MioPadIor6 = 36,
+ MioPadIor7 = 37,
+ MioPadIor8 = 38,
+ MioPadIor9 = 39,
+ MioPadIor10 = 40,
+ MioPadIor11 = 41,
+ MioPadIor12 = 42,
+ MioPadIor13 = 43,
+ MioPadCount
+ } mio_pad_e;
+
+ typedef enum {
+ DioPadPorN = 0,
+ DioPadSpiHostD0 = 1,
+ DioPadSpiHostD1 = 2,
+ DioPadSpiHostD2 = 3,
+ DioPadSpiHostD3 = 4,
+ DioPadSpiHostClk = 5,
+ DioPadSpiHostCsL = 6,
+ DioPadSpiDevD0 = 7,
+ DioPadSpiDevD1 = 8,
+ DioPadSpiDevD2 = 9,
+ DioPadSpiDevD3 = 10,
+ DioPadSpiDevClk = 11,
+ DioPadSpiDevCsL = 12,
+ DioPadUsbP = 13,
+ DioPadUsbN = 14,
+ DioPadCc1 = 15,
+ DioPadCc2 = 16,
+ DioPadFlashTestMode0 = 17,
+ DioPadFlashTestMode1 = 18,
+ DioPadFlashTestMode2 = 19,
+ DioPadFlashTestMode3 = 20,
+ DioPadFlashTestVolt = 21,
+ DioPadCount
+ } dio_pad_e;
// TODO: Enumeration for PLIC Interrupt source peripheral.
// TODO: Enumeration for PLIC Interrupt Ids.
