[topgen] Rework pinmux datastructure and templatize tops
This is a complete overhaul of the pinmux / padctrl configuration
datastructure in the top Hjson.
The new datastructures are used to provide more control over the
DIO/MIO configuration, pinout and target-specific differences
(ASIC vs FPGA vs Verilator).
The chip-level files are now generated from one common template,
and all regular DIO/MIO connections are made automatically.
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/pinmux/data/pinmux.hjson b/hw/ip/pinmux/data/pinmux.hjson
index 9261175..54709c5 100644
--- a/hw/ip/pinmux/data/pinmux.hjson
+++ b/hw/ip/pinmux/data/pinmux.hjson
@@ -179,42 +179,6 @@
default: "8",
local: "true"
},
- { name: "NUsbDevPads",
- desc: "Number of usbdev pins",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "NDioPadUsbDevStart",
- desc: "Start position for usbdev pins",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "UsbDpSel",
- desc: "index of usbdev_dp",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "UsbDnSel",
- desc: "index of usbdev_dn",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "UsbDpPullUpSel",
- desc: "index of usbdev_dp_pullup",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "UsbDnPullUpSel",
- desc: "index of usbdev_dn_pullup",
- type: "int",
- default: "0",
- local: "true"
- },
// Since the target-specific top-levels often have slightly
// different debug signal positions, we need a way to pass
// this info from the target specific top-level into the pinmux
diff --git a/hw/ip/pinmux/data/pinmux.hjson.tpl b/hw/ip/pinmux/data/pinmux.hjson.tpl
index 66e72d5..13e6344 100644
--- a/hw/ip/pinmux/data/pinmux.hjson.tpl
+++ b/hw/ip/pinmux/data/pinmux.hjson.tpl
@@ -191,42 +191,6 @@
default: "${wkup_cnt_width}",
local: "true"
},
- { name: "NUsbDevPads",
- desc: "Number of usbdev pins",
- type: "int",
- default: "${n_usb_pins}",
- local: "true"
- },
- { name: "NDioPadUsbDevStart",
- desc: "Start position for usbdev pins",
- type: "int",
- default: "${usb_start_pos}",
- local: "true"
- },
- { name: "UsbDpSel",
- desc: "index of usbdev_dp",
- type: "int",
- default: "${usb_dp_sel}",
- local: "true"
- },
- { name: "UsbDnSel",
- desc: "index of usbdev_dn",
- type: "int",
- default: "${usb_dn_sel}",
- local: "true"
- },
- { name: "UsbDpPullUpSel",
- desc: "index of usbdev_dp_pullup",
- type: "int",
- default: "${usb_dp_pull_sel}",
- local: "true"
- },
- { name: "UsbDnPullUpSel",
- desc: "index of usbdev_dn_pullup",
- type: "int",
- default: "${usb_dn_pull_sel}",
- local: "true"
- },
// Since the target-specific top-levels often have slightly
// different debug signal positions, we need a way to pass
// this info from the target specific top-level into the pinmux
diff --git a/hw/ip/pinmux/pinmux_component.core b/hw/ip/pinmux/pinmux_component.core
index 1ae1898..45679c2 100644
--- a/hw/ip/pinmux/pinmux_component.core
+++ b/hw/ip/pinmux/pinmux_component.core
@@ -12,7 +12,9 @@
- lowrisc:prim:all
- lowrisc:prim:clock_buf
- lowrisc:prim:buf
+ - lowrisc:prim:lc_dec
- lowrisc:prim:lc_sync
+ - lowrisc:prim:pad_wrapper_pkg
- lowrisc:ip:jtag_pkg
- lowrisc:ip:usbdev
# pinmux_wkup.sv depends on pinmux_reg_pkg.sv
diff --git a/hw/ip/pinmux/rtl/padring.sv b/hw/ip/pinmux/rtl/padring.sv
index 6ca2b29..5b6dfd1 100644
--- a/hw/ip/pinmux/rtl/padring.sv
+++ b/hw/ip/pinmux/rtl/padring.sv
@@ -9,265 +9,103 @@
`include "prim_assert.sv"
-module padring import pinmux_reg_pkg::*; #(
- // This allows to selectively connect Pad instances.
- // unconnected inputs are tied to 0, unconnected outputs are high-z.
- parameter bit ConnectClk = 1,
- parameter bit ConnectRst = 1,
- parameter bit [1:0] ConnectCc = '1,
- parameter bit [NMioPads-1:0] ConnectMioIn = '1,
- parameter bit [NMioPads-1:0] ConnectMioOut = '1,
- parameter bit [NDioPads-1:0] ConnectDioIn = '1,
- parameter bit [NDioPads-1:0] ConnectDioOut = '1,
-
- // 0: bidir, 1: input, 2: tolerant, 3: open drain
- parameter bit [NMioPads-1:0][1:0] MioPadVariant = '0,
- parameter bit [NDioPads-1:0][1:0] DioPadVariant = '0
+module padring
+ import prim_pad_wrapper_pkg::*;
+#(
+ parameter int NDioPads = 1,
+ parameter int NMioPads = 1,
+ parameter bit PhysicalPads = 0, // Only used for ASIC target
+ parameter int NIoBanks = 4,
+ parameter logic [NDioPads-1:0][$clog2(NIoBanks)-1:0] DioPadBank = '0,
+ parameter logic [NMioPads-1:0][$clog2(NIoBanks)-1:0] MioPadBank = '0,
+ parameter pad_type_e [NDioPads-1:0] DioPadType = {NDioPads{BidirStd}},
+ parameter pad_type_e [NMioPads-1:0] MioPadType = {NMioPads{BidirStd}},
+ parameter scan_role_e [NDioPads-1:0] DioScanRole = {NDioPads{NoScan}},
+ parameter scan_role_e [NMioPads-1:0] MioScanRole = {NMioPads{NoScan}}
) (
- // pad input
- input wire clk_pad_i,
- input wire rst_pad_ni,
- // to clocking/reset infrastructure
- output logic clk_o,
- output logic rst_no,
- // pads for dcd.
- input wire cc1_i,
- input wire cc2_i,
- // pads
- inout wire [NMioPads-1:0] mio_pad_io,
- inout wire [NDioPads-1:0] dio_pad_io,
- // muxed IO signals coming from pinmux
- output logic [NMioPads-1:0] mio_in_o,
- input [NMioPads-1:0] mio_out_i,
- input [NMioPads-1:0] mio_oe_i,
- // dedicated IO signals coming from peripherals
- output logic [NDioPads-1:0] dio_in_o,
- input [NDioPads-1:0] dio_out_i,
- input [NDioPads-1:0] dio_oe_i,
- // pad attributes from top level instance
- input [NMioPads-1:0][AttrDw-1:0] mio_attr_i,
- input [NDioPads-1:0][AttrDw-1:0] dio_attr_i
+ // This is only used for scan
+ input clk_scan_i,
+ lc_ctrl_pkg::lc_tx_t scanmode_i,
+ // RAW outputs used for DFT and infrastructure
+ // purposes (e.g. external muxed clock)
+ output logic [NDioPads-1:0] dio_in_raw_o,
+ output logic [NMioPads-1:0] mio_in_raw_o,
+ // Pad wires
+ inout wire [NDioPads-1:0] dio_pad_io,
+ inout wire [NMioPads-1:0] mio_pad_io,
+ // Dedicated IO signals coming from peripherals
+ output logic [NDioPads-1:0] dio_in_o,
+ input [NDioPads-1:0] dio_out_i,
+ input [NDioPads-1:0] dio_oe_i,
+ // Muxed IO signals coming from pinmux
+ output logic [NMioPads-1:0] mio_in_o,
+ input [NMioPads-1:0] mio_out_i,
+ input [NMioPads-1:0] mio_oe_i,
+ // Pad attributes from top level instance
+ input pad_attr_t [NDioPads-1:0] dio_attr_i,
+ input pad_attr_t [NMioPads-1:0] mio_attr_i
);
- /////////////////////////
- // Clock / Reset Infra //
- /////////////////////////
+ pad_pok_t [NIoBanks-1:0] pad_pok;
- // use this intermediate assignment to make both lint and fpv happy.
- // the clock/reset wires should be input-only, otherwise fpv
- // has trouble defining/tracing the clock signal. on the other hand, a direct
- // connection of input wire to an inout pad causes lint problems
- // (even though oe is hardwired to 0).
- wire clk, rst_n;
- assign clk = clk_pad_i;
- assign rst_n = rst_pad_ni;
-
- if (ConnectClk) begin : gen_clk_pad
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_clk_pad (
- .inout_io ( clk ),
- .in_o ( clk_o ),
- .ie_i ( 1'b1 ),
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
- end else begin : gen_no_clk_pad
- logic unused_clk;
- assign unused_clk = clk;
- assign clk_o = 1'b0;
- end
-
- if (ConnectRst) begin : gen_rst_pad
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_rst_pad (
- .inout_io ( rst_n ),
- .in_o ( rst_no ),
- .ie_i ( 1'b1 ),
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
- end else begin : gen_no_rst_pad
- logic unused_rst;
- assign unused_rst = rst_n;
- assign rst_no = 1'b0;
- end
-
- //////////////////
- // Pads for DCD //
- //////////////////
-
- // Note that analog connections to these pads are made in physical design.
- // None of the digital signals are used here.
- wire cc1, cc2;
- assign cc1 = cc1_i;
- assign cc2 = cc2_i;
-
- if (ConnectCc[0]) begin : gen_cc1_pad
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_cc1_pad (
- .inout_io ( cc1 ),
- .in_o ( ),
- .ie_i ( 1'b0 ), // input buffer disabled
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
- end else begin : gen_no_cc1_pad
- logic unused_cc1;
- assign unused_cc1 = cc1;
- end
-
- if (ConnectCc[1]) begin : gen_cc2_pad
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( 1 ) // input-only
- ) u_cc2_pad (
- .inout_io ( cc2 ),
- .in_o ( ),
- .ie_i ( 1'b0 ), // input buffer disabled
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( '0 ),
- .warl_o ( )
- );
- end else begin : gen_no_cc2_pad
- logic unused_cc2;
- assign unused_cc2 = cc2;
- end
-
- //////////////
- // MIO Pads //
- //////////////
-
- for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_pads
- if (ConnectMioIn[k] && ConnectMioOut[k]) begin : gen_mio_inout
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( MioPadVariant[k] )
- ) u_mio_pad (
- .inout_io ( mio_pad_io[k] ),
- .in_o ( mio_in_o[k] ),
- .ie_i ( 1'b1 ),
- .out_i ( mio_out_i[k] ),
- .oe_i ( mio_oe_i[k] ),
- .attr_i ( mio_attr_i[k] ),
- .warl_o ( )
- );
- end else if (ConnectMioOut[k]) begin : gen_mio_output
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( MioPadVariant[k] )
- ) u_mio_pad (
- .inout_io ( mio_pad_io[k] ),
- .in_o ( ),
- .ie_i ( 1'b0 ),
- .out_i ( mio_out_i[k] ),
- .oe_i ( mio_oe_i[k] ),
- .attr_i ( mio_attr_i[k] ),
- .warl_o ( )
- );
-
- assign mio_in_o[k] = 1'b0;
- end else if (ConnectMioIn[k]) begin : gen_mio_input
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( MioPadVariant[k] )
- ) u_mio_pad (
- .inout_io ( mio_pad_io[k] ),
- .in_o ( mio_in_o[k] ),
- .ie_i ( 1'b1 ),
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( mio_attr_i[k] ),
- .warl_o ( )
- );
-
- logic unused_out, unused_oe;
- assign unused_out = mio_out_i[k];
- assign unused_oe = mio_oe_i[k];
- end else begin : gen_mio_tie_off
- logic unused_out, unused_oe, unused_pad;
- logic [AttrDw-1:0] unused_attr;
- assign mio_pad_io[k] = 1'b0;
- assign unused_pad = mio_pad_io[k];
- assign unused_out = mio_out_i[k];
- assign unused_oe = mio_oe_i[k];
- assign unused_attr = mio_attr_i[k];
- assign mio_in_o[k] = 1'b0;
- end
- end
-
- //////////////
- // DIO Pads //
- //////////////
+ logic scanmode;
+ prim_lc_dec u_prim_lc_dec (
+ .lc_en_i ( scanmode_i ),
+ .lc_en_dec_o ( scanmode )
+ );
for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_pads
- if (ConnectDioIn[k] && ConnectDioOut[k]) begin : gen_dio_inout
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( DioPadVariant[k] )
- ) u_dio_pad (
- .inout_io ( dio_pad_io[k] ),
- .in_o ( dio_in_o[k] ),
- .ie_i ( 1'b1 ),
- .out_i ( dio_out_i[k] ),
- .oe_i ( dio_oe_i[k] ),
- .attr_i ( dio_attr_i[k] ),
- .warl_o ( )
- );
- end else if (ConnectDioOut[k]) begin : gen_dio_output
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( DioPadVariant[k] )
- ) u_dio_pad (
- .inout_io ( dio_pad_io[k] ),
- .in_o ( ),
- .ie_i ( 1'b0 ),
- .out_i ( dio_out_i[k] ),
- .oe_i ( dio_oe_i[k] ),
- .attr_i ( dio_attr_i[k] ),
- .warl_o ( )
- );
+ prim_pad_wrapper #(
+ .PadType ( DioPadType[k] ),
+ .ScanRole ( DioScanRole[k] )
+ ) u_dio_pad (
+ .clk_scan_i,
+ .scanmode_i ( scanmode ),
+ .pok_i ( pad_pok[DioPadBank[k]] ),
+ .inout_io ( dio_pad_io[k] ),
+ .in_o ( dio_in_o[k] ),
+ .in_raw_o ( dio_in_raw_o[k] ),
+ // This is currently not dynamically controlled.
+ // However, this may change in the future if the
+ // need arises (e.g. as part of to power sequencing).
+ .ie_i ( 1'b1 ),
+ .out_i ( dio_out_i[k] ),
+ .oe_i ( dio_oe_i[k] ),
+ .attr_i ( dio_attr_i[k] )
+ );
+ end
- assign dio_in_o[k] = 1'b0;
- end else if (ConnectDioIn[k]) begin : gen_dio_input
- prim_pad_wrapper #(
- .AttrDw ( AttrDw ),
- .Variant ( DioPadVariant[k] )
- ) u_dio_pad (
- .inout_io ( dio_pad_io[k] ),
- .in_o ( dio_in_o[k] ),
- .ie_i ( 1'b1 ),
- .out_i ( 1'b0 ),
- .oe_i ( 1'b0 ),
- .attr_i ( dio_attr_i[k] ),
- .warl_o ( )
- );
+ for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_pads
+ prim_pad_wrapper #(
+ .PadType ( MioPadType[k] ),
+ .ScanRole ( MioScanRole[k] )
+ ) u_mio_pad (
+ .clk_scan_i,
+ .scanmode_i ( scanmode ),
+ .pok_i ( pad_pok[MioPadBank[k]] ),
+ .inout_io ( mio_pad_io[k] ),
+ .in_o ( mio_in_o[k] ),
+ .in_raw_o ( mio_in_raw_o[k] ),
+ // This is currently not dynamically controlled.
+ // However, this may change in the future if the
+ // need arises (e.g. as part of to power sequencing).
+ .ie_i ( 1'b1 ),
+ .out_i ( mio_out_i[k] ),
+ .oe_i ( mio_oe_i[k] ),
+ .attr_i ( mio_attr_i[k] )
+ );
+ end
- logic unused_out, unused_oe;
- assign unused_out = dio_out_i[k];
- assign unused_oe = dio_oe_i[k];
- end else begin : gen_dio_tie_off
- logic unused_out, unused_oe, unused_pad;
- logic [AttrDw-1:0] unused_attr;
- assign dio_pad_io[k] = 1'b0;
- assign unused_pad = dio_pad_io[k];
- assign unused_out = dio_out_i[k];
- assign unused_oe = dio_oe_i[k];
- assign unused_attr = dio_attr_i[k];
- assign dio_in_o[k] = 1'b0;
- end
+ if (PhysicalPads) begin : gen_physical_pads
+ // TODO: Need to add this to the closed source repo first.
+ // physical_pads #(
+ // .NIoBanks(NIoBanks)
+ // ) (
+ // .pad_pok_o(pad_pok)
+ // );
+ assign pad_pok = '0;
+ end else begin : gen_no_physical_pads
+ assign pad_pok = '0;
end
endmodule : padring
diff --git a/hw/ip/pinmux/rtl/pinmux.sv b/hw/ip/pinmux/rtl/pinmux.sv
index 77560bf..411d516 100644
--- a/hw/ip/pinmux/rtl/pinmux.sv
+++ b/hw/ip/pinmux/rtl/pinmux.sv
@@ -61,15 +61,15 @@
output logic [NDioPads-1:0] dio_to_periph_o,
// Pad side
// MIOs
- output logic [NMioPads-1:0][AttrDw-1:0] mio_attr_o,
- output logic [NMioPads-1:0] mio_out_o,
- output logic [NMioPads-1:0] mio_oe_o,
- input [NMioPads-1:0] mio_in_i,
+ output prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_attr_o,
+ output logic [NMioPads-1:0] mio_out_o,
+ output logic [NMioPads-1:0] mio_oe_o,
+ input [NMioPads-1:0] mio_in_i,
// DIOs
- output logic [NDioPads-1:0][AttrDw-1:0] dio_attr_o,
- output logic [NDioPads-1:0] dio_out_o,
- output logic [NDioPads-1:0] dio_oe_o,
- input [NDioPads-1:0] dio_in_i
+ output prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_attr_o,
+ output logic [NDioPads-1:0] dio_out_o,
+ output logic [NDioPads-1:0] dio_oe_o,
+ input [NDioPads-1:0] dio_in_i
);
//////////////////////////////////
@@ -94,8 +94,8 @@
// Pad attribute registers //
/////////////////////////////
- logic [NDioPads-1:0][AttrDw-1:0] dio_pad_attr_q;
- logic [NMioPads-1:0][AttrDw-1:0] mio_pad_attr_q;
+ prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_pad_attr_q;
+ prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_pad_attr_q;
always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
if (!rst_ni) begin
@@ -123,14 +123,14 @@
// TODO(#5221): rework the WARL behavior
for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr
- logic [AttrDw-1:0] warl_mask;
+ prim_pad_wrapper_pkg::pad_attr_t warl_mask;
assign warl_mask = '0;
assign dio_attr_o[k] = dio_pad_attr_q[k] & warl_mask;
assign hw2reg.dio_pad_attr[k].d = dio_pad_attr_q[k] & warl_mask;
end
for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr
- logic [AttrDw-1:0] warl_mask;
+ prim_pad_wrapper_pkg::pad_attr_t warl_mask;
assign warl_mask = '0;
assign mio_attr_o[k] = mio_pad_attr_q[k] & warl_mask;
assign hw2reg.mio_pad_attr[k].d = mio_pad_attr_q[k] & warl_mask;
@@ -192,10 +192,10 @@
.low_power_alw_i(sleep_en_i),
// input signals for resume detection
- .usb_dp_async_alw_i(dio_to_periph_o[UsbDpSel]),
- .usb_dn_async_alw_i(dio_to_periph_o[UsbDnSel]),
- .usb_dppullup_en_alw_i(dio_oe_o[UsbDpPullUpSel]),
- .usb_dnpullup_en_alw_i(dio_oe_o[UsbDnPullUpSel]),
+ .usb_dp_async_alw_i(dio_to_periph_o[TargetCfg.usb_dp_idx]),
+ .usb_dn_async_alw_i(dio_to_periph_o[TargetCfg.usb_dn_idx]),
+ .usb_dppullup_en_alw_i(dio_oe_o[TargetCfg.usb_dp_pullup_idx]),
+ .usb_dnpullup_en_alw_i(dio_oe_o[TargetCfg.usb_dn_pullup_idx]),
// tie this to something from usbdev to indicate its out of reset
.usb_out_of_rst_upwr_i(usb_out_of_rst_i),
diff --git a/hw/ip/pinmux/rtl/pinmux_pkg.sv b/hw/ip/pinmux/rtl/pinmux_pkg.sv
index 2c16eac..dff92da 100644
--- a/hw/ip/pinmux/rtl/pinmux_pkg.sv
+++ b/hw/ip/pinmux/rtl/pinmux_pkg.sv
@@ -15,31 +15,39 @@
// datastructure below serves this purpose. Note that all the indices below are with respect to
// the concatenated {DIO, MIO} packed array.
typedef struct packed {
- bit const_sampling; // TODO: check whether this can be eliminated.
+ logic const_sampling; // TODO: check whether this can be eliminated.
logic [NumIOs-1:0] tie_offs; // TODO: check whether this can be eliminated.
- int tck_idx;
- int tms_idx;
- int trst_idx;
- int tdi_idx;
- int tdo_idx;
- int tap_strap0_idx;
- int tap_strap1_idx;
- int dft_strap0_idx;
- int dft_strap1_idx;
+ integer tck_idx;
+ integer tms_idx;
+ integer trst_idx;
+ integer tdi_idx;
+ integer tdo_idx;
+ integer tap_strap0_idx;
+ integer tap_strap1_idx;
+ integer dft_strap0_idx;
+ integer dft_strap1_idx;
+ integer usb_dp_idx;
+ integer usb_dn_idx;
+ integer usb_dp_pullup_idx;
+ integer usb_dn_pullup_idx;
} target_cfg_t;
parameter target_cfg_t DefaultTargetCfg = '{
- const_sampling: 1'b0,
- tie_offs: '0,
- tck_idx: 0,
- tms_idx: 0,
- trst_idx: 0,
- tdi_idx: 0,
- tdo_idx: 0,
- tap_strap0_idx: 0,
- tap_strap1_idx: 0,
- dft_strap0_idx: 0,
- dft_strap1_idx: 0
+ const_sampling: 1'b0,
+ tie_offs: '0,
+ tck_idx: 0,
+ tms_idx: 0,
+ trst_idx: 0,
+ tdi_idx: 0,
+ tdo_idx: 0,
+ tap_strap0_idx: 0,
+ tap_strap1_idx: 0,
+ dft_strap0_idx: 0,
+ dft_strap1_idx: 0,
+ usb_dp_idx: 0,
+ usb_dn_idx: 0,
+ usb_dp_pullup_idx: 0,
+ usb_dn_pullup_idx: 0
};
// Wakeup Detector Modes
diff --git a/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv b/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
index c02080e..baf5347 100644
--- a/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
+++ b/hw/ip/pinmux/rtl/pinmux_reg_pkg.sv
@@ -14,12 +14,6 @@
parameter int NDioPads = 16;
parameter int NWkupDetect = 8;
parameter int WkupCntWidth = 8;
- parameter int NUsbDevPads = 0;
- parameter int NDioPadUsbDevStart = 0;
- parameter int UsbDpSel = 0;
- parameter int UsbDnSel = 0;
- parameter int UsbDpPullUpSel = 0;
- parameter int UsbDnPullUpSel = 0;
// Address widths within the block
parameter int BlockAw = 11;
diff --git a/hw/ip/prim/prim_pad_wrapper.core b/hw/ip/prim/prim_pad_wrapper.core
index c7264c6..05a3593 100644
--- a/hw/ip/prim/prim_pad_wrapper.core
+++ b/hw/ip/prim/prim_pad_wrapper.core
@@ -9,6 +9,7 @@
primgen_dep:
depend:
- lowrisc:prim:prim_pkg
+ - lowrisc:prim:pad_wrapper_pkg
- lowrisc:prim:primgen
diff --git a/hw/ip/prim/prim_pad_wrapper_pkg.core b/hw/ip/prim/prim_pad_wrapper_pkg.core
new file mode 100644
index 0000000..76816d8
--- /dev/null
+++ b/hw/ip/prim/prim_pad_wrapper_pkg.core
@@ -0,0 +1,39 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:pad_wrapper_pkg"
+description: "Package for pad wrapper"
+filesets:
+ files_rtl:
+ files:
+ - rtl/prim_pad_wrapper_pkg.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/ip/prim/rtl/prim_pad_wrapper_pkg.sv b/hw/ip/prim/rtl/prim_pad_wrapper_pkg.sv
new file mode 100644
index 0000000..7b16642
--- /dev/null
+++ b/hw/ip/prim/rtl/prim_pad_wrapper_pkg.sv
@@ -0,0 +1,43 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package prim_pad_wrapper_pkg;
+
+ typedef enum logic [1:0] {
+ BidirStd = 2'h0, // Standard bidirectional pad
+ BidirTol = 2'h1, // Voltage tolerant pad
+ BidirOd = 2'h2, // Open-drain capable pad
+ InputStd = 2'h3 // Input-only pad
+ } pad_type_e;
+
+ typedef enum logic [1:0] {
+ NoScan = 2'h0,
+ ScanIn = 2'h1,
+ ScanOut = 2'h2
+ } scan_role_e;
+
+ // Pad attributes
+ parameter int DriveStrDw = 4;
+ parameter int SlewRateDw = 2;
+
+ typedef struct packed {
+ logic [DriveStrDw-1:0] drive_strength; // Drive strength (0000: weakest, 1111: strongest).
+ logic [SlewRateDw-1:0] slew_rate; // Slew rate (0: slowest, 11: fastest).
+ logic od_en; // Open-drain enable
+ logic schmitt_en; // Schmitt trigger enable.
+ logic keep_en; // Keeper enable.
+ logic pull_select; // Pull direction (0: pull down, 1: pull up).
+ logic pull_en; // Pull enable.
+ logic virt_od_en; // Virtual open drain enable.
+ logic invert; // Input/output inversion.
+ } pad_attr_t;
+
+ parameter int AttrDw = $bits(pad_attr_t);
+
+ // Power OK signals (library dependent)
+ parameter int PokDw = 8;
+
+ typedef logic [PokDw-1:0] pad_pok_t;
+
+endpackage : prim_pad_wrapper_pkg
diff --git a/hw/ip/prim_generic/prim_generic_pad_attr.core b/hw/ip/prim_generic/prim_generic_pad_attr.core
new file mode 100644
index 0000000..1cf1eaf
--- /dev/null
+++ b/hw/ip/prim_generic/prim_generic_pad_attr.core
@@ -0,0 +1,44 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_generic:pad_attr"
+description: "Technology-independent pad attribute WARL module (for sim only!)"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:prim:assert
+ - lowrisc:prim:pad_wrapper_pkg
+ files:
+ - rtl/prim_generic_pad_attr.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ #- lint/prim_generic_pad_attr.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ #- lint/prim_generic_pad_attr.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core
index d15c759..3a37482 100644
--- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core
+++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core
@@ -9,6 +9,7 @@
files_rtl:
depend:
- lowrisc:prim:assert
+ - lowrisc:prim:pad_wrapper_pkg
files:
- rtl/prim_generic_pad_wrapper.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv b/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv
new file mode 100644
index 0000000..23ef717
--- /dev/null
+++ b/hw/ip/prim_generic/rtl/prim_generic_pad_attr.sv
@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+`include "prim_assert.sv"
+
+module prim_generic_pad_attr
+ import prim_pad_wrapper_pkg::*;
+#(
+ parameter pad_type_e PadType = BidirStd // currently ignored in the generic model
+) (
+ output pad_attr_t attr_warl_o
+);
+
+ // Currently supported pad attributes of the generic pad library:
+ //
+ // - inversion
+ // - virtual open drain
+ // - keeper
+ // - pullup / pulldown
+ // - 1 driving strength bit
+ //
+ // Note that the last three attributes are not supported on Verilator.
+ always_comb begin : p_attr
+ attr_warl_o = '0;
+ attr_warl_o.invert = 1'b1;
+ attr_warl_o.virt_od_en = 1'b1;
+ attr_warl_o.keep_en = 1'b1;
+// Driving strength and pulls are not supported by Verilator
+`ifndef VERILATOR
+ attr_warl_o.pull_en = 1'b1;
+ attr_warl_o.pull_select = 1'b1;
+ // Only one driving strength bit is supported.
+ attr_warl_o.drive_strength[0] = 1'b1;
+`endif
+ end
+
+endmodule : prim_generic_pad_attr
diff --git a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv b/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
index 62a518e..11d3151 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
@@ -7,87 +7,57 @@
`include "prim_assert.sv"
-module prim_generic_pad_wrapper #(
- parameter int Variant = 0, // currently ignored
- parameter int AttrDw = 10,
- parameter bit WarlOnly = 0 // If set to 1, no pad is instantiated and only warl_o is driven
+module prim_generic_pad_wrapper
+ import prim_pad_wrapper_pkg::*;
+#(
+ // These parameters are ignored in this model.
+ parameter pad_type_e PadType = BidirStd,
+ parameter scan_role_e ScanRole = NoScan
) (
+ // This is only used for scanmode (not used in generic models)
+ input clk_scan_i,
+ input scanmode_i,
+ // Power sequencing signals (not used in generic models)
+ input pad_pok_t pok_i,
+ // Main Pad signals
inout wire inout_io, // bidirectional pad
output logic in_o, // input data
+ output logic in_raw_o, // uninverted output data
input ie_i, // input enable
input out_i, // output data
input oe_i, // output enable
- // additional attributes
- input [AttrDw-1:0] attr_i,
- output logic [AttrDw-1:0] warl_o
+ input pad_attr_t attr_i // additional pad attributes
);
- // Supported attributes:
- // [x] Bit 0: input/output inversion,
- // [x] Bit 1: Virtual open drain enable.
- // [x] Bit 2: Pull enable.
- // [x] Bit 3: Pull select (0: pull down, 1: pull up).
- // [x] Bit 4: Keeper enable.
- // [ ] Bit 5: Schmitt trigger enable.
- // [ ] Bit 6: Slew rate (0: slow, 1: fast).
- // [x] Bit 7/8: Drive strength (00: weakest, 11: strongest).
- // [ ] Bit 9: Reserved.
- assign warl_o = AttrDw'(10'h19F);
+ // not all signals are used here.
+ logic unused_sigs;
+ assign unused_sigs = ^{attr_i.slew_rate,
+ attr_i.drive_strength[3:1],
+ attr_i.od_en,
+ attr_i.schmitt_en,
+ scanmode_i,
+ pok_i};
- if (WarlOnly) begin : gen_warl
- assign inout_io = 1'bz;
- assign in_o = 1'b0;
+ assign in_raw_o = (ie_i) ? inout_io : 1'bz;
+ // input inversion
+ assign in_o = attr_i.invert ^ in_raw_o;
- logic [AttrDw-1:0] unused_attr;
- logic unused_ie, unused_oe, unused_out, unused_inout;
- assign unused_ie = ie_i;
- assign unused_oe = oe_i;
- assign unused_out = out_i;
- assign unused_attr = attr_i;
- assign unused_inout = inout_io;
- end else begin : gen_pad
- // get pad attributes
- logic unused_sm, kp, unused_sr, ps, pe, od, inv;
- typedef enum logic [1:0] {DRIVE_00 = 2'b00,
- DRIVE_01 = 2'b01,
- DRIVE_10 = 2'b10,
- DRIVE_11 = 2'b11} drv_e;
- drv_e drv;
- assign {drv, unused_sr, unused_sm, kp, ps, pe, od, inv} = attr_i[8:0];
+ // virtual open drain emulation
+ logic oe, out;
+ assign out = out_i ^ attr_i.invert;
+ assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
- if (AttrDw > 9) begin : gen_unused_attr
- logic [AttrDw-9-1:0] unused_attr;
- assign unused_attr = attr_i[AttrDw-1:9];
- end
-
- // input inversion
- logic in;
- assign in = inv ^ inout_io;
-
- // virtual open drain emulation
- logic oe, out;
- assign out = out_i ^ inv;
- assign oe = oe_i & ((od & ~out) | ~od);
-
- // driving strength attributes are not supported by verilator
+// drive strength attributes are not supported by verilator
`ifdef VERILATOR
- assign inout_io = (oe) ? out : 1'bz;
- // received data driver
- assign in_o = (ie_i) ? in : 1'bz;
+ assign inout_io = (oe) ? out : 1'bz;
`else
- // different driver types
- assign (strong0, strong1) inout_io = (oe && drv != DRIVE_00) ? out : 1'bz;
- assign (pull0, pull1) inout_io = (oe && drv == DRIVE_00) ? out : 1'bz;
- // pullup / pulldown termination
- assign (weak0, weak1) inout_io = pe ? ps : 1'bz;
- // fake trireg emulation
- assign (weak0, weak1) inout_io = (kp) ? inout_io : 1'bz;
- // received data driver
- assign in_o = (ie_i) ? in : 1'bz;
+ // different driver types
+ assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
+ assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
+ // pullup / pulldown termination
+ assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
+ // fake trireg emulation
+ assign (weak0, weak1) inout_io = (attr_i.keep_en) ? inout_io : 1'bz;
`endif
- end
-
- // assertions
- `ASSERT_INIT(AttrDwCheck_A, AttrDw >= 9)
endmodule : prim_generic_pad_wrapper
diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core
new file mode 100644
index 0000000..076c1cd
--- /dev/null
+++ b/hw/ip/prim_xilinx/prim_xilinx_pad_attr.core
@@ -0,0 +1,44 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim_xilinx:pad_attr"
+description: "Pad attribute WARL module for Xilinx pads"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:prim:assert
+ - lowrisc:prim:pad_wrapper_pkg
+ files:
+ - rtl/prim_xilinx_pad_attr.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ #- lint/prim_xilinx_pad_attr.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ #- lint/prim_xilinx_pad_attr.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
diff --git a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
index 5e6ff67..eb0cc5e 100644
--- a/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
+++ b/hw/ip/prim_xilinx/prim_xilinx_pad_wrapper.core
@@ -7,6 +7,9 @@
description: "prim"
filesets:
files_rtl:
+ depend:
+ - lowrisc:prim:assert
+ - lowrisc:prim:pad_wrapper_pkg
files:
- rtl/prim_xilinx_pad_wrapper.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv
new file mode 100644
index 0000000..1f1187e
--- /dev/null
+++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_attr.sv
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+`include "prim_assert.sv"
+
+module prim_xilinx_pad_attr
+ import prim_pad_wrapper_pkg::*;
+#(
+ // This parameter is ignored in this Xilinx variant.
+ parameter pad_type_e PadType = BidirStd
+) (
+ output pad_attr_t attr_warl_o
+);
+
+ // Currently supporte pad attributes of the Xilinx pad library.
+ //
+ // - inversion
+ // - virtual open drain
+ //
+ // TODO: add support for dynamic pull-up/down using the PULLUP/PULLDOWN primitives
+ // from the vivado-7series library (https://www.xilinx.com/support/documentation/
+ // sw_manuals/xilinx2020_2/ug953-vivado-7series-libraries.pdf)
+ always_comb begin : p_attr
+ attr_warl_o = '0;
+ attr_warl_o.invert = 1'b1;
+ attr_warl_o.virt_od_en = 1'b1;
+ end
+
+endmodule : prim_xilinx_pad_attr
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
index f9649dd..58608ff 100644
--- a/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
+++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv
@@ -6,73 +6,58 @@
// virtual open drain feature.
-module prim_xilinx_pad_wrapper #(
- parameter int Variant = 0, // currently ignored
- parameter int AttrDw = 10,
- parameter bit WarlOnly = 0 // If set to 1, no pad is instantiated and only warl_o is driven
+module prim_xilinx_pad_wrapper
+ import prim_pad_wrapper_pkg::*;
+#(
+ // These parameters are ignored in this Xilinx variant.
+ parameter pad_type_e PadType = BidirStd,
+ parameter scan_role_e ScanRole = NoScan
) (
+ // This is only used for scanmode (not used in this Xilinx variant)
+ input clk_scan_i,
+ input scanmode_i,
+ // Power sequencing signals (not used in this Xilinx variant)
+ input pad_pok_t pok_i,
+ // Main Pad signals
inout wire inout_io, // bidirectional pad
output logic in_o, // input data
+ output logic in_raw_o, // uninverted output data
input ie_i, // input enable
input out_i, // output data
input oe_i, // output enable
- // additional attributes
- input [AttrDw-1:0] attr_i,
- output logic [AttrDw-1:0] warl_o
+ input pad_attr_t attr_i // additional pad attributes
);
- // Supported attributes:
- // [x] Bit 0: input/output inversion,
- // [x] Bit 1: Virtual open drain enable.
- // [ ] Bit 2: Pull enable.
- // [ ] Bit 3: Pull select (0: pull down, 1: pull up).
- // [ ] Bit 4: Keeper enable.
- // [ ] Bit 5: Schmitt trigger enable.
- // [ ] Bit 6: Slew rate (0: slow, 1: fast).
- // [ ] Bit 7/8: Drive strength (00: weakest, 11: strongest).
- // [ ] Bit 9: Reserved.
- assign warl_o = AttrDw'(2'h3);
+ // not all signals are used here.
+ logic unused_sigs;
+ assign unused_sigs = ^{attr_i.slew_rate,
+ attr_i.drive_strength,
+ attr_i.od_en,
+ attr_i.schmitt_en,
+ attr_i.keep_en,
+ attr_i.pull_en,
+ attr_i.pull_select,
+ scanmode_i,
+ pok_i};
- if (WarlOnly) begin : gen_warl
- assign inout_io = 1'bz;
- assign in_o = 1'b0;
+ // input inversion
+ logic in;
+ assign in_raw_o = (ie_i) ? in : 1'bz;
+ assign in_o = attr_i.invert ^ in_raw_o;
- logic [AttrDw-1:0] unused_attr;
- logic unused_ie, unused_oe, unused_out, unused_inout;
- assign unused_ie = ie_i;
- assign unused_oe = oe_i;
- assign unused_out = out_i;
- assign unused_attr = attr_i;
- assign unused_inout = inout_io;
- end else begin : gen_pad
+ // virtual open drain emulation
+ logic oe_n, out;
+ assign out = out_i ^ attr_i.invert;
+ // oe_n = 0: enable driver
+ // oe_n = 1: disable driver
+ assign oe_n = ~oe_i | (out & attr_i.virt_od_en);
- // get pad attributes
- logic od, inv;
- assign {od, inv} = attr_i[1:0];
-
- if (AttrDw > 9) begin : gen_unused_attr
- logic [AttrDw-9-1:0] unused_attr;
- assign unused_attr = attr_i[AttrDw-1:9];
- end
-
- // input inversion and buffer
- logic in;
- assign in_o = (ie_i) ? inv ^ in : 1'bz;
-
- // virtual open drain emulation
- logic oe_n, out;
- assign out = out_i ^ inv;
- // oe_n = 0: enable driver
- // oe_n = 1: disable driver
- assign oe_n = ~oe_i | (out & od);
-
- // driver
- IOBUF i_iobuf (
- .T ( oe_n ),
- .I ( out ),
- .O ( in ),
- .IO ( inout_io )
- );
- end
+ // driver
+ IOBUF u_iobuf (
+ .T ( oe_n ),
+ .I ( out ),
+ .O ( in ),
+ .IO ( inout_io )
+ );
endmodule : prim_xilinx_pad_wrapper
diff --git a/hw/top_earlgrey/clkgen_xil7series.core b/hw/top_earlgrey/clkgen_xil7series.core
new file mode 100644
index 0000000..6324c5c
--- /dev/null
+++ b/hw/top_earlgrey/clkgen_xil7series.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# TODO: long term this should be merged into AST.
+
+name: "lowrisc:systems:clkgen_xil7series"
+description: "Clock generation infrastructure for Xilinx 7-Series FPGAs."
+filesets:
+ files_rtl:
+ files:
+ - rtl/clkgen_xil7series.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index ee0baf1..8fcda92 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -7543,535 +7543,1923 @@
]
}
]
+ pinout:
+ {
+ banks:
+ [
+ VCC
+ AVCC
+ VIOA
+ VIOB
+ ]
+ pads:
+ [
+ {
+ name: POR_N
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: System reset
+ idx: 0
+ }
+ {
+ name: SPI_HOST_D0
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI host data
+ idx: 1
+ }
+ {
+ name: SPI_HOST_D1
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI host data
+ idx: 2
+ }
+ {
+ name: SPI_HOST_D2
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI host data
+ idx: 3
+ }
+ {
+ name: SPI_HOST_D3
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI host data
+ idx: 4
+ }
+ {
+ name: SPI_HOST_CLK
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI host clock
+ idx: 5
+ }
+ {
+ name: SPI_HOST_CS_L
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI host chip select
+ idx: 6
+ }
+ {
+ name: SPI_DEV_D0
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI device data
+ idx: 7
+ }
+ {
+ name: SPI_DEV_D1
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI device data
+ idx: 8
+ }
+ {
+ name: SPI_DEV_D2
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI device data
+ idx: 9
+ }
+ {
+ name: SPI_DEV_D3
+ type: BidirStd
+ bank: VIOA
+ connection: direct
+ desc: SPI device data
+ idx: 10
+ }
+ {
+ name: SPI_DEV_CLK
+ type: InputStd
+ bank: VIOA
+ connection: direct
+ desc: SPI device clock
+ idx: 11
+ }
+ {
+ name: SPI_DEV_CS_L
+ type: InputStd
+ bank: VIOA
+ connection: direct
+ desc: SPI device chip select
+ idx: 12
+ }
+ {
+ name: USB_P
+ type: BidirTol
+ bank: VCC
+ connection: manual
+ desc: USB P signal
+ idx: 13
+ }
+ {
+ name: USB_N
+ type: BidirTol
+ bank: VCC
+ connection: manual
+ desc: USB N signal
+ idx: 14
+ }
+ {
+ name: CC1
+ type: InputStd
+ bank: AVCC
+ connection: manual
+ desc: ADC input 1
+ idx: 15
+ }
+ {
+ name: CC2
+ type: InputStd
+ bank: AVCC
+ connection: manual
+ desc: ADC input 2
+ idx: 16
+ }
+ {
+ name: FLASH_TEST_MODE0
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Flash test mode signal
+ idx: 17
+ }
+ {
+ name: FLASH_TEST_MODE1
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Flash test mode signal
+ idx: 18
+ }
+ {
+ name: FLASH_TEST_MODE2
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Flash test mode signal
+ idx: 19
+ }
+ {
+ name: FLASH_TEST_MODE3
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Flash test mode signal
+ idx: 20
+ }
+ {
+ name: FLASH_TEST_VOLT
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Flash test voltage input
+ idx: 21
+ }
+ {
+ name: IOA0
+ type: InputStd
+ bank: VIOA
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 0
+ }
+ {
+ name: IOA1
+ type: InputStd
+ bank: VIOA
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 1
+ }
+ {
+ name: IOA2
+ type: InputStd
+ bank: VIOA
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 2
+ }
+ {
+ name: IOA3
+ type: InputStd
+ bank: VIOA
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 3
+ }
+ {
+ name: IOA4
+ type: BidirOd
+ bank: VIOA
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 4
+ }
+ {
+ name: IOA5
+ type: BidirOd
+ bank: VIOA
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 5
+ }
+ {
+ name: IOB0
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 6
+ }
+ {
+ name: IOB1
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 7
+ }
+ {
+ name: IOB2
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 8
+ }
+ {
+ name: IOB3
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 9
+ }
+ {
+ name: IOB4
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 10
+ }
+ {
+ name: IOB5
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 11
+ }
+ {
+ name: IOB6
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 12
+ }
+ {
+ name: IOB7
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 13
+ }
+ {
+ name: IOB8
+ type: BidirOd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 14
+ }
+ {
+ name: IOB9
+ type: BidirOd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 15
+ }
+ {
+ name: IOB10
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 16
+ }
+ {
+ name: IOB11
+ type: InputStd
+ bank: VIOB
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 17
+ }
+ {
+ name: IOC0
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 18
+ }
+ {
+ name: IOC1
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 19
+ }
+ {
+ name: IOC2
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 20
+ }
+ {
+ name: IOC3
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 21
+ }
+ {
+ name: IOC4
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 22
+ }
+ {
+ name: IOC5
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 23
+ }
+ {
+ name: IOC6
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 24
+ }
+ {
+ name: IOC7
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 25
+ }
+ {
+ name: IOC8
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 26
+ }
+ {
+ name: IOC9
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 27
+ }
+ {
+ name: IOC10
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 28
+ }
+ {
+ name: IOC11
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 29
+ }
+ {
+ name: IOR0
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 30
+ }
+ {
+ name: IOR1
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 31
+ }
+ {
+ name: IOR2
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 32
+ }
+ {
+ name: IOR3
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 33
+ }
+ {
+ name: IOR4
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 34
+ }
+ {
+ name: IOR5
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 35
+ }
+ {
+ name: IOR6
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 36
+ }
+ {
+ name: IOR7
+ type: InputStd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 37
+ }
+ {
+ name: IOR8
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 38
+ }
+ {
+ name: IOR9
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 39
+ }
+ {
+ name: IOR10
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 40
+ }
+ {
+ name: IOR11
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 41
+ }
+ {
+ name: IOR12
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 42
+ }
+ {
+ name: IOR13
+ type: BidirOd
+ bank: VCC
+ connection: muxed
+ desc: Muxed IO pad
+ idx: 43
+ }
+ ]
+ }
pinmux:
{
- num_mio: 44
- dio_modules:
+ signals:
[
{
- name: spi_device
- pad:
- [
- ChC[0..5]
- ]
+ instance: spi_host0
+ port: sck
+ connection: direct
+ pad: SPI_HOST_CLK
+ desc: ""
}
{
- name: spi_host0
- pad:
- [
- ChB[0..5]
- ]
+ instance: spi_host0
+ port: csb
+ connection: direct
+ pad: SPI_HOST_CS_L
+ desc: ""
}
{
- name: usbdev
- pad:
- [
- ChA[0..8]
- ]
+ instance: spi_host0
+ port: sd[0]
+ connection: direct
+ pad: SPI_HOST_D0
+ desc: ""
}
- ]
- mio_modules:
- [
- gpio
- uart0
- uart1
- uart2
- uart3
- i2c0
- i2c1
- i2c2
- pattgen
- spi_host1
- flash_ctrl
- sensor_ctrl_aon
- ]
- nc_modules:
- [
- rv_timer
- hmac
+ {
+ instance: spi_host0
+ port: sd[1]
+ connection: direct
+ pad: SPI_HOST_D1
+ desc: ""
+ }
+ {
+ instance: spi_host0
+ port: sd[2]
+ connection: direct
+ pad: SPI_HOST_D2
+ desc: ""
+ }
+ {
+ instance: spi_host0
+ port: sd[3]
+ connection: direct
+ pad: SPI_HOST_D3
+ desc: ""
+ }
+ {
+ instance: spi_device
+ port: sck
+ connection: direct
+ pad: SPI_DEV_CLK
+ desc: ""
+ }
+ {
+ instance: spi_device
+ port: csb
+ connection: direct
+ pad: SPI_DEV_CS_L
+ desc: ""
+ }
+ {
+ instance: spi_device
+ port: sd[0]
+ connection: direct
+ pad: SPI_DEV_D0
+ desc: ""
+ }
+ {
+ instance: spi_device
+ port: sd[1]
+ connection: direct
+ pad: SPI_DEV_D1
+ desc: ""
+ }
+ {
+ instance: spi_device
+ port: sd[2]
+ connection: direct
+ pad: SPI_DEV_D2
+ desc: ""
+ }
+ {
+ instance: spi_device
+ port: sd[3]
+ connection: direct
+ pad: SPI_DEV_D3
+ desc: ""
+ }
+ {
+ instance: usbdev
+ port: ""
+ connection: manual
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: gpio
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: uart0
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: uart1
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: uart2
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: uart3
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: i2c0
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: i2c1
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: i2c2
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: pattgen
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: spi_host1
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: flash_ctrl
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
+ {
+ instance: sensor_ctrl_aon
+ port: ""
+ connection: muxed
+ pad: ""
+ desc: ""
+ }
]
num_wkup_detect: 8
wkup_cnt_width: 8
- dio:
+ ios:
[
{
- name: spi_device_sck
- width: 1
- type: input
- module_name: spi_device
- pad:
- [
- {
- name: ChC
- index: 0
- }
- ]
- }
- {
- name: spi_device_csb
- width: 1
- type: input
- module_name: spi_device
- pad:
- [
- {
- name: ChC
- index: 1
- }
- ]
- }
- {
- name: spi_device_sd
+ name: spi_host0_sd
width: 4
type: inout
- module_name: spi_device
- pad:
- [
- {
- name: ChC
- index: 2
- }
- {
- name: ChC
- index: 3
- }
- {
- name: ChC
- index: 4
- }
- {
- name: ChC
- index: 5
- }
- ]
- }
- {
- name: spi_host0_sck
- width: 1
- type: output
- module_name: spi_host0
- pad:
- [
- {
- name: ChB
- index: 0
- }
- ]
- }
- {
- name: spi_host0_csb
- width: 1
- type: output
- module_name: spi_host0
- pad:
- [
- {
- name: ChB
- index: 1
- }
- ]
+ idx: 0
+ pad: SPI_HOST_D0
+ connection: direct
+ glob_idx: 0
}
{
name: spi_host0_sd
width: 4
type: inout
- module_name: spi_host0
- pad:
- [
- {
- name: ChB
- index: 2
- }
- {
- name: ChB
- index: 3
- }
- {
- name: ChB
- index: 4
- }
- {
- name: ChB
- index: 5
- }
- ]
+ idx: 1
+ pad: SPI_HOST_D1
+ connection: direct
+ glob_idx: 1
}
{
- name: usbdev_sense
- width: 1
- type: input
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 0
- }
- ]
+ name: spi_host0_sd
+ width: 4
+ type: inout
+ idx: 2
+ pad: SPI_HOST_D2
+ connection: direct
+ glob_idx: 2
}
{
- name: usbdev_se0
- width: 1
- type: output
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 1
- }
- ]
+ name: spi_host0_sd
+ width: 4
+ type: inout
+ idx: 3
+ pad: SPI_HOST_D3
+ connection: direct
+ glob_idx: 3
}
{
- name: usbdev_dp_pullup
- width: 1
- type: output
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 2
- }
- ]
+ name: spi_device_sd
+ width: 4
+ type: inout
+ idx: 0
+ pad: SPI_DEV_D0
+ connection: direct
+ glob_idx: 4
}
{
- name: usbdev_dn_pullup
- width: 1
- type: output
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 3
- }
- ]
+ name: spi_device_sd
+ width: 4
+ type: inout
+ idx: 1
+ pad: SPI_DEV_D1
+ connection: direct
+ glob_idx: 5
}
{
- name: usbdev_tx_mode_se
- width: 1
- type: output
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 4
- }
- ]
+ name: spi_device_sd
+ width: 4
+ type: inout
+ idx: 2
+ pad: SPI_DEV_D2
+ connection: direct
+ glob_idx: 6
}
{
- name: usbdev_suspend
- width: 1
- type: output
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 5
- }
- ]
+ name: spi_device_sd
+ width: 4
+ type: inout
+ idx: 3
+ pad: SPI_DEV_D3
+ connection: direct
+ glob_idx: 7
}
{
name: usbdev_d
width: 1
type: inout
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 6
- }
- ]
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 8
}
{
name: usbdev_dp
width: 1
type: inout
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 7
- }
- ]
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 9
}
{
name: usbdev_dn
width: 1
type: inout
- module_name: usbdev
- pad:
- [
- {
- name: ChA
- index: 8
- }
- ]
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 10
}
- ]
- inputs:
- [
{
name: gpio_gpio
width: 32
type: inout
- module_name: gpio
+ idx: 0
+ pad: ""
+ connection: muxed
+ glob_idx: 0
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 1
+ pad: ""
+ connection: muxed
+ glob_idx: 1
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 2
+ pad: ""
+ connection: muxed
+ glob_idx: 2
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 3
+ pad: ""
+ connection: muxed
+ glob_idx: 3
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 4
+ pad: ""
+ connection: muxed
+ glob_idx: 4
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 5
+ pad: ""
+ connection: muxed
+ glob_idx: 5
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 6
+ pad: ""
+ connection: muxed
+ glob_idx: 6
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 7
+ pad: ""
+ connection: muxed
+ glob_idx: 7
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 8
+ pad: ""
+ connection: muxed
+ glob_idx: 8
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 9
+ pad: ""
+ connection: muxed
+ glob_idx: 9
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 10
+ pad: ""
+ connection: muxed
+ glob_idx: 10
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 11
+ pad: ""
+ connection: muxed
+ glob_idx: 11
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 12
+ pad: ""
+ connection: muxed
+ glob_idx: 12
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 13
+ pad: ""
+ connection: muxed
+ glob_idx: 13
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 14
+ pad: ""
+ connection: muxed
+ glob_idx: 14
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 15
+ pad: ""
+ connection: muxed
+ glob_idx: 15
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 16
+ pad: ""
+ connection: muxed
+ glob_idx: 16
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 17
+ pad: ""
+ connection: muxed
+ glob_idx: 17
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 18
+ pad: ""
+ connection: muxed
+ glob_idx: 18
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 19
+ pad: ""
+ connection: muxed
+ glob_idx: 19
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 20
+ pad: ""
+ connection: muxed
+ glob_idx: 20
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 21
+ pad: ""
+ connection: muxed
+ glob_idx: 21
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 22
+ pad: ""
+ connection: muxed
+ glob_idx: 22
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 23
+ pad: ""
+ connection: muxed
+ glob_idx: 23
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 24
+ pad: ""
+ connection: muxed
+ glob_idx: 24
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 25
+ pad: ""
+ connection: muxed
+ glob_idx: 25
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 26
+ pad: ""
+ connection: muxed
+ glob_idx: 26
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 27
+ pad: ""
+ connection: muxed
+ glob_idx: 27
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 28
+ pad: ""
+ connection: muxed
+ glob_idx: 28
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 29
+ pad: ""
+ connection: muxed
+ glob_idx: 29
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 30
+ pad: ""
+ connection: muxed
+ glob_idx: 30
+ }
+ {
+ name: gpio_gpio
+ width: 32
+ type: inout
+ idx: 31
+ pad: ""
+ connection: muxed
+ glob_idx: 31
+ }
+ {
+ name: i2c0_sda
+ width: 1
+ type: inout
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 32
+ }
+ {
+ name: i2c0_scl
+ width: 1
+ type: inout
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 33
+ }
+ {
+ name: i2c1_sda
+ width: 1
+ type: inout
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 34
+ }
+ {
+ name: i2c1_scl
+ width: 1
+ type: inout
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 35
+ }
+ {
+ name: i2c2_sda
+ width: 1
+ type: inout
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 36
+ }
+ {
+ name: i2c2_scl
+ width: 1
+ type: inout
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 37
+ }
+ {
+ name: spi_host1_sd
+ width: 4
+ type: inout
+ idx: 0
+ pad: ""
+ connection: muxed
+ glob_idx: 38
+ }
+ {
+ name: spi_host1_sd
+ width: 4
+ type: inout
+ idx: 1
+ pad: ""
+ connection: muxed
+ glob_idx: 39
+ }
+ {
+ name: spi_host1_sd
+ width: 4
+ type: inout
+ idx: 2
+ pad: ""
+ connection: muxed
+ glob_idx: 40
+ }
+ {
+ name: spi_host1_sd
+ width: 4
+ type: inout
+ idx: 3
+ pad: ""
+ connection: muxed
+ glob_idx: 41
+ }
+ {
+ name: spi_device_sck
+ width: 1
+ type: input
+ idx: -1
+ pad: SPI_DEV_CLK
+ connection: direct
+ glob_idx: 11
+ }
+ {
+ name: spi_device_csb
+ width: 1
+ type: input
+ idx: -1
+ pad: SPI_DEV_CS_L
+ connection: direct
+ glob_idx: 12
+ }
+ {
+ name: usbdev_sense
+ width: 1
+ type: input
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 13
}
{
name: uart0_rx
width: 1
type: input
- module_name: uart0
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 42
}
{
name: uart1_rx
width: 1
type: input
- module_name: uart1
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 43
}
{
name: uart2_rx
width: 1
type: input
- module_name: uart2
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 44
}
{
name: uart3_rx
width: 1
type: input
- module_name: uart3
- }
- {
- name: i2c0_sda
- width: 1
- type: inout
- module_name: i2c0
- }
- {
- name: i2c0_scl
- width: 1
- type: inout
- module_name: i2c0
- }
- {
- name: i2c1_sda
- width: 1
- type: inout
- module_name: i2c1
- }
- {
- name: i2c1_scl
- width: 1
- type: inout
- module_name: i2c1
- }
- {
- name: i2c2_sda
- width: 1
- type: inout
- module_name: i2c2
- }
- {
- name: i2c2_scl
- width: 1
- type: inout
- module_name: i2c2
- }
- {
- name: spi_host1_sd
- width: 4
- type: inout
- module_name: spi_host1
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 45
}
{
name: flash_ctrl_tck
width: 1
type: input
- module_name: flash_ctrl
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 46
}
{
name: flash_ctrl_tms
width: 1
type: input
- module_name: flash_ctrl
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 47
}
{
name: flash_ctrl_tdi
width: 1
type: input
- module_name: flash_ctrl
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 48
}
{
name: sensor_ctrl_aon_ast_debug_in
width: 10
type: input
- module_name: sensor_ctrl_aon
+ idx: 0
+ pad: ""
+ connection: muxed
+ glob_idx: 49
}
- ]
- outputs:
- [
{
- name: gpio_gpio
- width: 32
- type: inout
- module_name: gpio
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 1
+ pad: ""
+ connection: muxed
+ glob_idx: 50
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 2
+ pad: ""
+ connection: muxed
+ glob_idx: 51
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 3
+ pad: ""
+ connection: muxed
+ glob_idx: 52
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 4
+ pad: ""
+ connection: muxed
+ glob_idx: 53
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 5
+ pad: ""
+ connection: muxed
+ glob_idx: 54
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 6
+ pad: ""
+ connection: muxed
+ glob_idx: 55
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 7
+ pad: ""
+ connection: muxed
+ glob_idx: 56
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 8
+ pad: ""
+ connection: muxed
+ glob_idx: 57
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_in
+ width: 10
+ type: input
+ idx: 9
+ pad: ""
+ connection: muxed
+ glob_idx: 58
+ }
+ {
+ name: spi_host0_sck
+ width: 1
+ type: output
+ idx: -1
+ pad: SPI_HOST_CLK
+ connection: direct
+ glob_idx: 14
+ }
+ {
+ name: spi_host0_csb
+ width: 1
+ type: output
+ idx: -1
+ pad: SPI_HOST_CS_L
+ connection: direct
+ glob_idx: 15
+ }
+ {
+ name: usbdev_se0
+ width: 1
+ type: output
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 16
+ }
+ {
+ name: usbdev_dp_pullup
+ width: 1
+ type: output
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 17
+ }
+ {
+ name: usbdev_dn_pullup
+ width: 1
+ type: output
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 18
+ }
+ {
+ name: usbdev_tx_mode_se
+ width: 1
+ type: output
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 19
+ }
+ {
+ name: usbdev_suspend
+ width: 1
+ type: output
+ idx: -1
+ pad: ""
+ connection: manual
+ glob_idx: 20
}
{
name: uart0_tx
width: 1
type: output
- module_name: uart0
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 42
}
{
name: uart1_tx
width: 1
type: output
- module_name: uart1
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 43
}
{
name: uart2_tx
width: 1
type: output
- module_name: uart2
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 44
}
{
name: uart3_tx
width: 1
type: output
- module_name: uart3
- }
- {
- name: i2c0_sda
- width: 1
- type: inout
- module_name: i2c0
- }
- {
- name: i2c0_scl
- width: 1
- type: inout
- module_name: i2c0
- }
- {
- name: i2c1_sda
- width: 1
- type: inout
- module_name: i2c1
- }
- {
- name: i2c1_scl
- width: 1
- type: inout
- module_name: i2c1
- }
- {
- name: i2c2_sda
- width: 1
- type: inout
- module_name: i2c2
- }
- {
- name: i2c2_scl
- width: 1
- type: inout
- module_name: i2c2
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 45
}
{
name: pattgen_pda0_tx
width: 1
type: output
- module_name: pattgen
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 46
}
{
name: pattgen_pcl0_tx
width: 1
type: output
- module_name: pattgen
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 47
}
{
name: pattgen_pda1_tx
width: 1
type: output
- module_name: pattgen
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 48
}
{
name: pattgen_pcl1_tx
width: 1
type: output
- module_name: pattgen
- }
- {
- name: spi_host1_sd
- width: 4
- type: inout
- module_name: spi_host1
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 49
}
{
name: spi_host1_sck
width: 1
type: output
- module_name: spi_host1
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 50
}
{
name: spi_host1_csb
width: 1
type: output
- module_name: spi_host1
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 51
}
{
name: flash_ctrl_tdo
width: 1
type: output
- module_name: flash_ctrl
+ idx: -1
+ pad: ""
+ connection: muxed
+ glob_idx: 52
}
{
name: sensor_ctrl_aon_ast_debug_out
width: 10
type: output
- module_name: sensor_ctrl_aon
+ idx: 0
+ pad: ""
+ connection: muxed
+ glob_idx: 53
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 1
+ pad: ""
+ connection: muxed
+ glob_idx: 54
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 2
+ pad: ""
+ connection: muxed
+ glob_idx: 55
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 3
+ pad: ""
+ connection: muxed
+ glob_idx: 56
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 4
+ pad: ""
+ connection: muxed
+ glob_idx: 57
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 5
+ pad: ""
+ connection: muxed
+ glob_idx: 58
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 6
+ pad: ""
+ connection: muxed
+ glob_idx: 59
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 7
+ pad: ""
+ connection: muxed
+ glob_idx: 60
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 8
+ pad: ""
+ connection: muxed
+ glob_idx: 61
+ }
+ {
+ name: sensor_ctrl_aon_ast_debug_out
+ width: 10
+ type: output
+ idx: 9
+ pad: ""
+ connection: muxed
+ glob_idx: 62
}
]
+ io_counts:
+ {
+ dedicated:
+ {
+ inouts: 11
+ inputs: 3
+ outputs: 7
+ pads: 22
+ }
+ muxed:
+ {
+ inouts: 42
+ inputs: 17
+ outputs: 21
+ pads: 44
+ }
+ }
}
- padctrl:
- {
- attr_default:
- [
- STRONG
- ]
- pads:
- [
+ targets:
+ [
+ {
+ name: asic
+ pinout:
{
- name: ChA
- type: IO_33V
- count: 32
+ remove_pads: []
+ add_pads: []
}
+ pinmux:
{
- name: ChB
- type: IO_33V
- count: 4
- attr:
+ special_signals:
[
- KEEP
- WEAK
+ {
+ name: tap0
+ pad: IOC8
+ desc: TAP strap signal.
+ idx: 26
+ }
+ {
+ name: tap1
+ pad: IOC5
+ desc: TAP strap signal.
+ idx: 23
+ }
+ {
+ name: dft0
+ pad: IOC3
+ desc: DFT strap signal.
+ idx: 21
+ }
+ {
+ name: dft1
+ pad: IOC4
+ desc: DFT strap signal.
+ idx: 22
+ }
+ {
+ name: tck
+ pad: SPI_DEV_CLK
+ desc: JTAG tck signal, overlaid on SPI_DEV.
+ idx: 55
+ }
+ {
+ name: tms
+ pad: SPI_DEV_CS_L
+ desc: JTAG tms signal, overlaid on SPI_DEV.
+ idx: 56
+ }
+ {
+ name: trst_n
+ pad: IOC0
+ desc: JTAG trst_n signal, maps to MIO Pad 18.
+ idx: 18
+ }
+ {
+ name: tdi
+ pad: SPI_DEV_D0
+ desc: JTAG tdi signal, overlaid on SPI_DEV.
+ idx: 48
+ }
+ {
+ name: tdo
+ pad: SPI_DEV_D1
+ desc: JTAG tdo signal, overlaid on SPI_DEV.
+ idx: 49
+ }
]
}
+ }
+ {
+ name: nexysvideo
+ pinout:
{
- name: ChC
- type: IO_33V
- count: 4
- attr:
+ remove_pads:
[
- KEEP
- STRONG
+ CC1
+ CC2
+ IOC1
+ IOC2
+ IOC3
+ IOC4
+ IOC5
+ SPI_DEV_D2
+ SPI_DEV_D3
+ SPI_HOST_CLK
+ SPI_HOST_CS_L
+ SPI_HOST_D0
+ SPI_HOST_D1
+ SPI_HOST_D2
+ SPI_HOST_D3
+ FLASH_TEST_VOLT
+ FLASH_TEST_MODE0
+ FLASH_TEST_MODE1
+ FLASH_TEST_MODE2
+ FLASH_TEST_MODE3
+ IOR4
+ IOR5
+ IOR6
+ IOR7
+ IOR8
+ IOR9
+ IOR10
+ IOR11
+ IOR12
+ IOR13
+ ]
+ add_pads:
+ [
+ {
+ name: IO_CLK
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Extra clock input for FPGA target
+ }
+ {
+ name: IO_JSRST_N
+ type: InputStd
+ bank: VCC
+ connection: manual
+ desc: Dedicated JTAG system reset input
+ }
+ {
+ name: IO_USB_SENSE0
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB signal for FPGA target
+ }
+ {
+ name: IO_USB_DNPULLUP0
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB signal for FPGA target
+ }
+ {
+ name: IO_USB_DPPULLUP0
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB signal for FPGA target
+ }
+ {
+ name: IO_UPHY_DP_TX
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_DN_TX
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_DP_RX
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_DN_RX
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_D_RX
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_OE_N
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_SENSE
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
+ {
+ name: IO_UPHY_DPPULLUP
+ type: BidirStd
+ bank: VCC
+ connection: manual
+ desc: Manual USB UPHY signal for FPGA target
+ }
]
}
- ]
- }
+ pinmux:
+ {
+ special_signals:
+ [
+ {
+ name: tap0
+ pad: IOC2
+ desc: TAP strap signal, maps to a stubbed-off MIO.
+ idx: 20
+ }
+ {
+ name: tap1
+ pad: IOB10
+ desc: TAP strap signal, maps to MIO pad 16.
+ idx: 16
+ }
+ {
+ name: dft0
+ pad: IOC3
+ desc: DFT strap signal, maps to a stubbed-off MIO.
+ idx: 21
+ }
+ {
+ name: dft1
+ pad: IOC4
+ desc: DFT strap signal, maps to a stubbed-off MIO.
+ idx: 22
+ }
+ {
+ name: tck
+ pad: SPI_DEV_CLK
+ desc: JTAG tck signal, overlaid on SPI_DEV.
+ idx: 55
+ }
+ {
+ name: tms
+ pad: SPI_DEV_CS_L
+ desc: JTAG tms signal, overlaid on SPI_DEV.
+ idx: 56
+ }
+ {
+ name: trst_n
+ pad: IOC0
+ desc: JTAG trst_n signal, maps to MIO pad 18.
+ idx: 18
+ }
+ {
+ name: tdi
+ pad: SPI_DEV_D0
+ desc: JTAG tdi signal, overlaid on SPI_DEV.
+ idx: 48
+ }
+ {
+ name: tdo
+ pad: SPI_DEV_D1
+ desc: JTAG tdo signal, overlaid on SPI_DEV.
+ idx: 49
+ }
+ ]
+ }
+ }
+ ]
exported_clks:
{
ast:
diff --git a/hw/top_earlgrey/data/pins_nexysvideo.xdc b/hw/top_earlgrey/data/pins_nexysvideo.xdc
index bad69d1..2cb510e 100644
--- a/hw/top_earlgrey/data/pins_nexysvideo.xdc
+++ b/hw/top_earlgrey/data/pins_nexysvideo.xdc
@@ -28,14 +28,14 @@
## LEDs
-set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { IO_GP8 }]; #IO_L15P_T2_DQS_13 Sch=led[0]
-set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { IO_GP9 }]; #IO_L15N_T2_DQS_13 Sch=led[1]
-set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { IO_GP10 }]; #IO_L17P_T2_13 Sch=led[2]
-set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { IO_GP11 }]; #IO_L17N_T2_13 Sch=led[3]
-set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { IO_GP12 }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
-set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { IO_GP13 }]; #IO_L16N_T2_13 Sch=led[5]
-set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { IO_GP14 }]; #IO_L16P_T2_13 Sch=led[6]
-set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { IO_GP15 }]; #IO_L5P_T0_13 Sch=led[7]
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { IOB2 }]; #IO_L15P_T2_DQS_13 Sch=led[0]
+set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { IOB3 }]; #IO_L15N_T2_DQS_13 Sch=led[1]
+set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { IOB4 }]; #IO_L17P_T2_13 Sch=led[2]
+set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { IOB5 }]; #IO_L17N_T2_13 Sch=led[3]
+set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { IOB6 }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
+set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { IOB7 }]; #IO_L16N_T2_13 Sch=led[5]
+set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { IOB8 }]; #IO_L16P_T2_13 Sch=led[6]
+set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { IOB9 }]; #IO_L5P_T0_13 Sch=led[7]
## Buttons
@@ -44,18 +44,18 @@
#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L20P_T3_16 Sch=btnl
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L6P_T0_16 Sch=btnr
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_0_16 Sch=btnu
-set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { IO_RST_N }]; #IO_L12N_T1_MRCC_35 Sch=cpu_resetn
+set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { POR_N }]; #IO_L12N_T1_MRCC_35 Sch=cpu_resetn
## Switches
-set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS12 } [get_ports { IO_GP0 }]; #IO_L22P_T3_16 Sch=sw[0]
-set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { IO_GP1 }]; #IO_25_16 Sch=sw[1]
-set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS12 } [get_ports { IO_GP2 }]; #IO_L24P_T3_16 Sch=sw[2]
-set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { IO_GP3 }]; #IO_L24N_T3_16 Sch=sw[3]
-set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { IO_GP4 }]; #IO_L6P_T0_15 Sch=sw[4]
-set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { IO_GP5 }]; #IO_0_15 Sch=sw[5]
-set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { IO_GP6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
-set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS12 } [get_ports { IO_GP7 }]; #IO_25_15 Sch=sw[7]
+set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS12 } [get_ports { IOA0 }]; #IO_L22P_T3_16 Sch=sw[0]
+set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { IOA1 }]; #IO_25_16 Sch=sw[1]
+set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS12 } [get_ports { IOA2 }]; #IO_L24P_T3_16 Sch=sw[2]
+set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { IOA3 }]; #IO_L24N_T3_16 Sch=sw[3]
+set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { IOA4 }]; #IO_L6P_T0_15 Sch=sw[4]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { IOA5 }]; #IO_0_15 Sch=sw[5]
+set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { IOB0 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
+set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS12 } [get_ports { IOB1 }]; #IO_25_15 Sch=sw[7]
## OLED Display
@@ -115,19 +115,19 @@
## Pmod header JA
-set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { IO_GP24 }]; #IO_L10N_T1_D15_14 Sch=ja[1]
-set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { IO_GP25 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
-set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { IO_GP26 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
-set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { IO_GP27 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
-set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { IO_GP28 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
-set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { IO_GP29 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
-set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { IO_GP30 }]; #IO_L8P_T1_D11_14 Sch=ja[9]
-set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { IO_GP31 }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
+set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { IOC6 }]; #IO_L10N_T1_D15_14 Sch=ja[1]
+set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
+set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { IOC8 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
+set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
+set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
+set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
+set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { IOR0 }]; #IO_L8P_T1_D11_14 Sch=ja[9]
+set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { IOR1 }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
## Pmod header JB
-set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DP0 }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
-set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN0 }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
+set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_P }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
+set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_N }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DPPULLUP0 }]; #IO_L19P_T3_34 Sch=jb_p[2]
set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE0 }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DNPULLUP0 }]; #IO_L23P_T3_34 Sch=jb_p[4]
@@ -176,8 +176,8 @@
## UART
-set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { IO_UTX }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
-set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { IO_URX }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
+set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { IOR3 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
+set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { IOR2 }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
## Ethernet
@@ -206,14 +206,14 @@
## DPTI/DSPI
#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
-set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS0 }]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
-set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS1 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/sdi
-set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS2 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/sdo
-set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS3 }]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
-set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS4 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
-set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_DPS5 }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
-set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IO_DPS6 }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
-set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IO_DPS7 }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
+set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CLK }]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D0 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/sdi
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D1 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/sdo
+set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CS_L }]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
+set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { IOC0 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
+set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
+set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB10 }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
+set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB11 }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 9ae3f78..47322d4 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -997,77 +997,292 @@
}
],
- // ===== INTERRUPT CTRL =====================================================
+ // ===== PINMUX & PINOUT ======================================================
- // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
- // source. "sequential" is smaller but slower, "matrix" is larger but faster.
- // Choose depends on the criteria. Currently it is set to "matrix" to meet FPGA timing @ 50MHz
-
- // ===== ALERT HANDLER ======================================================
-
- // TODO: need to overhaul this datastructure.
- pinmux: {
-
- // Total number of Multiplexed I/O
- // All the input/outputs from IPs are muxed in pinmux, and it has # of I/O
- // talks to the outside of top_earlgrey.
- // This field will be replaced to the length of PAD if padctrl is defined
- num_mio: 44
-
- // Dedicated IO modules. The in/out ports of the modules below are connected
- // to TOP IO port through PADS directly. It bypasses PINMUX multiplexers
- dio_modules: [
- { name: "spi_device", pad: ["ChC[0..5]"] },
- { name: "spi_host0", pad: ["ChB[0..5]"] },
- { name: "usbdev", pad: ["ChA[0..8]"] },
- ],
-
- // Multiplexing IO modules. The in/out ports of the modules below are
- // connected through PINMUX, which gives controllability of the connection
- // between the modules and the IO PADS.
- // If `mio_modules` aren't defined, it uses all remaining modules from
- // module list except defined in `dio_modules`.
- mio_modules: ["gpio", "uart0", "uart1", "uart2", "uart3",
- "i2c0", "i2c1", "i2c2", "pattgen", "spi_host1",
- "flash_ctrl", "sensor_ctrl_aon"]
-
- // If any module isn't defined in above two lists, its inputs will be tied
- // to 0, and the output/OE signals will be floating (or connected to
- // unused signal). `rv_plic` is special module, shouldn't be defined here.
- nc_modules: ["rv_timer", "hmac"]
-
- // Number of wakeup detectors to instantiate, and bitwidth for the wakeup
- // counters. Note that all MIO pad inputs are connected to the wakeup detectors,
- // and there is no way to disable this. DIO inputs on the other hand are by
- // default not connected.
- // TODO: need to add mechanism to mark them as wakeup pins.
- num_wkup_detect: 8
- wkup_cnt_width: 8
-
- // Below fields are generated.
- // inputs: [
- // { name: "xxx", width: xx },
- // ]
- // outputs: [
- // { name: "xxx", width: xx },
- // ]
- // inouts: [
- // { name: "xxx", width: xx },
- // ]
- }
-
- // TODO: need to overhaul this datastructure.
- // PADS instantiation
- // Number of in/outs and the numer of PAD instances doesn't have to be
- // same. The number given below excludes clock/reset and other necessary
- // PADS but only defines GPIO pads.
- padctrl: {
- attr_default: ["STRONG"],
+ pinout: {
+ // IO power bank declaration.
+ // This list defines the IO bank power domains on the ASIC.
+ // Each individual pad must be in one of the declared power domains.
+ banks: ['VCC', 'AVCC', 'VIOA', 'VIOB'],
+ // Pad declaration.
+ // Each entry must have the following four keys:
+ //
+ // - name: Name of the pad (this will be exposed at the chiplevel).
+ //
+ // - type: Pad type (this maps to the pad types defined in prim_pad_wrapper_pkg.sv)
+ //
+ // - bank: Specifies in which of the IO power banks this pad lives.
+ //
+ // - connection: Can have either of the following values:
+ //
+ // 1) 'direct': This is a dedicated IO Pad that is directly connected to a peripheral.
+ //
+ // 2) 'manual': This is a dedicated IO signal that is not directly connected to a
+ // peripheral. It needs to be manually wired up in the template.
+ //
+ // 3) 'muxed': This is a muxed IO pad that will be connected to the pinmux.
+ //
+ // Optionally, each pad can also have a 'desc' field for further description.
pads: [
- { name: "ChA" type: "IO_33V", count: 32 }, // Accessing as ChA[0] .. ChA[31]
- { name: "ChB" type: "IO_33V", count: 4, attr: ["KEEP", "WEAK"]},
- { name: "ChC" type: "IO_33V", count: 4, attr: ["KEEP", "STRONG"]},
+ // TODO: this needs to be updated to the latest ASIC pinout.
+ // Dedicated
+ { name: 'POR_N' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'System reset'},
+ { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_CLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host clock'},
+ { name: 'SPI_HOST_CS_L' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host chip select'},
+ { name: 'SPI_DEV_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_CLK' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device clock'},
+ { name: 'SPI_DEV_CS_L' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device chip select'},
+ { name: 'USB_P' , type: 'BidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB P signal'},
+ { name: 'USB_N' , type: 'BidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB N signal'},
+ { name: 'CC1' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 1'},
+ { name: 'CC2' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 2'},
+ { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE2', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE3', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_VOLT' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'},
+ // IOA
+ { name: 'IOA0' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA1' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA2' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA3' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA4' , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA5' , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOB
+ { name: 'IOB0' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB1' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB2' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB3' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB4' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB5' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB6' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB7' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB8' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB9' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB10' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB11' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOC
+ { name: 'IOC0' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC1' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC2' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC3' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC4' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC5' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC6' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC7' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC8' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC9' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOR
+ { name: 'IOR0' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR1' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR2' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR3' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR4' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR5' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR6' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR7' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR8' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR9' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR13' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
]
}
+ pinmux: {
+ // Signal to pinmux/pad mapping.
+ // Each entry in the list below must have the following two mandatory keys:
+ //
+ // - instance: This is the comportable IO instance name where the IO signal comes from.
+ //
+ // - connection: This key is similar to the connection key in the pinout/pad configuration and
+ // can have either of the following values:
+ //
+ // 1) 'direct': This is a dedicated IO signal that is directly connected to a pad.
+ // Such an IO signal must also specify the 'port' and 'pad' keys
+ // (see further below).
+ //
+ // 2) 'manual': This is a dedicated IO signal that is not directly connected to a pad.
+ // It needs to be manually wired up in the template.
+ // Such an IO signal may have a 'port' key, but no 'pad' key.
+ //
+ // 3) 'muxed': This is a muxed IO signal that will be connected to the pinmux.
+ // Such an IO signal may have a 'port' key, but no 'pad' key.
+ //
+ // Depending on the connection type specified, each entry may have the following optional keys:
+ //
+ // - port: Name of the available IO signal of the instance.
+ // This is required for 'direct' connections, but optional for the others.
+ // Individual signals of a bus IO signal must be indexed with square brackets, e.g. mybus[1].
+ // Not specifying this key or setting it to an empty string acts as a wild card
+ // and includes all available IOs of this instance.
+ //
+ // - pad: Name of the pad the 'direct' connection should connect to.
+ // This is not required for 'muxed' and 'manual' connections.
+ //
+ // - desc: Optional description field.
+ signals: [
+ // SPI Host0
+ { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''},
+ { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L', desc: ''},
+ { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''},
+ // SPI Device
+ { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''},
+ { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''},
+ { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''},
+ { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''},
+ { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''},
+ { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''},
+ // USBDEV
+ { instance: 'usbdev', port: '', connection: 'manual', pad: '' , desc: ''},
+ // MIOs
+ { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart1", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart2", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart3", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2c0", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2c1", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "i2c2", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "pattgen", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ ],
+
+ // Number of wakeup detectors to instantiate, and bitwidth for the wakeup counters.
+ num_wkup_detect: 8
+ wkup_cnt_width: 8
+ }
+
+ // Implementation targets.
+ // This defines the configuration of the target-specific chip-levels to
+ // generate from the shared template. Each target uses the same base
+ // configuration for the pinmux and pinout as defined above, and the
+ // generated software constants for the pinmux DIF do not change among the
+ // implementation targets. However, in order to accommodate slight
+ // differences among the ASIC, FPGA emulation and simulation environments,
+ // it is possible to make very limited pinout changes below. In particular,
+ // it is possible to remove and tie-off specific pads, or add more 'manual'
+ // pads that need to be manually connected in the template. It is also possible
+ // to override the JTAG and strap locations indices, since the testing and DFT
+ // setups may differ among the targets.
+ targets: [
+ { name: 'asic',
+
+ // Pinout Changes.
+ pinout: {
+ // This is a list of pad names to remove from the base pinout defined
+ // above. Removed pads will be stubbed off such that their inputs
+ // signals are driven with zero. Output signals and output enables
+ // will be left unconnected. If no changes are needed, this list can
+ // be left empty.
+ remove_pads: [],
+
+ // This is a list of additional "manual" pads to add to the pinout.
+ // The pad entries have the same format as the pad entries in the pinout
+ // configuration above. However, the 'connection' key must always be set
+ // to 'manual' as it is not possible to connect these additional pads
+ // to the pinmux or peripherals.
+ add_pads: [],
+ },
+
+ pinmux: {
+ // Special signal positions. Each entry in the list below creates a
+ // target-specific pad position parameter in the chiplevel hierarchy
+ // that can be used to parameterize certain IPs like the pinmux or
+ // padring. This is mainly used to define the pad positions of special
+ // test and DFT signals such as the JTAG signals and the TAP and DFT
+ // straps. Straps in this context are special pads that get sampled at
+ // boot time during certain life cycle states in order to determine
+ // DFT modes and the TAP mux selection index (the JTAG signals can be
+ // muxed to either the lifecycle TAP, DFT TAP or RISC-V processor
+ // TAP). TODO: add more documentation to https://docs.opentitan.org/hw/ip/pinmux/doc/index.html
+ // Each entry must have the following two keys:
+ //
+ // - name: Basename for the SV parameter.
+ //
+ // - pad: The pad name that this special signal maps to. The generated
+ // parameter will be assigned the corresponding pad index.
+ //
+ // Each entry may have an optional 'desc' key for further description.
+ special_signals: [
+ // Straps
+ { name: 'tap0', pad: 'IOC8', desc: 'TAP strap signal.' },
+ { name: 'tap1', pad: 'IOC5', desc: 'TAP strap signal.' },
+ { name: 'dft0', pad: 'IOC3', desc: 'DFT strap signal.' },
+ { name: 'dft1', pad: 'IOC4', desc: 'DFT strap signal.' },
+ // JTAG
+ // TODO: this needs to be updated to the latest ASIC pinout.
+ { name: 'tck', pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.' },
+ { name: 'tms', pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.' },
+ { name: 'trst_n', pad: 'IOC0' , desc: 'JTAG trst_n signal, maps to MIO Pad 18.' },
+ { name: 'tdi', pad: 'SPI_DEV_D0' , desc: 'JTAG tdi signal, overlaid on SPI_DEV.' },
+ { name: 'tdo', pad: 'SPI_DEV_D1' , desc: 'JTAG tdo signal, overlaid on SPI_DEV.' },
+ ],
+ }
+ },
+ { name: 'nexysvideo',
+
+ pinout: {
+ remove_pads: [
+ 'CC1', 'CC2',
+ 'IOC1', 'IOC2','IOC3','IOC4','IOC5',
+ 'SPI_DEV_D2', 'SPI_DEV_D3'
+ 'SPI_HOST_CLK', 'SPI_HOST_CS_L',
+ 'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3',
+ 'FLASH_TEST_VOLT',
+ 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', 'FLASH_TEST_MODE2', 'FLASH_TEST_MODE3',
+ 'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
+ ],
+
+ add_pads: [
+ // Additional infrastucture pads
+ { name: 'IO_CLK', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
+ { name: 'IO_JSRST_N', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Dedicated JTAG system reset input'}
+ // Custom USB pads
+ { name: 'IO_USB_SENSE0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
+ { name: 'IO_USB_DNPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
+ { name: 'IO_USB_DPPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
+ { name: 'IO_UPHY_DP_TX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_DN_TX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_DP_RX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_DN_RX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_D_RX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_OE_N', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_SENSE', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ { name: 'IO_UPHY_DPPULLUP', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
+ ],
+ },
+
+ pinmux: {
+ special_signals: [
+ // Straps
+ { name: 'tap0', pad: 'IOC2' , desc: 'TAP strap signal, maps to a stubbed-off MIO.' },
+ { name: 'tap1', pad: 'IOB10', desc: 'TAP strap signal, maps to MIO pad 16.' },
+ { name: 'dft0', pad: 'IOC3' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
+ { name: 'dft1', pad: 'IOC4' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
+ // JTAG
+ { name: 'tck', pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.' },
+ { name: 'tms', pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.' },
+ { name: 'trst_n', pad: 'IOC0' , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
+ { name: 'tdi', pad: 'SPI_DEV_D0' , desc: 'JTAG tdi signal, overlaid on SPI_DEV.' },
+ { name: 'tdo', pad: 'SPI_DEV_D1' , desc: 'JTAG tdo signal, overlaid on SPI_DEV.' },
+ ],
+ }
+ }
+ ]
}
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index fe596a8..a369458 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -157,7 +157,10 @@
.USB_P(usb_dp0),
.USB_N(usb_dn0),
// FLASH
- .FLASH_TEST_MODE(tie_off[27:24]),
+ .FLASH_TEST_MODE0(tie_off[24]),
+ .FLASH_TEST_MODE1(tie_off[25]),
+ .FLASH_TEST_MODE2(tie_off[26]),
+ .FLASH_TEST_MODE3(tie_off[27]),
.FLASH_TEST_VOLT(tie_off[28])
);
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
index ed94b5e..748c657 100644
--- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -148,7 +148,7 @@
{ name: "AttrDw",
desc: "Pad attribute data width",
type: "int",
- default: "10",
+ default: "13",
local: "true"
},
{ name: "NMioPeriphIn",
@@ -187,42 +187,6 @@
default: "8",
local: "true"
},
- { name: "NUsbDevPads",
- desc: "Number of usbdev pins",
- type: "int",
- default: "9",
- local: "true"
- },
- { name: "NDioPadUsbDevStart",
- desc: "Start position for usbdev pins",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "UsbDpSel",
- desc: "index of usbdev_dp",
- type: "int",
- default: "1",
- local: "true"
- },
- { name: "UsbDnSel",
- desc: "index of usbdev_dn",
- type: "int",
- default: "0",
- local: "true"
- },
- { name: "UsbDpPullUpSel",
- desc: "index of usbdev_dp_pullup",
- type: "int",
- default: "6",
- local: "true"
- },
- { name: "UsbDnPullUpSel",
- desc: "index of usbdev_dn_pullup",
- type: "int",
- default: "5",
- local: "true"
- },
// Since the target-specific top-levels often have slightly
// different debug signal positions, we need a way to pass
// this info from the target specific top-level into the pinmux
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
index 99ddaf8..0ceff37 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -7,19 +7,13 @@
package pinmux_reg_pkg;
// Param list
- parameter int AttrDw = 10;
+ parameter int AttrDw = 13;
parameter int NMioPeriphIn = 59;
parameter int NMioPeriphOut = 63;
parameter int NMioPads = 44;
parameter int NDioPads = 21;
parameter int NWkupDetect = 8;
parameter int WkupCntWidth = 8;
- parameter int NUsbDevPads = 9;
- parameter int NDioPadUsbDevStart = 0;
- parameter int UsbDpSel = 1;
- parameter int UsbDnSel = 0;
- parameter int UsbDpPullUpSel = 6;
- parameter int UsbDnPullUpSel = 5;
// Address widths within the block
parameter int BlockAw = 12;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 381b51c..b91ffb7 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -44,10 +44,8 @@
output logic [20:0] dio_oe_o,
// pad attributes to padring
- output logic[pinmux_reg_pkg::NMioPads-1:0]
- [pinmux_reg_pkg::AttrDw-1:0] mio_attr_o,
- output logic[pinmux_reg_pkg::NDioPads-1:0]
- [pinmux_reg_pkg::AttrDw-1:0] dio_attr_o,
+ output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o,
+ output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o,
// Inter-module Signal External type
@@ -113,16 +111,17 @@
import tlul_pkg::*;
import top_pkg::*;
import tl_main_pkg::*;
+ import top_earlgrey_pkg::*;
// Compile-time random constants
import top_earlgrey_rnd_cnst_pkg::*;
// Signals
logic [58:0] mio_p2d;
logic [62:0] mio_d2p;
- logic [62:0] mio_d2p_en;
+ logic [62:0] mio_en_d2p;
logic [20:0] dio_p2d;
logic [20:0] dio_d2p;
- logic [20:0] dio_d2p_en;
+ logic [20:0] dio_en_d2p;
// uart0
logic cio_uart0_rx_p2d;
logic cio_uart0_tx_d2p;
@@ -1698,7 +1697,7 @@
.tl_o(pinmux_aon_tl_rsp),
.periph_to_mio_i (mio_d2p ),
- .periph_to_mio_oe_i (mio_d2p_en ),
+ .periph_to_mio_oe_i (mio_en_d2p ),
.mio_to_periph_o (mio_p2d ),
.mio_attr_o,
@@ -1707,7 +1706,7 @@
.mio_in_i,
.periph_to_dio_i (dio_d2p ),
- .periph_to_dio_oe_i (dio_d2p_en ),
+ .periph_to_dio_oe_i (dio_en_d2p ),
.dio_to_periph_o (dio_p2d ),
.dio_attr_o,
@@ -2576,141 +2575,267 @@
);
// Pinmux connections
- assign mio_d2p = {
- cio_sensor_ctrl_aon_ast_debug_out_d2p,
- cio_flash_ctrl_tdo_d2p,
- cio_spi_host1_csb_d2p,
- cio_spi_host1_sck_d2p,
- cio_spi_host1_sd_d2p,
- cio_pattgen_pcl1_tx_d2p,
- cio_pattgen_pda1_tx_d2p,
- cio_pattgen_pcl0_tx_d2p,
- cio_pattgen_pda0_tx_d2p,
- cio_i2c2_scl_d2p,
- cio_i2c2_sda_d2p,
- cio_i2c1_scl_d2p,
- cio_i2c1_sda_d2p,
- cio_i2c0_scl_d2p,
- cio_i2c0_sda_d2p,
- cio_uart3_tx_d2p,
- cio_uart2_tx_d2p,
- cio_uart1_tx_d2p,
- cio_uart0_tx_d2p,
- cio_gpio_gpio_d2p
- };
- assign mio_d2p_en = {
- cio_sensor_ctrl_aon_ast_debug_out_en_d2p,
- cio_flash_ctrl_tdo_en_d2p,
- cio_spi_host1_csb_en_d2p,
- cio_spi_host1_sck_en_d2p,
- cio_spi_host1_sd_en_d2p,
- cio_pattgen_pcl1_tx_en_d2p,
- cio_pattgen_pda1_tx_en_d2p,
- cio_pattgen_pcl0_tx_en_d2p,
- cio_pattgen_pda0_tx_en_d2p,
- cio_i2c2_scl_en_d2p,
- cio_i2c2_sda_en_d2p,
- cio_i2c1_scl_en_d2p,
- cio_i2c1_sda_en_d2p,
- cio_i2c0_scl_en_d2p,
- cio_i2c0_sda_en_d2p,
- cio_uart3_tx_en_d2p,
- cio_uart2_tx_en_d2p,
- cio_uart1_tx_en_d2p,
- cio_uart0_tx_en_d2p,
- cio_gpio_gpio_en_d2p
- };
- assign {
- cio_sensor_ctrl_aon_ast_debug_in_p2d,
- cio_flash_ctrl_tdi_p2d,
- cio_flash_ctrl_tms_p2d,
- cio_flash_ctrl_tck_p2d,
- cio_spi_host1_sd_p2d,
- cio_i2c2_scl_p2d,
- cio_i2c2_sda_p2d,
- cio_i2c1_scl_p2d,
- cio_i2c1_sda_p2d,
- cio_i2c0_scl_p2d,
- cio_i2c0_sda_p2d,
- cio_uart3_rx_p2d,
- cio_uart2_rx_p2d,
- cio_uart1_rx_p2d,
- cio_uart0_rx_p2d,
- cio_gpio_gpio_p2d
- } = mio_p2d;
+ // All muxed inputs
+ assign cio_gpio_gpio_p2d[0] = mio_p2d[MioInGpioGpio0];
+ assign cio_gpio_gpio_p2d[1] = mio_p2d[MioInGpioGpio1];
+ assign cio_gpio_gpio_p2d[2] = mio_p2d[MioInGpioGpio2];
+ assign cio_gpio_gpio_p2d[3] = mio_p2d[MioInGpioGpio3];
+ assign cio_gpio_gpio_p2d[4] = mio_p2d[MioInGpioGpio4];
+ assign cio_gpio_gpio_p2d[5] = mio_p2d[MioInGpioGpio5];
+ assign cio_gpio_gpio_p2d[6] = mio_p2d[MioInGpioGpio6];
+ assign cio_gpio_gpio_p2d[7] = mio_p2d[MioInGpioGpio7];
+ assign cio_gpio_gpio_p2d[8] = mio_p2d[MioInGpioGpio8];
+ assign cio_gpio_gpio_p2d[9] = mio_p2d[MioInGpioGpio9];
+ assign cio_gpio_gpio_p2d[10] = mio_p2d[MioInGpioGpio10];
+ assign cio_gpio_gpio_p2d[11] = mio_p2d[MioInGpioGpio11];
+ assign cio_gpio_gpio_p2d[12] = mio_p2d[MioInGpioGpio12];
+ assign cio_gpio_gpio_p2d[13] = mio_p2d[MioInGpioGpio13];
+ assign cio_gpio_gpio_p2d[14] = mio_p2d[MioInGpioGpio14];
+ assign cio_gpio_gpio_p2d[15] = mio_p2d[MioInGpioGpio15];
+ assign cio_gpio_gpio_p2d[16] = mio_p2d[MioInGpioGpio16];
+ assign cio_gpio_gpio_p2d[17] = mio_p2d[MioInGpioGpio17];
+ assign cio_gpio_gpio_p2d[18] = mio_p2d[MioInGpioGpio18];
+ assign cio_gpio_gpio_p2d[19] = mio_p2d[MioInGpioGpio19];
+ assign cio_gpio_gpio_p2d[20] = mio_p2d[MioInGpioGpio20];
+ assign cio_gpio_gpio_p2d[21] = mio_p2d[MioInGpioGpio21];
+ assign cio_gpio_gpio_p2d[22] = mio_p2d[MioInGpioGpio22];
+ assign cio_gpio_gpio_p2d[23] = mio_p2d[MioInGpioGpio23];
+ assign cio_gpio_gpio_p2d[24] = mio_p2d[MioInGpioGpio24];
+ assign cio_gpio_gpio_p2d[25] = mio_p2d[MioInGpioGpio25];
+ assign cio_gpio_gpio_p2d[26] = mio_p2d[MioInGpioGpio26];
+ assign cio_gpio_gpio_p2d[27] = mio_p2d[MioInGpioGpio27];
+ assign cio_gpio_gpio_p2d[28] = mio_p2d[MioInGpioGpio28];
+ assign cio_gpio_gpio_p2d[29] = mio_p2d[MioInGpioGpio29];
+ assign cio_gpio_gpio_p2d[30] = mio_p2d[MioInGpioGpio30];
+ assign cio_gpio_gpio_p2d[31] = mio_p2d[MioInGpioGpio31];
+ assign cio_i2c0_sda_p2d = mio_p2d[MioInI2c0Sda];
+ assign cio_i2c0_scl_p2d = mio_p2d[MioInI2c0Scl];
+ assign cio_i2c1_sda_p2d = mio_p2d[MioInI2c1Sda];
+ assign cio_i2c1_scl_p2d = mio_p2d[MioInI2c1Scl];
+ assign cio_i2c2_sda_p2d = mio_p2d[MioInI2c2Sda];
+ assign cio_i2c2_scl_p2d = mio_p2d[MioInI2c2Scl];
+ assign cio_spi_host1_sd_p2d[0] = mio_p2d[MioInSpiHost1Sd0];
+ assign cio_spi_host1_sd_p2d[1] = mio_p2d[MioInSpiHost1Sd1];
+ assign cio_spi_host1_sd_p2d[2] = mio_p2d[MioInSpiHost1Sd2];
+ assign cio_spi_host1_sd_p2d[3] = mio_p2d[MioInSpiHost1Sd3];
+ assign cio_uart0_rx_p2d = mio_p2d[MioInUart0Rx];
+ assign cio_uart1_rx_p2d = mio_p2d[MioInUart1Rx];
+ assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx];
+ assign cio_uart3_rx_p2d = mio_p2d[MioInUart3Rx];
+ assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck];
+ assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms];
+ assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[0] = mio_p2d[MioInSensorCtrlAonAstDebugIn0];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[1] = mio_p2d[MioInSensorCtrlAonAstDebugIn1];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[2] = mio_p2d[MioInSensorCtrlAonAstDebugIn2];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[3] = mio_p2d[MioInSensorCtrlAonAstDebugIn3];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[4] = mio_p2d[MioInSensorCtrlAonAstDebugIn4];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[5] = mio_p2d[MioInSensorCtrlAonAstDebugIn5];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[6] = mio_p2d[MioInSensorCtrlAonAstDebugIn6];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[7] = mio_p2d[MioInSensorCtrlAonAstDebugIn7];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[8] = mio_p2d[MioInSensorCtrlAonAstDebugIn8];
+ assign cio_sensor_ctrl_aon_ast_debug_in_p2d[9] = mio_p2d[MioInSensorCtrlAonAstDebugIn9];
- // Dedicated IO connections
- // Input-only DIOs have no d2p signals
- assign dio_d2p = {
- 1'b0, // DIO20: cio_spi_device_sck
- 1'b0, // DIO19: cio_spi_device_csb
- cio_spi_device_sd_d2p[3], // DIO18
- cio_spi_device_sd_d2p[2], // DIO17
- cio_spi_device_sd_d2p[1], // DIO16
- cio_spi_device_sd_d2p[0], // DIO15
- cio_spi_host0_sck_d2p, // DIO14
- cio_spi_host0_csb_d2p, // DIO13
- cio_spi_host0_sd_d2p[3], // DIO12
- cio_spi_host0_sd_d2p[2], // DIO11
- cio_spi_host0_sd_d2p[1], // DIO10
- cio_spi_host0_sd_d2p[0], // DIO9
- 1'b0, // DIO8: cio_usbdev_sense
- cio_usbdev_se0_d2p, // DIO7
- cio_usbdev_dp_pullup_d2p, // DIO6
- cio_usbdev_dn_pullup_d2p, // DIO5
- cio_usbdev_tx_mode_se_d2p, // DIO4
- cio_usbdev_suspend_d2p, // DIO3
- cio_usbdev_d_d2p, // DIO2
- cio_usbdev_dp_d2p, // DIO1
- cio_usbdev_dn_d2p // DIO0
- };
+ // All muxed outputs
+ assign mio_d2p[MioOutGpioGpio0] = cio_gpio_gpio_d2p[0];
+ assign mio_d2p[MioOutGpioGpio1] = cio_gpio_gpio_d2p[1];
+ assign mio_d2p[MioOutGpioGpio2] = cio_gpio_gpio_d2p[2];
+ assign mio_d2p[MioOutGpioGpio3] = cio_gpio_gpio_d2p[3];
+ assign mio_d2p[MioOutGpioGpio4] = cio_gpio_gpio_d2p[4];
+ assign mio_d2p[MioOutGpioGpio5] = cio_gpio_gpio_d2p[5];
+ assign mio_d2p[MioOutGpioGpio6] = cio_gpio_gpio_d2p[6];
+ assign mio_d2p[MioOutGpioGpio7] = cio_gpio_gpio_d2p[7];
+ assign mio_d2p[MioOutGpioGpio8] = cio_gpio_gpio_d2p[8];
+ assign mio_d2p[MioOutGpioGpio9] = cio_gpio_gpio_d2p[9];
+ assign mio_d2p[MioOutGpioGpio10] = cio_gpio_gpio_d2p[10];
+ assign mio_d2p[MioOutGpioGpio11] = cio_gpio_gpio_d2p[11];
+ assign mio_d2p[MioOutGpioGpio12] = cio_gpio_gpio_d2p[12];
+ assign mio_d2p[MioOutGpioGpio13] = cio_gpio_gpio_d2p[13];
+ assign mio_d2p[MioOutGpioGpio14] = cio_gpio_gpio_d2p[14];
+ assign mio_d2p[MioOutGpioGpio15] = cio_gpio_gpio_d2p[15];
+ assign mio_d2p[MioOutGpioGpio16] = cio_gpio_gpio_d2p[16];
+ assign mio_d2p[MioOutGpioGpio17] = cio_gpio_gpio_d2p[17];
+ assign mio_d2p[MioOutGpioGpio18] = cio_gpio_gpio_d2p[18];
+ assign mio_d2p[MioOutGpioGpio19] = cio_gpio_gpio_d2p[19];
+ assign mio_d2p[MioOutGpioGpio20] = cio_gpio_gpio_d2p[20];
+ assign mio_d2p[MioOutGpioGpio21] = cio_gpio_gpio_d2p[21];
+ assign mio_d2p[MioOutGpioGpio22] = cio_gpio_gpio_d2p[22];
+ assign mio_d2p[MioOutGpioGpio23] = cio_gpio_gpio_d2p[23];
+ assign mio_d2p[MioOutGpioGpio24] = cio_gpio_gpio_d2p[24];
+ assign mio_d2p[MioOutGpioGpio25] = cio_gpio_gpio_d2p[25];
+ assign mio_d2p[MioOutGpioGpio26] = cio_gpio_gpio_d2p[26];
+ assign mio_d2p[MioOutGpioGpio27] = cio_gpio_gpio_d2p[27];
+ assign mio_d2p[MioOutGpioGpio28] = cio_gpio_gpio_d2p[28];
+ assign mio_d2p[MioOutGpioGpio29] = cio_gpio_gpio_d2p[29];
+ assign mio_d2p[MioOutGpioGpio30] = cio_gpio_gpio_d2p[30];
+ assign mio_d2p[MioOutGpioGpio31] = cio_gpio_gpio_d2p[31];
+ assign mio_d2p[MioOutI2c0Sda] = cio_i2c0_sda_d2p;
+ assign mio_d2p[MioOutI2c0Scl] = cio_i2c0_scl_d2p;
+ assign mio_d2p[MioOutI2c1Sda] = cio_i2c1_sda_d2p;
+ assign mio_d2p[MioOutI2c1Scl] = cio_i2c1_scl_d2p;
+ assign mio_d2p[MioOutI2c2Sda] = cio_i2c2_sda_d2p;
+ assign mio_d2p[MioOutI2c2Scl] = cio_i2c2_scl_d2p;
+ assign mio_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_d2p[0];
+ assign mio_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_d2p[1];
+ assign mio_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_d2p[2];
+ assign mio_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_d2p[3];
+ assign mio_d2p[MioOutUart0Tx] = cio_uart0_tx_d2p;
+ assign mio_d2p[MioOutUart1Tx] = cio_uart1_tx_d2p;
+ assign mio_d2p[MioOutUart2Tx] = cio_uart2_tx_d2p;
+ assign mio_d2p[MioOutUart3Tx] = cio_uart3_tx_d2p;
+ assign mio_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_d2p;
+ assign mio_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_d2p;
+ assign mio_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_d2p;
+ assign mio_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_d2p;
+ assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p;
+ assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p;
+ assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p;
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_d2p[0];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_d2p[1];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_d2p[2];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut3] = cio_sensor_ctrl_aon_ast_debug_out_d2p[3];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut4] = cio_sensor_ctrl_aon_ast_debug_out_d2p[4];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut5] = cio_sensor_ctrl_aon_ast_debug_out_d2p[5];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut6] = cio_sensor_ctrl_aon_ast_debug_out_d2p[6];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut7] = cio_sensor_ctrl_aon_ast_debug_out_d2p[7];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut8] = cio_sensor_ctrl_aon_ast_debug_out_d2p[8];
+ assign mio_d2p[MioOutSensorCtrlAonAstDebugOut9] = cio_sensor_ctrl_aon_ast_debug_out_d2p[9];
- assign dio_d2p_en = {
- 1'b0, // DIO20: cio_spi_device_sck
- 1'b0, // DIO19: cio_spi_device_csb
- cio_spi_device_sd_en_d2p[3], // DIO18
- cio_spi_device_sd_en_d2p[2], // DIO17
- cio_spi_device_sd_en_d2p[1], // DIO16
- cio_spi_device_sd_en_d2p[0], // DIO15
- cio_spi_host0_sck_en_d2p, // DIO14
- cio_spi_host0_csb_en_d2p, // DIO13
- cio_spi_host0_sd_en_d2p[3], // DIO12
- cio_spi_host0_sd_en_d2p[2], // DIO11
- cio_spi_host0_sd_en_d2p[1], // DIO10
- cio_spi_host0_sd_en_d2p[0], // DIO9
- 1'b0, // DIO8: cio_usbdev_sense
- cio_usbdev_se0_en_d2p, // DIO7
- cio_usbdev_dp_pullup_en_d2p, // DIO6
- cio_usbdev_dn_pullup_en_d2p, // DIO5
- cio_usbdev_tx_mode_se_en_d2p, // DIO4
- cio_usbdev_suspend_en_d2p, // DIO3
- cio_usbdev_d_en_d2p, // DIO2
- cio_usbdev_dp_en_d2p, // DIO1
- cio_usbdev_dn_en_d2p // DIO0
- };
+ // All muxed output enables
+ assign mio_en_d2p[MioOutGpioGpio0] = cio_gpio_gpio_en_d2p[0];
+ assign mio_en_d2p[MioOutGpioGpio1] = cio_gpio_gpio_en_d2p[1];
+ assign mio_en_d2p[MioOutGpioGpio2] = cio_gpio_gpio_en_d2p[2];
+ assign mio_en_d2p[MioOutGpioGpio3] = cio_gpio_gpio_en_d2p[3];
+ assign mio_en_d2p[MioOutGpioGpio4] = cio_gpio_gpio_en_d2p[4];
+ assign mio_en_d2p[MioOutGpioGpio5] = cio_gpio_gpio_en_d2p[5];
+ assign mio_en_d2p[MioOutGpioGpio6] = cio_gpio_gpio_en_d2p[6];
+ assign mio_en_d2p[MioOutGpioGpio7] = cio_gpio_gpio_en_d2p[7];
+ assign mio_en_d2p[MioOutGpioGpio8] = cio_gpio_gpio_en_d2p[8];
+ assign mio_en_d2p[MioOutGpioGpio9] = cio_gpio_gpio_en_d2p[9];
+ assign mio_en_d2p[MioOutGpioGpio10] = cio_gpio_gpio_en_d2p[10];
+ assign mio_en_d2p[MioOutGpioGpio11] = cio_gpio_gpio_en_d2p[11];
+ assign mio_en_d2p[MioOutGpioGpio12] = cio_gpio_gpio_en_d2p[12];
+ assign mio_en_d2p[MioOutGpioGpio13] = cio_gpio_gpio_en_d2p[13];
+ assign mio_en_d2p[MioOutGpioGpio14] = cio_gpio_gpio_en_d2p[14];
+ assign mio_en_d2p[MioOutGpioGpio15] = cio_gpio_gpio_en_d2p[15];
+ assign mio_en_d2p[MioOutGpioGpio16] = cio_gpio_gpio_en_d2p[16];
+ assign mio_en_d2p[MioOutGpioGpio17] = cio_gpio_gpio_en_d2p[17];
+ assign mio_en_d2p[MioOutGpioGpio18] = cio_gpio_gpio_en_d2p[18];
+ assign mio_en_d2p[MioOutGpioGpio19] = cio_gpio_gpio_en_d2p[19];
+ assign mio_en_d2p[MioOutGpioGpio20] = cio_gpio_gpio_en_d2p[20];
+ assign mio_en_d2p[MioOutGpioGpio21] = cio_gpio_gpio_en_d2p[21];
+ assign mio_en_d2p[MioOutGpioGpio22] = cio_gpio_gpio_en_d2p[22];
+ assign mio_en_d2p[MioOutGpioGpio23] = cio_gpio_gpio_en_d2p[23];
+ assign mio_en_d2p[MioOutGpioGpio24] = cio_gpio_gpio_en_d2p[24];
+ assign mio_en_d2p[MioOutGpioGpio25] = cio_gpio_gpio_en_d2p[25];
+ assign mio_en_d2p[MioOutGpioGpio26] = cio_gpio_gpio_en_d2p[26];
+ assign mio_en_d2p[MioOutGpioGpio27] = cio_gpio_gpio_en_d2p[27];
+ assign mio_en_d2p[MioOutGpioGpio28] = cio_gpio_gpio_en_d2p[28];
+ assign mio_en_d2p[MioOutGpioGpio29] = cio_gpio_gpio_en_d2p[29];
+ assign mio_en_d2p[MioOutGpioGpio30] = cio_gpio_gpio_en_d2p[30];
+ assign mio_en_d2p[MioOutGpioGpio31] = cio_gpio_gpio_en_d2p[31];
+ assign mio_en_d2p[MioOutI2c0Sda] = cio_i2c0_sda_en_d2p;
+ assign mio_en_d2p[MioOutI2c0Scl] = cio_i2c0_scl_en_d2p;
+ assign mio_en_d2p[MioOutI2c1Sda] = cio_i2c1_sda_en_d2p;
+ assign mio_en_d2p[MioOutI2c1Scl] = cio_i2c1_scl_en_d2p;
+ assign mio_en_d2p[MioOutI2c2Sda] = cio_i2c2_sda_en_d2p;
+ assign mio_en_d2p[MioOutI2c2Scl] = cio_i2c2_scl_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_en_d2p[0];
+ assign mio_en_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_en_d2p[1];
+ assign mio_en_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_en_d2p[2];
+ assign mio_en_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_en_d2p[3];
+ assign mio_en_d2p[MioOutUart0Tx] = cio_uart0_tx_en_d2p;
+ assign mio_en_d2p[MioOutUart1Tx] = cio_uart1_tx_en_d2p;
+ assign mio_en_d2p[MioOutUart2Tx] = cio_uart2_tx_en_d2p;
+ assign mio_en_d2p[MioOutUart3Tx] = cio_uart3_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_en_d2p;
+ assign mio_en_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p;
+ assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p;
+ assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p;
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[0];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[1];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[2];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut3] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[3];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut4] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[4];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut5] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[5];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut6] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[6];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut7] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[7];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut8] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[8];
+ assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut9] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[9];
- // Output-only DIOs have no p2d signal
- assign cio_spi_device_sck_p2d = dio_p2d[20]; // DIO20
- assign cio_spi_device_csb_p2d = dio_p2d[19]; // DIO19
- assign cio_spi_device_sd_p2d[3] = dio_p2d[18]; // DIO18
- assign cio_spi_device_sd_p2d[2] = dio_p2d[17]; // DIO17
- assign cio_spi_device_sd_p2d[1] = dio_p2d[16]; // DIO16
- assign cio_spi_device_sd_p2d[0] = dio_p2d[15]; // DIO15
- // DIO14: cio_spi_host0_sck // DIO14
- // DIO13: cio_spi_host0_csb // DIO13
- assign cio_spi_host0_sd_p2d[3] = dio_p2d[12]; // DIO12
- assign cio_spi_host0_sd_p2d[2] = dio_p2d[11]; // DIO11
- assign cio_spi_host0_sd_p2d[1] = dio_p2d[10]; // DIO10
- assign cio_spi_host0_sd_p2d[0] = dio_p2d[9]; // DIO9
- assign cio_usbdev_sense_p2d = dio_p2d[8]; // DIO8
- // DIO7: cio_usbdev_se0 // DIO7
- // DIO6: cio_usbdev_dp_pullup // DIO6
- // DIO5: cio_usbdev_dn_pullup // DIO5
- // DIO4: cio_usbdev_tx_mode_se // DIO4
- // DIO3: cio_usbdev_suspend // DIO3
- assign cio_usbdev_d_p2d = dio_p2d[2]; // DIO2
- assign cio_usbdev_dp_p2d = dio_p2d[1]; // DIO1
- assign cio_usbdev_dn_p2d = dio_p2d[0]; // DIO0
+ // All dedicated inputs
+ logic [20:0] unused_dio_p2d;
+ assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0];
+ assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1];
+ assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2];
+ assign cio_spi_host0_sd_p2d[3] = dio_p2d[DioSpiHost0Sd3];
+ assign cio_spi_device_sd_p2d[0] = dio_p2d[DioSpiDeviceSd0];
+ assign cio_spi_device_sd_p2d[1] = dio_p2d[DioSpiDeviceSd1];
+ assign cio_spi_device_sd_p2d[2] = dio_p2d[DioSpiDeviceSd2];
+ assign cio_spi_device_sd_p2d[3] = dio_p2d[DioSpiDeviceSd3];
+ assign cio_usbdev_d_p2d = dio_p2d[DioUsbdevD];
+ assign cio_usbdev_dp_p2d = dio_p2d[DioUsbdevDp];
+ assign cio_usbdev_dn_p2d = dio_p2d[DioUsbdevDn];
+ assign cio_spi_device_sck_p2d = dio_p2d[DioSpiDeviceSck];
+ assign cio_spi_device_csb_p2d = dio_p2d[DioSpiDeviceCsb];
+ assign cio_usbdev_sense_p2d = dio_p2d[DioUsbdevSense];
+ assign unused_dio_p2d[0] = dio_p2d[DioSpiHost0Sck];
+ assign unused_dio_p2d[1] = dio_p2d[DioSpiHost0Csb];
+ assign unused_dio_p2d[2] = dio_p2d[DioUsbdevSe0];
+ assign unused_dio_p2d[3] = dio_p2d[DioUsbdevDpPullup];
+ assign unused_dio_p2d[4] = dio_p2d[DioUsbdevDnPullup];
+ assign unused_dio_p2d[5] = dio_p2d[DioUsbdevTxModeSe];
+ assign unused_dio_p2d[6] = dio_p2d[DioUsbdevSuspend];
+
+ // All dedicated outputs
+ assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0];
+ assign dio_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_d2p[1];
+ assign dio_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_d2p[2];
+ assign dio_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_d2p[3];
+ assign dio_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_d2p[0];
+ assign dio_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_d2p[1];
+ assign dio_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_d2p[2];
+ assign dio_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_d2p[3];
+ assign dio_d2p[DioUsbdevD] = cio_usbdev_d_d2p;
+ assign dio_d2p[DioUsbdevDp] = cio_usbdev_dp_d2p;
+ assign dio_d2p[DioUsbdevDn] = cio_usbdev_dn_d2p;
+ assign dio_d2p[DioSpiDeviceSck] = 1'b0;
+ assign dio_d2p[DioSpiDeviceCsb] = 1'b0;
+ assign dio_d2p[DioUsbdevSense] = 1'b0;
+ assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p;
+ assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p;
+ assign dio_d2p[DioUsbdevSe0] = cio_usbdev_se0_d2p;
+ assign dio_d2p[DioUsbdevDpPullup] = cio_usbdev_dp_pullup_d2p;
+ assign dio_d2p[DioUsbdevDnPullup] = cio_usbdev_dn_pullup_d2p;
+ assign dio_d2p[DioUsbdevTxModeSe] = cio_usbdev_tx_mode_se_d2p;
+ assign dio_d2p[DioUsbdevSuspend] = cio_usbdev_suspend_d2p;
+
+ // All dedicated output enables
+ assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0];
+ assign dio_en_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_en_d2p[1];
+ assign dio_en_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_en_d2p[2];
+ assign dio_en_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_en_d2p[3];
+ assign dio_en_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_en_d2p[0];
+ assign dio_en_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_en_d2p[1];
+ assign dio_en_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_en_d2p[2];
+ assign dio_en_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_en_d2p[3];
+ assign dio_en_d2p[DioUsbdevD] = cio_usbdev_d_en_d2p;
+ assign dio_en_d2p[DioUsbdevDp] = cio_usbdev_dp_en_d2p;
+ assign dio_en_d2p[DioUsbdevDn] = cio_usbdev_dn_en_d2p;
+ assign dio_en_d2p[DioSpiDeviceSck] = 1'b0;
+ assign dio_en_d2p[DioSpiDeviceCsb] = 1'b0;
+ assign dio_en_d2p[DioUsbdevSense] = 1'b0;
+ assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p;
+ assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p;
+ assign dio_en_d2p[DioUsbdevSe0] = cio_usbdev_se0_en_d2p;
+ assign dio_en_d2p[DioUsbdevDpPullup] = cio_usbdev_dp_pullup_en_d2p;
+ assign dio_en_d2p[DioUsbdevDnPullup] = cio_usbdev_dn_pullup_en_d2p;
+ assign dio_en_d2p[DioUsbdevTxModeSe] = cio_usbdev_tx_mode_se_en_d2p;
+ assign dio_en_d2p[DioUsbdevSuspend] = cio_usbdev_suspend_en_d2p;
+
// make sure scanmode_i is never X (including during reset)
`ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_main_i, 0)
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_asic.sv
new file mode 100644
index 0000000..33ca562
--- /dev/null
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_asic.sv
@@ -0,0 +1,1192 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \
+// -o hw/top_earlgrey/ \
+// --rnd_cnst_seed 4881560218908238235
+
+// TODO: change the naming to chip_earlgrey_asic
+module top_earlgrey_asic (
+ // Dedicated Pads
+ inout POR_N, // Manual Pad
+ inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd
+ inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck
+ inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb
+ inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck
+ inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb
+ inout USB_P, // Manual Pad
+ inout USB_N, // Manual Pad
+ inout CC1, // Manual Pad
+ inout CC2, // Manual Pad
+ inout FLASH_TEST_MODE0, // Manual Pad
+ inout FLASH_TEST_MODE1, // Manual Pad
+ inout FLASH_TEST_MODE2, // Manual Pad
+ inout FLASH_TEST_MODE3, // Manual Pad
+ inout FLASH_TEST_VOLT, // Manual Pad
+
+ // Muxed Pads
+ inout IOA0, // MIO Pad 0
+ inout IOA1, // MIO Pad 1
+ inout IOA2, // MIO Pad 2
+ inout IOA3, // MIO Pad 3
+ inout IOA4, // MIO Pad 4
+ inout IOA5, // MIO Pad 5
+ inout IOB0, // MIO Pad 6
+ inout IOB1, // MIO Pad 7
+ inout IOB2, // MIO Pad 8
+ inout IOB3, // MIO Pad 9
+ inout IOB4, // MIO Pad 10
+ inout IOB5, // MIO Pad 11
+ inout IOB6, // MIO Pad 12
+ inout IOB7, // MIO Pad 13
+ inout IOB8, // MIO Pad 14
+ inout IOB9, // MIO Pad 15
+ inout IOB10, // MIO Pad 16
+ inout IOB11, // MIO Pad 17
+ inout IOC0, // MIO Pad 18
+ inout IOC1, // MIO Pad 19
+ inout IOC2, // MIO Pad 20
+ inout IOC3, // MIO Pad 21
+ inout IOC4, // MIO Pad 22
+ inout IOC5, // MIO Pad 23
+ inout IOC6, // MIO Pad 24
+ inout IOC7, // MIO Pad 25
+ inout IOC8, // MIO Pad 26
+ inout IOC9, // MIO Pad 27
+ inout IOC10, // MIO Pad 28
+ inout IOC11, // MIO Pad 29
+ inout IOR0, // MIO Pad 30
+ inout IOR1, // MIO Pad 31
+ inout IOR2, // MIO Pad 32
+ inout IOR3, // MIO Pad 33
+ inout IOR4, // MIO Pad 34
+ inout IOR5, // MIO Pad 35
+ inout IOR6, // MIO Pad 36
+ inout IOR7, // MIO Pad 37
+ inout IOR8, // MIO Pad 38
+ inout IOR9, // MIO Pad 39
+ inout IOR10, // MIO Pad 40
+ inout IOR11, // MIO Pad 41
+ inout IOR12, // MIO Pad 42
+ inout IOR13 // MIO Pad 43
+);
+
+ import top_earlgrey_pkg::*;
+ import prim_pad_wrapper_pkg::*;
+
+ ////////////////////////////
+ // Special Signal Indices //
+ ////////////////////////////
+
+ parameter int Tap0PadIdx = 26;
+ parameter int Tap1PadIdx = 23;
+ parameter int Dft0PadIdx = 21;
+ parameter int Dft1PadIdx = 22;
+ parameter int TckPadIdx = 55;
+ parameter int TmsPadIdx = 56;
+ parameter int TrstNPadIdx = 18;
+ parameter int TdiPadIdx = 48;
+ parameter int TdoPadIdx = 49;
+
+ // TODO: this is temporary and will be removed in the future.
+ // This specifies the tie-off values of the muxed MIO/DIOs
+ // when the JTAG is active. SPI CSB is active low.
+ localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << (
+ pinmux_reg_pkg::NMioPads + DioSpiDeviceCsb));
+
+ // DFT and Debug signal positions in the pinout.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ const_sampling: 1'b1,
+ tie_offs: TieOffValues, // TODO: can we remove this and just set it to zero?
+ tck_idx: TckPadIdx,
+ tms_idx: TmsPadIdx,
+ trst_idx: TrstNPadIdx,
+ tdi_idx: TdiPadIdx,
+ tdo_idx: TdoPadIdx,
+ tap_strap0_idx: Tap0PadIdx,
+ tap_strap1_idx: Tap1PadIdx,
+ dft_strap0_idx: Dft0PadIdx,
+ dft_strap1_idx: Dft1PadIdx,
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevDp,
+ usb_dn_idx: DioUsbdevDn,
+ usb_dp_pullup_idx: DioUsbdevDpPullup,
+ usb_dn_pullup_idx: DioUsbdevDnPullup
+ };
+
+ ////////////////////////
+ // Signal definitions //
+ ////////////////////////
+
+ pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+ pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+
+ // Manual pads
+ logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
+ logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
+ logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
+ logic manual_in_cc1, manual_out_cc1, manual_oe_cc1;
+ logic manual_in_cc2, manual_out_cc2, manual_oe_cc2;
+ logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0;
+ logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1;
+ logic manual_in_flash_test_mode2, manual_out_flash_test_mode2, manual_oe_flash_test_mode2;
+ logic manual_in_flash_test_mode3, manual_out_flash_test_mode3, manual_oe_flash_test_mode3;
+ logic manual_in_flash_test_volt, manual_out_flash_test_volt, manual_oe_flash_test_volt;
+
+ pad_attr_t manual_attr_por_n;
+ pad_attr_t manual_attr_usb_p;
+ pad_attr_t manual_attr_usb_n;
+ pad_attr_t manual_attr_cc1;
+ pad_attr_t manual_attr_cc2;
+ pad_attr_t manual_attr_flash_test_mode0;
+ pad_attr_t manual_attr_flash_test_mode1;
+ pad_attr_t manual_attr_flash_test_mode2;
+ pad_attr_t manual_attr_flash_test_mode3;
+ pad_attr_t manual_attr_flash_test_volt;
+
+
+ //////////////////////
+ // Padring Instance //
+ //////////////////////
+
+ // AST signals needed in padring
+ ast_pkg::ast_clks_t ast_base_clks;
+ logic scan_rst_n;
+ lc_ctrl_pkg::lc_tx_t scanmode;
+
+ padring #(
+ // Padring specific counts may differ from pinmux config due
+ // to custom, stubbed or added pads.
+ .NDioPads(22),
+ .NMioPads(44),
+ // TODO: need to add ScanRole parameters
+ .PhysicalPads(1),
+ .NIoBanks(IoBankCount),
+ .DioPadBank ({
+ IoBankVcc, // FLASH_TEST_VOLT
+ IoBankVcc, // FLASH_TEST_MODE3
+ IoBankVcc, // FLASH_TEST_MODE2
+ IoBankVcc, // FLASH_TEST_MODE1
+ IoBankVcc, // FLASH_TEST_MODE0
+ IoBankAvcc, // CC2
+ IoBankAvcc, // CC1
+ IoBankVcc, // USB_N
+ IoBankVcc, // USB_P
+ IoBankVioa, // SPI_DEV_CS_L
+ IoBankVioa, // SPI_DEV_CLK
+ IoBankVioa, // SPI_DEV_D3
+ IoBankVioa, // SPI_DEV_D2
+ IoBankVioa, // SPI_DEV_D1
+ IoBankVioa, // SPI_DEV_D0
+ IoBankVioa, // SPI_HOST_CS_L
+ IoBankVioa, // SPI_HOST_CLK
+ IoBankVioa, // SPI_HOST_D3
+ IoBankVioa, // SPI_HOST_D2
+ IoBankVioa, // SPI_HOST_D1
+ IoBankVioa, // SPI_HOST_D0
+ IoBankVcc // POR_N
+ }),
+ .MioPadBank ({
+ IoBankVcc, // IOR13
+ IoBankVcc, // IOR12
+ IoBankVcc, // IOR11
+ IoBankVcc, // IOR10
+ IoBankVcc, // IOR9
+ IoBankVcc, // IOR8
+ IoBankVcc, // IOR7
+ IoBankVcc, // IOR6
+ IoBankVcc, // IOR5
+ IoBankVcc, // IOR4
+ IoBankVcc, // IOR3
+ IoBankVcc, // IOR2
+ IoBankVcc, // IOR1
+ IoBankVcc, // IOR0
+ IoBankVcc, // IOC11
+ IoBankVcc, // IOC10
+ IoBankVcc, // IOC9
+ IoBankVcc, // IOC8
+ IoBankVcc, // IOC7
+ IoBankVcc, // IOC6
+ IoBankVcc, // IOC5
+ IoBankVcc, // IOC4
+ IoBankVcc, // IOC3
+ IoBankVcc, // IOC2
+ IoBankVcc, // IOC1
+ IoBankVcc, // IOC0
+ IoBankViob, // IOB11
+ IoBankViob, // IOB10
+ IoBankViob, // IOB9
+ IoBankViob, // IOB8
+ IoBankViob, // IOB7
+ IoBankViob, // IOB6
+ IoBankViob, // IOB5
+ IoBankViob, // IOB4
+ IoBankViob, // IOB3
+ IoBankViob, // IOB2
+ IoBankViob, // IOB1
+ IoBankViob, // IOB0
+ IoBankVioa, // IOA5
+ IoBankVioa, // IOA4
+ IoBankVioa, // IOA3
+ IoBankVioa, // IOA2
+ IoBankVioa, // IOA1
+ IoBankVioa // IOA0
+ }),
+ .DioPadType ({
+ InputStd, // FLASH_TEST_VOLT
+ InputStd, // FLASH_TEST_MODE3
+ InputStd, // FLASH_TEST_MODE2
+ InputStd, // FLASH_TEST_MODE1
+ InputStd, // FLASH_TEST_MODE0
+ InputStd, // CC2
+ InputStd, // CC1
+ BidirTol, // USB_N
+ BidirTol, // USB_P
+ InputStd, // SPI_DEV_CS_L
+ InputStd, // SPI_DEV_CLK
+ BidirStd, // SPI_DEV_D3
+ BidirStd, // SPI_DEV_D2
+ BidirStd, // SPI_DEV_D1
+ BidirStd, // SPI_DEV_D0
+ BidirStd, // SPI_HOST_CS_L
+ BidirStd, // SPI_HOST_CLK
+ BidirStd, // SPI_HOST_D3
+ BidirStd, // SPI_HOST_D2
+ BidirStd, // SPI_HOST_D1
+ BidirStd, // SPI_HOST_D0
+ InputStd // POR_N
+ }),
+ .MioPadType ({
+ BidirOd, // IOR13
+ BidirOd, // IOR12
+ BidirOd, // IOR11
+ BidirOd, // IOR10
+ BidirOd, // IOR9
+ BidirOd, // IOR8
+ InputStd, // IOR7
+ InputStd, // IOR6
+ InputStd, // IOR5
+ InputStd, // IOR4
+ InputStd, // IOR3
+ InputStd, // IOR2
+ InputStd, // IOR1
+ InputStd, // IOR0
+ BidirOd, // IOC11
+ BidirOd, // IOC10
+ BidirOd, // IOC9
+ BidirOd, // IOC8
+ InputStd, // IOC7
+ InputStd, // IOC6
+ InputStd, // IOC5
+ InputStd, // IOC4
+ InputStd, // IOC3
+ InputStd, // IOC2
+ InputStd, // IOC1
+ InputStd, // IOC0
+ InputStd, // IOB11
+ InputStd, // IOB10
+ BidirOd, // IOB9
+ BidirOd, // IOB8
+ InputStd, // IOB7
+ InputStd, // IOB6
+ InputStd, // IOB5
+ InputStd, // IOB4
+ InputStd, // IOB3
+ InputStd, // IOB2
+ InputStd, // IOB1
+ InputStd, // IOB0
+ BidirOd, // IOA5
+ BidirOd, // IOA4
+ InputStd, // IOA3
+ InputStd, // IOA2
+ InputStd, // IOA1
+ InputStd // IOA0
+ })
+ ) u_padring (
+ // This is only used for scan and DFT purposes
+ .clk_scan_i ( ast_base_clks.clk_sys ),
+ .scanmode_i ( scanmode ),
+ // TODO: wire this up to AST. Hint: the top_<name>_pkg contains
+ // generated parameters that can be used to index pads by name.
+ .dio_in_raw_o ( ),
+ .mio_in_raw_o ( ),
+ // Chip IOs
+ .dio_pad_io ({
+ FLASH_TEST_VOLT,
+ FLASH_TEST_MODE3,
+ FLASH_TEST_MODE2,
+ FLASH_TEST_MODE1,
+ FLASH_TEST_MODE0,
+ CC2,
+ CC1,
+ USB_N,
+ USB_P,
+ SPI_DEV_CS_L,
+ SPI_DEV_CLK,
+ SPI_DEV_D3,
+ SPI_DEV_D2,
+ SPI_DEV_D1,
+ SPI_DEV_D0,
+ SPI_HOST_CS_L,
+ SPI_HOST_CLK,
+ SPI_HOST_D3,
+ SPI_HOST_D2,
+ SPI_HOST_D1,
+ SPI_HOST_D0,
+ POR_N
+ }),
+
+ .mio_pad_io ({
+ IOR13,
+ IOR12,
+ IOR11,
+ IOR10,
+ IOR9,
+ IOR8,
+ IOR7,
+ IOR6,
+ IOR5,
+ IOR4,
+ IOR3,
+ IOR2,
+ IOR1,
+ IOR0,
+ IOC11,
+ IOC10,
+ IOC9,
+ IOC8,
+ IOC7,
+ IOC6,
+ IOC5,
+ IOC4,
+ IOC3,
+ IOC2,
+ IOC1,
+ IOC0,
+ IOB11,
+ IOB10,
+ IOB9,
+ IOB8,
+ IOB7,
+ IOB6,
+ IOB5,
+ IOB4,
+ IOB3,
+ IOB2,
+ IOB1,
+ IOB0,
+ IOA5,
+ IOA4,
+ IOA3,
+ IOA2,
+ IOA1,
+ IOA0
+ }),
+
+ // Core-facing
+ .dio_in_o ({
+ manual_in_flash_test_volt,
+ manual_in_flash_test_mode3,
+ manual_in_flash_test_mode2,
+ manual_in_flash_test_mode1,
+ manual_in_flash_test_mode0,
+ manual_in_cc2,
+ manual_in_cc1,
+ manual_in_usb_n,
+ manual_in_usb_p,
+ dio_in[DioSpiDeviceCsb],
+ dio_in[DioSpiDeviceSck],
+ dio_in[DioSpiDeviceSd3],
+ dio_in[DioSpiDeviceSd2],
+ dio_in[DioSpiDeviceSd1],
+ dio_in[DioSpiDeviceSd0],
+ dio_in[DioSpiHost0Csb],
+ dio_in[DioSpiHost0Sck],
+ dio_in[DioSpiHost0Sd3],
+ dio_in[DioSpiHost0Sd2],
+ dio_in[DioSpiHost0Sd1],
+ dio_in[DioSpiHost0Sd0],
+ manual_in_por_n
+ }),
+ .dio_out_i ({
+ manual_out_flash_test_volt,
+ manual_out_flash_test_mode3,
+ manual_out_flash_test_mode2,
+ manual_out_flash_test_mode1,
+ manual_out_flash_test_mode0,
+ manual_out_cc2,
+ manual_out_cc1,
+ manual_out_usb_n,
+ manual_out_usb_p,
+ dio_out[DioSpiDeviceCsb],
+ dio_out[DioSpiDeviceSck],
+ dio_out[DioSpiDeviceSd3],
+ dio_out[DioSpiDeviceSd2],
+ dio_out[DioSpiDeviceSd1],
+ dio_out[DioSpiDeviceSd0],
+ dio_out[DioSpiHost0Csb],
+ dio_out[DioSpiHost0Sck],
+ dio_out[DioSpiHost0Sd3],
+ dio_out[DioSpiHost0Sd2],
+ dio_out[DioSpiHost0Sd1],
+ dio_out[DioSpiHost0Sd0],
+ manual_out_por_n
+ }),
+ .dio_oe_i ({
+ manual_oe_flash_test_volt,
+ manual_oe_flash_test_mode3,
+ manual_oe_flash_test_mode2,
+ manual_oe_flash_test_mode1,
+ manual_oe_flash_test_mode0,
+ manual_oe_cc2,
+ manual_oe_cc1,
+ manual_oe_usb_n,
+ manual_oe_usb_p,
+ dio_oe[DioSpiDeviceCsb],
+ dio_oe[DioSpiDeviceSck],
+ dio_oe[DioSpiDeviceSd3],
+ dio_oe[DioSpiDeviceSd2],
+ dio_oe[DioSpiDeviceSd1],
+ dio_oe[DioSpiDeviceSd0],
+ dio_oe[DioSpiHost0Csb],
+ dio_oe[DioSpiHost0Sck],
+ dio_oe[DioSpiHost0Sd3],
+ dio_oe[DioSpiHost0Sd2],
+ dio_oe[DioSpiHost0Sd1],
+ dio_oe[DioSpiHost0Sd0],
+ manual_oe_por_n
+ }),
+ .dio_attr_i ({
+ manual_attr_flash_test_volt,
+ manual_attr_flash_test_mode3,
+ manual_attr_flash_test_mode2,
+ manual_attr_flash_test_mode1,
+ manual_attr_flash_test_mode0,
+ manual_attr_cc2,
+ manual_attr_cc1,
+ manual_attr_usb_n,
+ manual_attr_usb_p,
+ dio_attr[DioSpiDeviceCsb],
+ dio_attr[DioSpiDeviceSck],
+ dio_attr[DioSpiDeviceSd3],
+ dio_attr[DioSpiDeviceSd2],
+ dio_attr[DioSpiDeviceSd1],
+ dio_attr[DioSpiDeviceSd0],
+ dio_attr[DioSpiHost0Csb],
+ dio_attr[DioSpiHost0Sck],
+ dio_attr[DioSpiHost0Sd3],
+ dio_attr[DioSpiHost0Sd2],
+ dio_attr[DioSpiHost0Sd1],
+ dio_attr[DioSpiHost0Sd0],
+ manual_attr_por_n
+ }),
+
+ .mio_in_o ({
+ mio_in[43],
+ mio_in[42],
+ mio_in[41],
+ mio_in[40],
+ mio_in[39],
+ mio_in[38],
+ mio_in[37],
+ mio_in[36],
+ mio_in[35],
+ mio_in[34],
+ mio_in[33],
+ mio_in[32],
+ mio_in[31],
+ mio_in[30],
+ mio_in[29],
+ mio_in[28],
+ mio_in[27],
+ mio_in[26],
+ mio_in[25],
+ mio_in[24],
+ mio_in[23],
+ mio_in[22],
+ mio_in[21],
+ mio_in[20],
+ mio_in[19],
+ mio_in[18],
+ mio_in[17],
+ mio_in[16],
+ mio_in[15],
+ mio_in[14],
+ mio_in[13],
+ mio_in[12],
+ mio_in[11],
+ mio_in[10],
+ mio_in[9],
+ mio_in[8],
+ mio_in[7],
+ mio_in[6],
+ mio_in[5],
+ mio_in[4],
+ mio_in[3],
+ mio_in[2],
+ mio_in[1],
+ mio_in[0]
+ }),
+ .mio_out_i ({
+ mio_out[43],
+ mio_out[42],
+ mio_out[41],
+ mio_out[40],
+ mio_out[39],
+ mio_out[38],
+ mio_out[37],
+ mio_out[36],
+ mio_out[35],
+ mio_out[34],
+ mio_out[33],
+ mio_out[32],
+ mio_out[31],
+ mio_out[30],
+ mio_out[29],
+ mio_out[28],
+ mio_out[27],
+ mio_out[26],
+ mio_out[25],
+ mio_out[24],
+ mio_out[23],
+ mio_out[22],
+ mio_out[21],
+ mio_out[20],
+ mio_out[19],
+ mio_out[18],
+ mio_out[17],
+ mio_out[16],
+ mio_out[15],
+ mio_out[14],
+ mio_out[13],
+ mio_out[12],
+ mio_out[11],
+ mio_out[10],
+ mio_out[9],
+ mio_out[8],
+ mio_out[7],
+ mio_out[6],
+ mio_out[5],
+ mio_out[4],
+ mio_out[3],
+ mio_out[2],
+ mio_out[1],
+ mio_out[0]
+ }),
+ .mio_oe_i ({
+ mio_oe[43],
+ mio_oe[42],
+ mio_oe[41],
+ mio_oe[40],
+ mio_oe[39],
+ mio_oe[38],
+ mio_oe[37],
+ mio_oe[36],
+ mio_oe[35],
+ mio_oe[34],
+ mio_oe[33],
+ mio_oe[32],
+ mio_oe[31],
+ mio_oe[30],
+ mio_oe[29],
+ mio_oe[28],
+ mio_oe[27],
+ mio_oe[26],
+ mio_oe[25],
+ mio_oe[24],
+ mio_oe[23],
+ mio_oe[22],
+ mio_oe[21],
+ mio_oe[20],
+ mio_oe[19],
+ mio_oe[18],
+ mio_oe[17],
+ mio_oe[16],
+ mio_oe[15],
+ mio_oe[14],
+ mio_oe[13],
+ mio_oe[12],
+ mio_oe[11],
+ mio_oe[10],
+ mio_oe[9],
+ mio_oe[8],
+ mio_oe[7],
+ mio_oe[6],
+ mio_oe[5],
+ mio_oe[4],
+ mio_oe[3],
+ mio_oe[2],
+ mio_oe[1],
+ mio_oe[0]
+ }),
+ .mio_attr_i ({
+ mio_attr[43],
+ mio_attr[42],
+ mio_attr[41],
+ mio_attr[40],
+ mio_attr[39],
+ mio_attr[38],
+ mio_attr[37],
+ mio_attr[36],
+ mio_attr[35],
+ mio_attr[34],
+ mio_attr[33],
+ mio_attr[32],
+ mio_attr[31],
+ mio_attr[30],
+ mio_attr[29],
+ mio_attr[28],
+ mio_attr[27],
+ mio_attr[26],
+ mio_attr[25],
+ mio_attr[24],
+ mio_attr[23],
+ mio_attr[22],
+ mio_attr[21],
+ mio_attr[20],
+ mio_attr[19],
+ mio_attr[18],
+ mio_attr[17],
+ mio_attr[16],
+ mio_attr[15],
+ mio_attr[14],
+ mio_attr[13],
+ mio_attr[12],
+ mio_attr[11],
+ mio_attr[10],
+ mio_attr[9],
+ mio_attr[8],
+ mio_attr[7],
+ mio_attr[6],
+ mio_attr[5],
+ mio_attr[4],
+ mio_attr[3],
+ mio_attr[2],
+ mio_attr[1],
+ mio_attr[0]
+ })
+ );
+
+
+
+
+
+ //////////////////////////////////
+ // Manual Pad / Signal Tie-offs //
+ //////////////////////////////////
+
+ assign manual_out_por_n = 1'b0;
+ assign manual_oe_por_n = 1'b0;
+
+ assign manual_out_flash_test_mode0 = 1'b0;
+ assign manual_oe_flash_test_mode0 = 1'b0;
+ assign manual_out_flash_test_mode1 = 1'b0;
+ assign manual_oe_flash_test_mode1 = 1'b0;
+ assign manual_out_flash_test_mode2 = 1'b0;
+ assign manual_oe_flash_test_mode2 = 1'b0;
+ assign manual_out_flash_test_mode3 = 1'b0;
+ assign manual_oe_flash_test_mode3 = 1'b0;
+
+ assign manual_out_cc1 = 1'b0;
+ assign manual_oe_cc1 = 1'b0;
+ assign manual_out_cc2 = 1'b0;
+ assign manual_oe_cc2 = 1'b0;
+
+ assign manual_out_flash_test_volt = 1'b0;
+ assign manual_oe_flash_test_volt = 1'b0;
+
+ // These pad attributes currently tied off permanently (these are all input-only pads).
+ assign manual_attr_por_n = '0;
+ assign manual_attr_cc1 = '0;
+ assign manual_attr_cc2 = '0;
+ assign manual_attr_flash_test_mode0 = '0;
+ assign manual_attr_flash_test_mode1 = '0;
+ assign manual_attr_flash_test_mode2 = '0;
+ assign manual_attr_flash_test_mode3 = '0;
+ assign manual_attr_flash_test_volt = '0;
+
+ logic unused_manual_sigs;
+ assign unused_manual_sigs = ^{
+ manual_in_cc2,
+ manual_in_cc1,
+ manual_in_flash_test_mode3,
+ manual_in_flash_test_mode2,
+ manual_in_flash_test_mode1,
+ manual_in_flash_test_mode0,
+ manual_in_flash_test_volt
+ };
+
+ ///////////////////////////////
+ // Differential USB Receiver //
+ ///////////////////////////////
+
+ // TODO: generalize this USB mux code and align with other tops.
+
+ // Connect the DP pad
+ assign dio_in[DioUsbdevDp] = manual_in_usb_p;
+ assign manual_out_usb_p = dio_out[DioUsbdevDp];
+ assign manual_oe_usb_p = dio_oe[DioUsbdevDp];
+ assign manual_attr_usb_p = dio_attr[DioUsbdevDp];
+
+ // Connect the DN pad
+ assign dio_in[DioUsbdevDn] = manual_in_usb_n;
+ assign manual_out_usb_n = dio_out[DioUsbdevDn];
+ assign manual_oe_usb_n = dio_oe[DioUsbdevDn];
+ assign manual_attr_usb_n = dio_attr[DioUsbdevDn];
+
+ // Pullups
+ logic usb_pullup_p_en, usb_pullup_n_en;
+ assign usb_pullup_p_en = dio_out[DioUsbdevDpPullup] & dio_oe[DioUsbdevDpPullup];
+ assign usb_pullup_n_en = dio_out[DioUsbdevDnPullup] & dio_oe[DioUsbdevDnPullup];
+
+ // TODO(#5925): connect this to AST?
+ logic usbdev_aon_usb_rx_enable;
+ logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
+ assign usbdev_aon_usb_rx_enable = 1'b0;
+
+ prim_usb_diff_rx #(
+ .CalibW(ast_pkg::UsbCalibWidth)
+ ) u_prim_usb_diff_rx (
+ .input_pi ( USB_P ),
+ .input_ni ( USB_N ),
+ .input_en_i ( usbdev_aon_usb_rx_enable ),
+ .core_pok_i ( ast_base_pwr.main_pok ),
+ .pullup_p_en_i ( usb_pullup_p_en ),
+ .pullup_n_en_i ( usb_pullup_n_en ),
+ .calibration_i ( usb_io_pu_cal ),
+ .input_o ( dio_in[DioUsbdevD] )
+ );
+
+ // Tie-off unused signals
+ assign dio_in[DioUsbdevSense] = 1'b0;
+ assign dio_in[DioUsbdevSe0] = 1'b0;
+ assign dio_in[DioUsbdevTxModeSe] = 1'b0;
+ assign dio_in[DioUsbdevSuspend] = 1'b0;
+
+ logic unused_usb_sigs;
+ assign unused_usb_sigs = ^{
+ // Sense
+ dio_out[DioUsbdevSense],
+ dio_oe[DioUsbdevSense],
+ dio_attr[DioUsbdevSense],
+ // SE0
+ dio_out[DioUsbdevSe0],
+ dio_oe[DioUsbdevSe0],
+ dio_attr[DioUsbdevSe0],
+ // TX Mode
+ dio_out[DioUsbdevTxModeSe],
+ dio_oe[DioUsbdevTxModeSe],
+ dio_attr[DioUsbdevTxModeSe],
+ // Suspend
+ dio_out[DioUsbdevSuspend],
+ dio_oe[DioUsbdevSuspend],
+ dio_attr[DioUsbdevSuspend],
+ // D is used as an input only
+ dio_out[DioUsbdevD],
+ dio_oe[DioUsbdevD],
+ dio_attr[DioUsbdevD]
+ };
+
+ //////////////////////
+ // AST //
+ //////////////////////
+ // TLUL interface
+ tlul_pkg::tl_h2d_t base_ast_bus;
+ tlul_pkg::tl_d2h_t ast_base_bus;
+
+ // assorted ast status
+ ast_pkg::ast_status_t ast_status;
+
+ // ast clocks and resets
+ logic aon_pok;
+
+ // pwrmgr interface
+ pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+
+ // synchronization clocks / rests
+ clkmgr_pkg::clkmgr_ast_out_t clks_ast;
+ rstmgr_pkg::rstmgr_ast_out_t rsts_ast;
+
+ // otp power sequence
+ otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
+ otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
+
+ logic usb_ref_pulse;
+ logic usb_ref_val;
+
+ // adc
+ // The adc package definition should eventually be moved to the adc module
+ ast_pkg::adc_ast_req_t adc_i;
+ ast_pkg::adc_ast_rsp_t adc_o;
+
+ // entropy source interface
+ // The entropy source pacakge definition should eventually be moved to es
+ entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+ entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+ logic es_rng_fips;
+
+ // entropy distribution network
+ edn_pkg::edn_req_t ast_edn_edn_req;
+ edn_pkg::edn_rsp_t ast_edn_edn_rsp;
+
+ // alerts interface
+ ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+ ast_pkg::ast_alert_req_t ast_alert_req;
+
+ // Flash connections
+ lc_ctrl_pkg::lc_tx_t flash_bist_enable;
+ logic flash_power_down_h;
+ logic flash_power_ready_h;
+
+ // Life cycle clock bypass req/ack
+ lc_ctrl_pkg::lc_tx_t ast_clk_byp_req;
+ lc_ctrl_pkg::lc_tx_t ast_clk_byp_ack;
+
+ // DFT connections
+ logic scan_en;
+ lc_ctrl_pkg::lc_tx_t dft_en;
+ pinmux_pkg::dft_strap_test_req_t dft_strap_test;
+
+ // Debug connections
+ logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
+ logic [ast_pkg::Pad2AstInWidth-1:0] pinmux2ast;
+
+ // Jitter enable
+ logic jen;
+
+ // Alert connections
+ import sensor_ctrl_reg_pkg::AsSel;
+ import sensor_ctrl_reg_pkg::CgSel;
+ import sensor_ctrl_reg_pkg::GdSel;
+ import sensor_ctrl_reg_pkg::TsHiSel;
+ import sensor_ctrl_reg_pkg::TsLoSel;
+ import sensor_ctrl_reg_pkg::LsSel;
+ import sensor_ctrl_reg_pkg::OtSel;
+
+ // reset domain connections
+ import rstmgr_pkg::PowerDomains;
+ import rstmgr_pkg::DomainAonSel;
+ import rstmgr_pkg::Domain0Sel;
+
+ // adc connections
+ ast_pkg::adc_ast_req_t adc_req;
+ ast_pkg::adc_ast_rsp_t adc_rsp;
+
+ // TODO: need to mux the external clock.
+ logic ext_clk;
+ assign ext_clk = 1'b0;
+
+ // Memory configuration connections
+ ast_pkg::spm_rm_t ast_ram_1p_cfg;
+ ast_pkg::spm_rm_t ast_rf_cfg;
+ ast_pkg::spm_rm_t ast_rom_cfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
+
+ prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
+ prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
+ prim_rom_pkg::rom_cfg_t rom_cfg;
+
+ // conversion from ast structure to memory centric structures
+ assign ram_1p_cfg = '{
+ ram_cfg: '{
+ cfg_en: ast_ram_1p_cfg.marg_en,
+ cfg: ast_ram_1p_cfg.marg
+ },
+ rf_cfg: '{
+ cfg_en: ast_rf_cfg.marg_en,
+ cfg: ast_rf_cfg.marg
+ }
+ };
+
+ assign ram_2p_cfg = '{
+ a_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_a,
+ cfg: ast_ram_2p_fcfg.marg_a
+ },
+ a_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_a,
+ cfg: ast_ram_2p_lcfg.marg_a
+ },
+ b_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_b,
+ cfg: ast_ram_2p_fcfg.marg_b
+ },
+ b_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_b,
+ cfg: ast_ram_2p_lcfg.marg_b
+ }
+ };
+
+ assign rom_cfg = '{
+ cfg_en: ast_rom_cfg.marg_en,
+ cfg: ast_rom_cfg.marg
+ };
+
+
+ // AST does not use all clocks / resets forwarded to it
+ logic unused_slow_clk_en;
+ logic unused_usb_clk_aon;
+ logic unused_usb_clk_io_div4;
+ assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
+ assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri;
+ assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri;
+
+ logic unused_usb_usb_rst;
+ logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst;
+ logic [PowerDomains-1:0] unused_usb_sys_aon_rst;
+ logic unused_ast_sys_io_div4_rst;
+ logic unused_sensor_ctrl_sys_io_div4_rst;
+ logic unused_adc_ctrl_sys_io_div4_rst;
+ logic unused_entropy_sys_rst;
+ logic unused_edn_sys_rst;
+ assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel];
+ assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n;
+ assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n;
+ assign unused_ast_sys_io_div4_rst =
+ rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel];
+ assign unused_sensor_ctrl_sys_io_div4_rst =
+ rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[Domain0Sel];
+ assign unused_adc_ctrl_sys_io_div4_rst =
+ rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[Domain0Sel];
+ assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel];
+ assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel];
+
+
+ ast #(
+ .EntropyStreams(top_pkg::ENTROPY_STREAM),
+ .AdcChannels(top_pkg::ADC_CHANNELS),
+ .AdcDataWidth(top_pkg::ADC_DATAW),
+ .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+ .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+ .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
+ ) u_ast (
+ // tlul
+ .tl_i ( base_ast_bus ),
+ .tl_o ( ast_base_bus ),
+ // buffered clocks & resets
+ // Reset domain connection is manual at the moment
+ .clk_ast_adc_i ( clks_ast.clk_ast_adc_ctrl_aon_io_div4_peri ),
+ .rst_ast_adc_ni ( rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_alert_i ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ),
+ .rst_ast_alert_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_es_i ( clks_ast.clk_ast_edn0_main_secure ),
+ .rst_ast_es_ni ( rsts_ast.rst_ast_edn0_sys_n[Domain0Sel] ),
+ .clk_ast_rng_i ( clks_ast.clk_ast_entropy_src_main_secure ),
+ .rst_ast_rng_ni ( rsts_ast.rst_ast_entropy_src_sys_n[Domain0Sel] ),
+ .clk_ast_tlul_i ( clks_ast.clk_ast_ast_io_div4_secure ),
+ .rst_ast_tlul_ni ( rsts_ast.rst_ast_ast_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ),
+ .rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ),
+ .clk_ast_ext_i ( ext_clk ),
+ .por_ni ( manual_in_por_n ),
+ // pok test for FPGA
+ .vcc_supp_i ( 1'b1 ),
+ .vcaon_supp_i ( 1'b1 ),
+ .vcmain_supp_i ( 1'b1 ),
+ .vioa_supp_i ( 1'b1 ),
+ .viob_supp_i ( 1'b1 ),
+ // pok
+ .vcaon_pok_o ( aon_pok ),
+ .vcmain_pok_o ( ast_base_pwr.main_pok ),
+ .vioa_pok_o ( ast_status.io_pok[0] ),
+ .viob_pok_o ( ast_status.io_pok[1] ),
+ // main regulator
+ .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
+ .main_pd_ni ( base_ast_pwr.main_pd_n ),
+ // pdm control (flash)/otp
+ .flash_power_down_h_o ( flash_power_down_h ),
+ .flash_power_ready_h_o ( flash_power_ready_h ),
+ .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
+ // system source clock
+ .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
+ // need to add function in clkmgr
+ .clk_src_sys_jen_i ( jen ),
+ .clk_src_sys_o ( ast_base_clks.clk_sys ),
+ .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
+ // aon source clock
+ .clk_src_aon_o ( ast_base_clks.clk_aon ),
+ .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
+ // io source clock
+ .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
+ .clk_src_io_o ( ast_base_clks.clk_io ),
+ .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
+ // usb source clock
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
+ .clk_src_usb_o ( ast_base_clks.clk_usb ),
+ .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
+ // USB IO Pull-up Calibration Setting
+ .usb_io_pu_cal_o ( usb_io_pu_cal ),
+ // adc
+ .adc_a0_ai ( CC1 ),
+ .adc_a1_ai ( CC2 ),
+ .adc_pd_i ( adc_req.pd ),
+ .adc_chnsel_i ( adc_req.channel_sel ),
+ .adc_d_o ( adc_rsp.data ),
+ .adc_d_val_o ( adc_rsp.data_valid ),
+ // rng
+ .rng_en_i ( es_rng_req.rng_enable ),
+ .rng_fips_i ( es_rng_fips ),
+ .rng_val_o ( es_rng_rsp.rng_valid ),
+ .rng_b_o ( es_rng_rsp.rng_b ),
+ // entropy
+ .entropy_rsp_i ( ast_edn_edn_rsp ),
+ .entropy_req_o ( ast_edn_edn_req ),
+ // alerts
+ .as_alert_trig_i ( ast_alert_rsp.alerts_trig[AsSel] ),
+ .as_alert_ack_i ( ast_alert_rsp.alerts_ack[AsSel] ),
+ .as_alert_o ( ast_alert_req.alerts[AsSel] ),
+ .cg_alert_trig_i ( ast_alert_rsp.alerts_trig[CgSel] ),
+ .cg_alert_ack_i ( ast_alert_rsp.alerts_ack[CgSel] ),
+ .cg_alert_o ( ast_alert_req.alerts[CgSel] ),
+ .gd_alert_trig_i ( ast_alert_rsp.alerts_trig[GdSel] ),
+ .gd_alert_ack_i ( ast_alert_rsp.alerts_ack[GdSel] ),
+ .gd_alert_o ( ast_alert_req.alerts[GdSel] ),
+ .ts_alert_hi_trig_i ( ast_alert_rsp.alerts_trig[TsHiSel] ),
+ .ts_alert_hi_ack_i ( ast_alert_rsp.alerts_ack[TsHiSel] ),
+ .ts_alert_hi_o ( ast_alert_req.alerts[TsHiSel] ),
+ .ts_alert_lo_trig_i ( ast_alert_rsp.alerts_trig[TsLoSel] ),
+ .ts_alert_lo_ack_i ( ast_alert_rsp.alerts_ack[TsLoSel] ),
+ .ts_alert_lo_o ( ast_alert_req.alerts[TsLoSel] ),
+ .ls_alert_trig_i ( ast_alert_rsp.alerts_trig[LsSel] ),
+ .ls_alert_ack_i ( ast_alert_rsp.alerts_ack[LsSel] ),
+ .ls_alert_o ( ast_alert_req.alerts[LsSel] ),
+ .ot_alert_trig_i ( ast_alert_rsp.alerts_trig[OtSel] ),
+ .ot_alert_ack_i ( ast_alert_rsp.alerts_ack[OtSel] ),
+ .ot_alert_o ( ast_alert_req.alerts[OtSel] ),
+ // dft
+ .dft_strap_test_i ( dft_strap_test ),
+ .lc_dft_en_i ( dft_en ),
+ // pinmux related
+ .padmux2ast_i ( pinmux2ast ),
+ .ast2padmux_o ( ast2pinmux ),
+ // Direct short to PAD
+ .pad2ast_t0_ai ( IOA4 ),
+ .pad2ast_t1_ai ( IOA5 ),
+ .ast2pad_t0_ao ( IOA2 ),
+ .ast2pad_t1_ao ( IOA3 ),
+ .lc_clk_byp_req_i ( ast_clk_byp_req ),
+ .lc_clk_byp_ack_o ( ast_clk_byp_ack ),
+ .flash_bist_en_o ( flash_bist_enable ),
+ // Memory configuration connections
+ .dpram_rmf_o ( ast_ram_2p_fcfg ),
+ .dpram_rml_o ( ast_ram_2p_lcfg ),
+ .spram_rm_o ( ast_ram_1p_cfg ),
+ .sprgf_rm_o ( ast_rf_cfg ),
+ .sprom_rm_o ( ast_rom_cfg ),
+ // scan
+ .dft_scan_md_o ( scanmode ),
+ .scan_shift_en_o ( scan_en ),
+ .scan_reset_no ( scan_rst_n )
+ );
+
+ //////////////////////
+ // Top-level design //
+ //////////////////////
+
+ top_earlgrey #(
+ .AesMasking(1'b1),
+ .AesSBoxImpl(aes_pkg::SBoxImplDom),
+ .SecAesStartTriggerDelay(0),
+ .SecAesAllowForcingMasks(1'b0),
+ .KmacEnMasking(1), // DOM AND + Masking scheme
+ .KmacReuseShare(0),
+ .SramCtrlRetAonInstrExec(0),
+ .SramCtrlMainInstrExec(1),
+ .PinmuxAonTargetCfg(PinmuxTargetCfg)
+ ) top_earlgrey (
+ .rst_ni ( aon_pok ),
+ // ast connections
+ .clk_main_i ( ast_base_clks.clk_sys ),
+ .clk_io_i ( ast_base_clks.clk_io ),
+ .clk_usb_i ( ast_base_clks.clk_usb ),
+ .clk_aon_i ( ast_base_clks.clk_aon ),
+ .clks_ast_o ( clks_ast ),
+ .clk_main_jitter_en_o ( jen ),
+ .rsts_ast_o ( rsts_ast ),
+ .pwrmgr_ast_req_o ( base_ast_pwr ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
+ .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
+ .sensor_ctrl_ast_status_i ( ast_status ),
+ .usbdev_usb_ref_val_o ( usb_ref_pulse ),
+ .usbdev_usb_ref_pulse_o ( usb_ref_val ),
+ .ast_tl_req_o ( base_ast_bus ),
+ .ast_tl_rsp_i ( ast_base_bus ),
+ .adc_req_o ( adc_req ),
+ .adc_rsp_i ( adc_rsp ),
+ .ast_edn_req_i ( ast_edn_edn_req ),
+ .ast_edn_rsp_o ( ast_edn_edn_rsp ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
+ .flash_bist_enable_i ( flash_bist_enable ),
+ .flash_power_down_h_i ( flash_power_down_h ),
+ .flash_power_ready_h_i ( flash_power_ready_h ),
+ .es_rng_req_o ( es_rng_req ),
+ .es_rng_rsp_i ( es_rng_rsp ),
+ .es_rng_fips_o ( es_rng_fips ),
+ .ast_clk_byp_req_o ( ast_clk_byp_req ),
+ .ast_clk_byp_ack_i ( ast_clk_byp_ack ),
+ .pinmux2ast_o ( pinmux2ast ),
+ .ast2pinmux_i ( ast2pinmux ),
+
+ // Flash test mode voltages
+ .flash_test_mode_a_io ( {FLASH_TEST_MODE3,
+ FLASH_TEST_MODE2,
+ FLASH_TEST_MODE1,
+ FLASH_TEST_MODE0} ),
+ .flash_test_voltage_h_io ( FLASH_TEST_VOLT ),
+
+ // Multiplexed I/O
+ .mio_in_i ( mio_in ),
+ .mio_out_o ( mio_out ),
+ .mio_oe_o ( mio_oe ),
+
+ // Dedicated I/O
+ .dio_in_i ( dio_in ),
+ .dio_out_o ( dio_out ),
+ .dio_oe_o ( dio_oe ),
+
+ // Pad attributes
+ .mio_attr_o ( mio_attr ),
+ .dio_attr_o ( dio_attr ),
+
+ // Memory attributes
+ .ram_1p_cfg_i ( ram_1p_cfg ),
+ .ram_2p_cfg_i ( ram_2p_cfg ),
+ .rom_cfg_i ( rom_cfg ),
+
+ // DFT signals
+ .ast_lc_dft_en_o ( dft_en ),
+ .dft_strap_test_o ( dft_strap_test ),
+ .scan_rst_ni ( scan_rst_n ),
+ .scan_en_i ( scan_en ),
+ .scanmode_i ( scanmode )
+ );
+
+
+
+
+// TODO: change the naming to chip_
+endmodule : top_earlgrey_asic
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_nexysvideo.sv
new file mode 100644
index 0000000..a61b5da
--- /dev/null
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_nexysvideo.sv
@@ -0,0 +1,813 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
+// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+//
+// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \
+// -o hw/top_earlgrey/ \
+// --rnd_cnst_seed 4881560218908238235
+
+// TODO: change the naming to chip_earlgrey_nexysvideo
+module top_earlgrey_nexysvideo #(
+ // Path to a VMEM file containing the contents of the boot ROM, which will be
+ // baked into the FPGA bitstream.
+ parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem",
+ // Path to a VMEM file containing the contents of the emulated OTP, which will be
+ // baked into the FPGA bitstream.
+ parameter OtpCtrlMemInitFile = "otp_img_fpga_nexysvideo.vmem"
+) (
+ // Dedicated Pads
+ inout POR_N, // Manual Pad
+ inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd
+ inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck
+ inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb
+ inout USB_P, // Manual Pad
+ inout USB_N, // Manual Pad
+ inout IO_CLK, // Manual Pad
+ inout IO_JSRST_N, // Manual Pad
+ inout IO_USB_SENSE0, // Manual Pad
+ inout IO_USB_DNPULLUP0, // Manual Pad
+ inout IO_USB_DPPULLUP0, // Manual Pad
+ inout IO_UPHY_DP_TX, // Manual Pad
+ inout IO_UPHY_DN_TX, // Manual Pad
+ inout IO_UPHY_DP_RX, // Manual Pad
+ inout IO_UPHY_DN_RX, // Manual Pad
+ inout IO_UPHY_D_RX, // Manual Pad
+ inout IO_UPHY_OE_N, // Manual Pad
+ inout IO_UPHY_SENSE, // Manual Pad
+ inout IO_UPHY_DPPULLUP, // Manual Pad
+
+ // Muxed Pads
+ inout IOA0, // MIO Pad 0
+ inout IOA1, // MIO Pad 1
+ inout IOA2, // MIO Pad 2
+ inout IOA3, // MIO Pad 3
+ inout IOA4, // MIO Pad 4
+ inout IOA5, // MIO Pad 5
+ inout IOB0, // MIO Pad 6
+ inout IOB1, // MIO Pad 7
+ inout IOB2, // MIO Pad 8
+ inout IOB3, // MIO Pad 9
+ inout IOB4, // MIO Pad 10
+ inout IOB5, // MIO Pad 11
+ inout IOB6, // MIO Pad 12
+ inout IOB7, // MIO Pad 13
+ inout IOB8, // MIO Pad 14
+ inout IOB9, // MIO Pad 15
+ inout IOB10, // MIO Pad 16
+ inout IOB11, // MIO Pad 17
+ inout IOC0, // MIO Pad 18
+ inout IOC6, // MIO Pad 24
+ inout IOC7, // MIO Pad 25
+ inout IOC8, // MIO Pad 26
+ inout IOC9, // MIO Pad 27
+ inout IOC10, // MIO Pad 28
+ inout IOC11, // MIO Pad 29
+ inout IOR0, // MIO Pad 30
+ inout IOR1, // MIO Pad 31
+ inout IOR2, // MIO Pad 32
+ inout IOR3 // MIO Pad 33
+);
+
+ import top_earlgrey_pkg::*;
+ import prim_pad_wrapper_pkg::*;
+
+ ////////////////////////////
+ // Special Signal Indices //
+ ////////////////////////////
+
+ parameter int Tap0PadIdx = 20;
+ parameter int Tap1PadIdx = 16;
+ parameter int Dft0PadIdx = 21;
+ parameter int Dft1PadIdx = 22;
+ parameter int TckPadIdx = 55;
+ parameter int TmsPadIdx = 56;
+ parameter int TrstNPadIdx = 18;
+ parameter int TdiPadIdx = 48;
+ parameter int TdoPadIdx = 49;
+
+ // TODO: this is temporary and will be removed in the future.
+ // This specifies the tie-off values of the muxed MIO/DIOs
+ // when the JTAG is active. SPI CSB is active low.
+ localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << (
+ pinmux_reg_pkg::NMioPads + DioSpiDeviceCsb));
+
+ // DFT and Debug signal positions in the pinout.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ const_sampling: 1'b1,
+ tie_offs: TieOffValues, // TODO: can we remove this and just set it to zero?
+ tck_idx: TckPadIdx,
+ tms_idx: TmsPadIdx,
+ trst_idx: TrstNPadIdx,
+ tdi_idx: TdiPadIdx,
+ tdo_idx: TdoPadIdx,
+ tap_strap0_idx: Tap0PadIdx,
+ tap_strap1_idx: Tap1PadIdx,
+ dft_strap0_idx: Dft0PadIdx,
+ dft_strap1_idx: Dft1PadIdx,
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevDp,
+ usb_dn_idx: DioUsbdevDn,
+ usb_dp_pullup_idx: DioUsbdevDpPullup,
+ usb_dn_pullup_idx: DioUsbdevDnPullup
+ };
+
+ ////////////////////////
+ // Signal definitions //
+ ////////////////////////
+
+ pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+ pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+
+ // Manual pads
+ logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
+ logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
+ logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
+ logic manual_in_io_clk, manual_out_io_clk, manual_oe_io_clk;
+ logic manual_in_io_jsrst_n, manual_out_io_jsrst_n, manual_oe_io_jsrst_n;
+ logic manual_in_io_usb_sense0, manual_out_io_usb_sense0, manual_oe_io_usb_sense0;
+ logic manual_in_io_usb_dnpullup0, manual_out_io_usb_dnpullup0, manual_oe_io_usb_dnpullup0;
+ logic manual_in_io_usb_dppullup0, manual_out_io_usb_dppullup0, manual_oe_io_usb_dppullup0;
+ logic manual_in_io_uphy_dp_tx, manual_out_io_uphy_dp_tx, manual_oe_io_uphy_dp_tx;
+ logic manual_in_io_uphy_dn_tx, manual_out_io_uphy_dn_tx, manual_oe_io_uphy_dn_tx;
+ logic manual_in_io_uphy_dp_rx, manual_out_io_uphy_dp_rx, manual_oe_io_uphy_dp_rx;
+ logic manual_in_io_uphy_dn_rx, manual_out_io_uphy_dn_rx, manual_oe_io_uphy_dn_rx;
+ logic manual_in_io_uphy_d_rx, manual_out_io_uphy_d_rx, manual_oe_io_uphy_d_rx;
+ logic manual_in_io_uphy_oe_n, manual_out_io_uphy_oe_n, manual_oe_io_uphy_oe_n;
+ logic manual_in_io_uphy_sense, manual_out_io_uphy_sense, manual_oe_io_uphy_sense;
+ logic manual_in_io_uphy_dppullup, manual_out_io_uphy_dppullup, manual_oe_io_uphy_dppullup;
+
+ pad_attr_t manual_attr_por_n;
+ pad_attr_t manual_attr_usb_p;
+ pad_attr_t manual_attr_usb_n;
+ pad_attr_t manual_attr_io_clk;
+ pad_attr_t manual_attr_io_jsrst_n;
+ pad_attr_t manual_attr_io_usb_sense0;
+ pad_attr_t manual_attr_io_usb_dnpullup0;
+ pad_attr_t manual_attr_io_usb_dppullup0;
+ pad_attr_t manual_attr_io_uphy_dp_tx;
+ pad_attr_t manual_attr_io_uphy_dn_tx;
+ pad_attr_t manual_attr_io_uphy_dp_rx;
+ pad_attr_t manual_attr_io_uphy_dn_rx;
+ pad_attr_t manual_attr_io_uphy_d_rx;
+ pad_attr_t manual_attr_io_uphy_oe_n;
+ pad_attr_t manual_attr_io_uphy_sense;
+ pad_attr_t manual_attr_io_uphy_dppullup;
+
+ /////////////////////////
+ // Stubbed pad tie-off //
+ /////////////////////////
+
+ // Only signals going to non-custom pads need to be tied off.
+ logic [65:0] unused_sig;
+ assign dio_in[DioSpiHost0Sd0] = 1'b0;
+ assign unused_sig[1] = dio_out[DioSpiHost0Sd0] ^ dio_oe[DioSpiHost0Sd0];
+ assign dio_in[DioSpiHost0Sd1] = 1'b0;
+ assign unused_sig[2] = dio_out[DioSpiHost0Sd1] ^ dio_oe[DioSpiHost0Sd1];
+ assign dio_in[DioSpiHost0Sd2] = 1'b0;
+ assign unused_sig[3] = dio_out[DioSpiHost0Sd2] ^ dio_oe[DioSpiHost0Sd2];
+ assign dio_in[DioSpiHost0Sd3] = 1'b0;
+ assign unused_sig[4] = dio_out[DioSpiHost0Sd3] ^ dio_oe[DioSpiHost0Sd3];
+ assign dio_in[DioSpiHost0Sck] = 1'b0;
+ assign unused_sig[5] = dio_out[DioSpiHost0Sck] ^ dio_oe[DioSpiHost0Sck];
+ assign dio_in[DioSpiHost0Csb] = 1'b0;
+ assign unused_sig[6] = dio_out[DioSpiHost0Csb] ^ dio_oe[DioSpiHost0Csb];
+ assign dio_in[DioSpiDeviceSd2] = 1'b0;
+ assign unused_sig[9] = dio_out[DioSpiDeviceSd2] ^ dio_oe[DioSpiDeviceSd2];
+ assign dio_in[DioSpiDeviceSd3] = 1'b0;
+ assign unused_sig[10] = dio_out[DioSpiDeviceSd3] ^ dio_oe[DioSpiDeviceSd3];
+ assign mio_in[19] = 1'b0;
+ assign unused_sig[41] = mio_out[19] ^ mio_oe[19];
+ assign mio_in[20] = 1'b0;
+ assign unused_sig[42] = mio_out[20] ^ mio_oe[20];
+ assign mio_in[21] = 1'b0;
+ assign unused_sig[43] = mio_out[21] ^ mio_oe[21];
+ assign mio_in[22] = 1'b0;
+ assign unused_sig[44] = mio_out[22] ^ mio_oe[22];
+ assign mio_in[23] = 1'b0;
+ assign unused_sig[45] = mio_out[23] ^ mio_oe[23];
+ assign mio_in[34] = 1'b0;
+ assign unused_sig[56] = mio_out[34] ^ mio_oe[34];
+ assign mio_in[35] = 1'b0;
+ assign unused_sig[57] = mio_out[35] ^ mio_oe[35];
+ assign mio_in[36] = 1'b0;
+ assign unused_sig[58] = mio_out[36] ^ mio_oe[36];
+ assign mio_in[37] = 1'b0;
+ assign unused_sig[59] = mio_out[37] ^ mio_oe[37];
+ assign mio_in[38] = 1'b0;
+ assign unused_sig[60] = mio_out[38] ^ mio_oe[38];
+ assign mio_in[39] = 1'b0;
+ assign unused_sig[61] = mio_out[39] ^ mio_oe[39];
+ assign mio_in[40] = 1'b0;
+ assign unused_sig[62] = mio_out[40] ^ mio_oe[40];
+ assign mio_in[41] = 1'b0;
+ assign unused_sig[63] = mio_out[41] ^ mio_oe[41];
+ assign mio_in[42] = 1'b0;
+ assign unused_sig[64] = mio_out[42] ^ mio_oe[42];
+ assign mio_in[43] = 1'b0;
+ assign unused_sig[65] = mio_out[43] ^ mio_oe[43];
+
+ //////////////////////
+ // Padring Instance //
+ //////////////////////
+
+
+ padring #(
+ // Padring specific counts may differ from pinmux config due
+ // to custom, stubbed or added pads.
+ .NDioPads(20),
+ .NMioPads(29),
+ .DioPadType ({
+ BidirStd, // IO_UPHY_DPPULLUP
+ BidirStd, // IO_UPHY_SENSE
+ BidirStd, // IO_UPHY_OE_N
+ BidirStd, // IO_UPHY_D_RX
+ BidirStd, // IO_UPHY_DN_RX
+ BidirStd, // IO_UPHY_DP_RX
+ BidirStd, // IO_UPHY_DN_TX
+ BidirStd, // IO_UPHY_DP_TX
+ BidirStd, // IO_USB_DPPULLUP0
+ BidirStd, // IO_USB_DNPULLUP0
+ BidirStd, // IO_USB_SENSE0
+ InputStd, // IO_JSRST_N
+ InputStd, // IO_CLK
+ BidirTol, // USB_N
+ BidirTol, // USB_P
+ InputStd, // SPI_DEV_CS_L
+ InputStd, // SPI_DEV_CLK
+ BidirStd, // SPI_DEV_D1
+ BidirStd, // SPI_DEV_D0
+ InputStd // POR_N
+ }),
+ .MioPadType ({
+ InputStd, // IOR3
+ InputStd, // IOR2
+ InputStd, // IOR1
+ InputStd, // IOR0
+ BidirOd, // IOC11
+ BidirOd, // IOC10
+ BidirOd, // IOC9
+ BidirOd, // IOC8
+ InputStd, // IOC7
+ InputStd, // IOC6
+ InputStd, // IOC0
+ InputStd, // IOB11
+ InputStd, // IOB10
+ BidirOd, // IOB9
+ BidirOd, // IOB8
+ InputStd, // IOB7
+ InputStd, // IOB6
+ InputStd, // IOB5
+ InputStd, // IOB4
+ InputStd, // IOB3
+ InputStd, // IOB2
+ InputStd, // IOB1
+ InputStd, // IOB0
+ BidirOd, // IOA5
+ BidirOd, // IOA4
+ InputStd, // IOA3
+ InputStd, // IOA2
+ InputStd, // IOA1
+ InputStd // IOA0
+ })
+ ) u_padring (
+ // This is only used for scan and DFT purposes
+ .clk_scan_i ( 1'b0 ),
+ .scanmode_i ( lc_ctrl_pkg::Off ),
+ // TODO: wire this up to AST. Hint: the top_<name>_pkg contains
+ // generated parameters that can be used to index pads by name.
+ .dio_in_raw_o ( ),
+ .mio_in_raw_o ( ),
+ // Chip IOs
+ .dio_pad_io ({
+ IO_UPHY_DPPULLUP,
+ IO_UPHY_SENSE,
+ IO_UPHY_OE_N,
+ IO_UPHY_D_RX,
+ IO_UPHY_DN_RX,
+ IO_UPHY_DP_RX,
+ IO_UPHY_DN_TX,
+ IO_UPHY_DP_TX,
+ IO_USB_DPPULLUP0,
+ IO_USB_DNPULLUP0,
+ IO_USB_SENSE0,
+ IO_JSRST_N,
+ IO_CLK,
+ USB_N,
+ USB_P,
+ SPI_DEV_CS_L,
+ SPI_DEV_CLK,
+ SPI_DEV_D1,
+ SPI_DEV_D0,
+ POR_N
+ }),
+
+ .mio_pad_io ({
+ IOR3,
+ IOR2,
+ IOR1,
+ IOR0,
+ IOC11,
+ IOC10,
+ IOC9,
+ IOC8,
+ IOC7,
+ IOC6,
+ IOC0,
+ IOB11,
+ IOB10,
+ IOB9,
+ IOB8,
+ IOB7,
+ IOB6,
+ IOB5,
+ IOB4,
+ IOB3,
+ IOB2,
+ IOB1,
+ IOB0,
+ IOA5,
+ IOA4,
+ IOA3,
+ IOA2,
+ IOA1,
+ IOA0
+ }),
+
+ // Core-facing
+ .dio_in_o ({
+ manual_in_io_uphy_dppullup,
+ manual_in_io_uphy_sense,
+ manual_in_io_uphy_oe_n,
+ manual_in_io_uphy_d_rx,
+ manual_in_io_uphy_dn_rx,
+ manual_in_io_uphy_dp_rx,
+ manual_in_io_uphy_dn_tx,
+ manual_in_io_uphy_dp_tx,
+ manual_in_io_usb_dppullup0,
+ manual_in_io_usb_dnpullup0,
+ manual_in_io_usb_sense0,
+ manual_in_io_jsrst_n,
+ manual_in_io_clk,
+ manual_in_usb_n,
+ manual_in_usb_p,
+ dio_in[DioSpiDeviceCsb],
+ dio_in[DioSpiDeviceSck],
+ dio_in[DioSpiDeviceSd1],
+ dio_in[DioSpiDeviceSd0],
+ manual_in_por_n
+ }),
+ .dio_out_i ({
+ manual_out_io_uphy_dppullup,
+ manual_out_io_uphy_sense,
+ manual_out_io_uphy_oe_n,
+ manual_out_io_uphy_d_rx,
+ manual_out_io_uphy_dn_rx,
+ manual_out_io_uphy_dp_rx,
+ manual_out_io_uphy_dn_tx,
+ manual_out_io_uphy_dp_tx,
+ manual_out_io_usb_dppullup0,
+ manual_out_io_usb_dnpullup0,
+ manual_out_io_usb_sense0,
+ manual_out_io_jsrst_n,
+ manual_out_io_clk,
+ manual_out_usb_n,
+ manual_out_usb_p,
+ dio_out[DioSpiDeviceCsb],
+ dio_out[DioSpiDeviceSck],
+ dio_out[DioSpiDeviceSd1],
+ dio_out[DioSpiDeviceSd0],
+ manual_out_por_n
+ }),
+ .dio_oe_i ({
+ manual_oe_io_uphy_dppullup,
+ manual_oe_io_uphy_sense,
+ manual_oe_io_uphy_oe_n,
+ manual_oe_io_uphy_d_rx,
+ manual_oe_io_uphy_dn_rx,
+ manual_oe_io_uphy_dp_rx,
+ manual_oe_io_uphy_dn_tx,
+ manual_oe_io_uphy_dp_tx,
+ manual_oe_io_usb_dppullup0,
+ manual_oe_io_usb_dnpullup0,
+ manual_oe_io_usb_sense0,
+ manual_oe_io_jsrst_n,
+ manual_oe_io_clk,
+ manual_oe_usb_n,
+ manual_oe_usb_p,
+ dio_oe[DioSpiDeviceCsb],
+ dio_oe[DioSpiDeviceSck],
+ dio_oe[DioSpiDeviceSd1],
+ dio_oe[DioSpiDeviceSd0],
+ manual_oe_por_n
+ }),
+ .dio_attr_i ({
+ manual_attr_io_uphy_dppullup,
+ manual_attr_io_uphy_sense,
+ manual_attr_io_uphy_oe_n,
+ manual_attr_io_uphy_d_rx,
+ manual_attr_io_uphy_dn_rx,
+ manual_attr_io_uphy_dp_rx,
+ manual_attr_io_uphy_dn_tx,
+ manual_attr_io_uphy_dp_tx,
+ manual_attr_io_usb_dppullup0,
+ manual_attr_io_usb_dnpullup0,
+ manual_attr_io_usb_sense0,
+ manual_attr_io_jsrst_n,
+ manual_attr_io_clk,
+ manual_attr_usb_n,
+ manual_attr_usb_p,
+ dio_attr[DioSpiDeviceCsb],
+ dio_attr[DioSpiDeviceSck],
+ dio_attr[DioSpiDeviceSd1],
+ dio_attr[DioSpiDeviceSd0],
+ manual_attr_por_n
+ }),
+
+ .mio_in_o ({
+ mio_in[33],
+ mio_in[32],
+ mio_in[31],
+ mio_in[30],
+ mio_in[29],
+ mio_in[28],
+ mio_in[27],
+ mio_in[26],
+ mio_in[25],
+ mio_in[24],
+ mio_in[18],
+ mio_in[17],
+ mio_in[16],
+ mio_in[15],
+ mio_in[14],
+ mio_in[13],
+ mio_in[12],
+ mio_in[11],
+ mio_in[10],
+ mio_in[9],
+ mio_in[8],
+ mio_in[7],
+ mio_in[6],
+ mio_in[5],
+ mio_in[4],
+ mio_in[3],
+ mio_in[2],
+ mio_in[1],
+ mio_in[0]
+ }),
+ .mio_out_i ({
+ mio_out[33],
+ mio_out[32],
+ mio_out[31],
+ mio_out[30],
+ mio_out[29],
+ mio_out[28],
+ mio_out[27],
+ mio_out[26],
+ mio_out[25],
+ mio_out[24],
+ mio_out[18],
+ mio_out[17],
+ mio_out[16],
+ mio_out[15],
+ mio_out[14],
+ mio_out[13],
+ mio_out[12],
+ mio_out[11],
+ mio_out[10],
+ mio_out[9],
+ mio_out[8],
+ mio_out[7],
+ mio_out[6],
+ mio_out[5],
+ mio_out[4],
+ mio_out[3],
+ mio_out[2],
+ mio_out[1],
+ mio_out[0]
+ }),
+ .mio_oe_i ({
+ mio_oe[33],
+ mio_oe[32],
+ mio_oe[31],
+ mio_oe[30],
+ mio_oe[29],
+ mio_oe[28],
+ mio_oe[27],
+ mio_oe[26],
+ mio_oe[25],
+ mio_oe[24],
+ mio_oe[18],
+ mio_oe[17],
+ mio_oe[16],
+ mio_oe[15],
+ mio_oe[14],
+ mio_oe[13],
+ mio_oe[12],
+ mio_oe[11],
+ mio_oe[10],
+ mio_oe[9],
+ mio_oe[8],
+ mio_oe[7],
+ mio_oe[6],
+ mio_oe[5],
+ mio_oe[4],
+ mio_oe[3],
+ mio_oe[2],
+ mio_oe[1],
+ mio_oe[0]
+ }),
+ .mio_attr_i ({
+ mio_attr[33],
+ mio_attr[32],
+ mio_attr[31],
+ mio_attr[30],
+ mio_attr[29],
+ mio_attr[28],
+ mio_attr[27],
+ mio_attr[26],
+ mio_attr[25],
+ mio_attr[24],
+ mio_attr[18],
+ mio_attr[17],
+ mio_attr[16],
+ mio_attr[15],
+ mio_attr[14],
+ mio_attr[13],
+ mio_attr[12],
+ mio_attr[11],
+ mio_attr[10],
+ mio_attr[9],
+ mio_attr[8],
+ mio_attr[7],
+ mio_attr[6],
+ mio_attr[5],
+ mio_attr[4],
+ mio_attr[3],
+ mio_attr[2],
+ mio_attr[1],
+ mio_attr[0]
+ })
+ );
+
+
+
+
+ /////////////////////
+ // USB Overlay Mux //
+ /////////////////////
+
+ // TODO: generalize this USB mux code and align with other tops.
+
+ // Software can enable the pinflip feature inside usbdev.
+ // The example hello_usbdev does this based on GPIO0 (a switch on the board)
+ //
+ // Here, we use the state of the DN pullup to effectively undo the
+ // swapping such that the PCB always sees the unflipped D+/D-. We
+ // could do the same inside the .xdc file but then two FPGA
+ // bitstreams would be needed for testing.
+ //
+ // dio_in/out/oe map is: PADS <- _padring <- JTAG mux -> _umux -> USB mux -> _core
+
+ // Split out for differential PHY testing
+
+ // Outputs always drive and just copy the value
+ // Let them go to the normal place too because it won't do any harm
+ // and it simplifies the changes needed
+
+ // The output enable for IO_USB_DNPULLUP0 is used to decide whether we need to undo the swapping.
+ logic undo_swap;
+ assign undo_swap = dio_oe[DioUsbdevDnPullup];
+
+ // GPIO[2] = Switch 2 on board is used to select using the UPHY
+ // Keep GPIO[1] for selecting differential in sw
+ logic use_uphy;
+ assign use_uphy = mio_in[MioPadIoa2];
+
+ // DioUsbdevDn
+ assign manual_attr_usb_n = '0;
+ assign manual_attr_io_uphy_dn_tx = '0;
+
+ assign manual_out_io_uphy_dn_tx = manual_out_usb_n;
+ assign manual_out_usb_n = undo_swap ? dio_out[DioUsbdevDp] :
+ dio_out[DioUsbdevDn];
+
+ assign manual_oe_io_uphy_dn_tx = manual_oe_usb_n;
+ assign manual_oe_usb_n = undo_swap ? dio_oe[DioUsbdevDp] :
+ dio_oe[DioUsbdevDn];
+
+ assign dio_in[DioUsbdevDn] = use_uphy ?
+ (undo_swap ? manual_in_io_uphy_dp_rx :
+ manual_in_io_uphy_dn_rx) :
+ (undo_swap ? manual_in_usb_p :
+ manual_in_usb_n);
+ // DioUsbdevDp
+ assign manual_attr_usb_p = '0;
+ assign manual_attr_io_uphy_dp_tx = '0;
+
+ assign manual_out_io_uphy_dp_tx = manual_out_usb_p;
+ assign manual_out_usb_p = undo_swap ? dio_out[DioUsbdevDn] :
+ dio_out[DioUsbdevDp];
+
+ assign manual_oe_io_uphy_dp_tx = manual_oe_usb_p;
+ assign manual_oe_usb_p = undo_swap ? dio_oe[DioUsbdevDn] :
+ dio_oe[DioUsbdevDp];
+ assign dio_in[DioUsbdevDp] = use_uphy ?
+ (undo_swap ? manual_in_io_uphy_dn_rx :
+ manual_in_io_uphy_dp_rx) :
+ (undo_swap ? manual_in_usb_n :
+ manual_in_usb_p);
+ // DioUsbdevD
+ // This is not connected at the moment
+ logic unused_out_usb_d;
+ assign unused_out_usb_d = dio_out[DioUsbdevD] ^
+ dio_oe[DioUsbdevD];
+ assign dio_in[DioUsbdevD] = use_uphy ?
+ (undo_swap ? ~manual_in_io_uphy_d_rx :
+ manual_in_io_uphy_d_rx) :
+ // This is not connected at the moment
+ (undo_swap ? 1'b1 : 1'b0);
+ assign manual_out_io_uphy_d_rx = 1'b0;
+ assign manual_oe_io_uphy_d_rx = 1'b0;
+
+ // DioUsbdevDnPullup
+ assign manual_attr_io_usb_dnpullup0 = '0;
+ assign manual_out_io_usb_dnpullup0 = undo_swap ? dio_out[DioUsbdevDpPullup] :
+ dio_out[DioUsbdevDnPullup];
+ assign manual_oe_io_usb_dnpullup0 = undo_swap ? dio_oe[DioUsbdevDpPullup] :
+ dio_oe[DioUsbdevDnPullup];
+ assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0;
+
+ // DioUsbdevDpPullup
+ assign manual_attr_io_usb_dppullup0 = '0;
+ assign manual_out_io_usb_dppullup0 = undo_swap ? dio_out[DioUsbdevDnPullup] :
+ dio_out[DioUsbdevDpPullup];
+ assign manual_oe_io_usb_dppullup0 = undo_swap ? dio_oe[DioUsbdevDnPullup] :
+ dio_oe[DioUsbdevDpPullup];
+ assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0;
+
+ // DioUsbdevSense
+ assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense];
+ assign manual_oe_io_usb_sense0 = dio_oe[DioUsbdevSense];
+ assign dio_in[DioUsbdevSense] = use_uphy ? manual_in_io_uphy_sense :
+ manual_in_io_usb_sense0;
+ assign manual_out_io_uphy_sense = 1'b0;
+ assign manual_oe_io_uphy_sense = 1'b0;
+
+ // Additional outputs for uphy
+ assign manual_oe_io_uphy_dppullup = 1'b1;
+ assign manual_out_io_uphy_dppullup = manual_out_io_usb_dppullup0 &
+ manual_oe_io_usb_dppullup0;
+
+ logic unused_in_io_uphy_dppullup;
+ assign unused_in_io_uphy_dppullup = manual_in_io_uphy_dppullup;
+
+ assign manual_oe_io_uphy_oe_n = 1'b1;
+ assign manual_out_io_uphy_oe_n = ~manual_oe_usb_p;
+
+ logic unused_in_io_uphy_oe_n;
+ assign unused_in_io_uphy_oe_n = manual_in_io_uphy_oe_n;
+
+
+
+ //////////////////
+ // PLL for FPGA //
+ //////////////////
+
+ assign manual_out_io_clk = 1'b0;
+ assign manual_oe_io_clk = 1'b0;
+ assign manual_out_por_n = 1'b0;
+ assign manual_oe_por_n = 1'b0;
+ assign manual_out_io_jsrst_n = 1'b0;
+ assign manual_oe_io_jsrst_n = 1'b0;
+
+ logic clk_main, clk_usb_48mhz, clk_aon, rst_n;
+ clkgen_xil7series # (
+ .AddClkBuf(0)
+ ) clkgen (
+ .clk_i(manual_in_io_clk),
+ .rst_ni(manual_in_por_n),
+ .jtag_srst_ni(manual_in_io_jsrst_n),
+ .clk_main_o(clk_main),
+ .clk_48MHz_o(clk_usb_48mhz),
+ .clk_aon_o(clk_aon),
+ .rst_no(rst_n)
+ );
+
+ //////////////////////
+ // Top-level design //
+ //////////////////////
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+ ast_pkg::ast_alert_req_t ast_base_alerts;
+ ast_pkg::ast_status_t ast_base_status;
+
+ assign ast_base_pwr.slow_clk_val = 1'b1;
+ assign ast_base_pwr.core_clk_val = 1'b1;
+ assign ast_base_pwr.io_clk_val = 1'b1;
+ assign ast_base_pwr.usb_clk_val = 1'b1;
+ assign ast_base_pwr.main_pok = 1'b1;
+
+ ast_pkg::ast_dif_t silent_alert = '{
+ p: 1'b0,
+ n: 1'b1
+ };
+
+ assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
+
+ // the rst_ni pin only goes to AST
+ // the rest of the logic generates reset based on the 'pok' signal.
+ // for verilator purposes, make these two the same.
+ lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
+
+
+// TODO: align this with ASIC version to minimize the duplication.
+// Also need to add AST simulation and FPGA emulation models for things like entropy source -
+// otherwise Verilator / FPGA will hang.
+ top_earlgrey #(
+ .AesMasking(1'b0),
+ .AesSBoxImpl(aes_pkg::SBoxImplLut),
+ .SecAesStartTriggerDelay(0),
+ .SecAesAllowForcingMasks(1'b0),
+ .SecAesSkipPRNGReseeding(1'b0),
+ .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
+ .OtbnRegFile(otbn_pkg::RegFileFPGA),
+ .OtpCtrlMemInitFile(OtpCtrlMemInitFile),
+ .RomCtrlBootRomInitFile(BootRomInitFile),
+ .IbexRegFile(ibex_pkg::RegFileFPGA),
+ .IbexPipeLine(1),
+ .SramCtrlRetAonInstrExec(0),
+ .SramCtrlMainInstrExec(1),
+ .PinmuxAonTargetCfg(PinmuxTargetCfg)
+ ) top_earlgrey (
+ .rst_ni ( rst_n ),
+ .clk_main_i ( clk_main ),
+ .clk_io_i ( clk_main ),
+ .clk_usb_i ( clk_usb_48mhz ),
+ .clk_aon_i ( clk_aon ),
+ .clks_ast_o ( ),
+ .clk_main_jitter_en_o ( ),
+ .rsts_ast_o ( ),
+ .pwrmgr_ast_req_o ( ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
+ .sensor_ctrl_ast_alert_rsp_o ( ),
+ .sensor_ctrl_ast_status_i ( ast_base_status ),
+ .usbdev_usb_ref_val_o ( ),
+ .usbdev_usb_ref_pulse_o ( ),
+ .ast_edn_req_i ( '0 ),
+ .ast_edn_rsp_o ( ),
+ .flash_bist_enable_i ( lc_ctrl_pkg::Off ),
+ .flash_power_down_h_i ( 1'b0 ),
+ .flash_power_ready_h_i ( 1'b1 ),
+ .ast_clk_byp_req_o ( lc_clk_bypass ),
+ .ast_clk_byp_ack_i ( lc_clk_bypass ),
+
+ .ast_tl_req_o ( ),
+ .ast_tl_rsp_i ( '0 ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
+ .es_rng_req_o ( ),
+ .es_rng_rsp_i ( '0 ),
+ .es_rng_fips_o ( ),
+ .pinmux2ast_o ( ),
+ .ast2pinmux_i ( '0 ),
+
+ // Multiplexed I/O
+ .mio_in_i ( mio_in ),
+ .mio_out_o ( mio_out ),
+ .mio_oe_o ( mio_oe ),
+
+ // Dedicated I/O
+ .dio_in_i ( dio_in ),
+ .dio_out_o ( dio_out ),
+ .dio_oe_o ( dio_oe ),
+
+ // Pad attributes
+ .mio_attr_o ( mio_attr ),
+ .dio_attr_o ( dio_attr ),
+
+ // Memory attributes
+ .ram_1p_cfg_i ( '0 ),
+ .ram_2p_cfg_i ( '0 ),
+ .rom_cfg_i ( '0 ),
+
+ // DFT signals
+ .scan_rst_ni ( 1'b1 ),
+ .scan_en_i ( 1'b0 ),
+ .scanmode_i ( lc_ctrl_pkg::Off )
+ );
+
+
+
+// TODO: change the naming to chip_
+endmodule : top_earlgrey_nexysvideo
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 57bcb35..b83dc34 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -450,31 +450,250 @@
*/
parameter int unsigned TOP_EARLGREY_EFLASH_SIZE_BYTES = 32'h100000;
- // Enumeration for DIO pins.
+
+ // Enumeration of IO power domains.
+ // Only used in ASIC target.
typedef enum {
- TopEarlgreyDioPinUsbdevDn = 0,
- TopEarlgreyDioPinUsbdevDp = 1,
- TopEarlgreyDioPinUsbdevD = 2,
- TopEarlgreyDioPinUsbdevSuspend = 3,
- TopEarlgreyDioPinUsbdevTxModeSe = 4,
- TopEarlgreyDioPinUsbdevDnPullup = 5,
- TopEarlgreyDioPinUsbdevDpPullup = 6,
- TopEarlgreyDioPinUsbdevSe0 = 7,
- TopEarlgreyDioPinUsbdevSense = 8,
- TopEarlgreyDioPinSpiHost0Sd0 = 9,
- TopEarlgreyDioPinSpiHost0Sd1 = 10,
- TopEarlgreyDioPinSpiHost0Sd2 = 11,
- TopEarlgreyDioPinSpiHost0Sd3 = 12,
- TopEarlgreyDioPinSpiHost0Csb = 13,
- TopEarlgreyDioPinSpiHost0Sck = 14,
- TopEarlgreyDioPinSpiDeviceSd0 = 15,
- TopEarlgreyDioPinSpiDeviceSd1 = 16,
- TopEarlgreyDioPinSpiDeviceSd2 = 17,
- TopEarlgreyDioPinSpiDeviceSd3 = 18,
- TopEarlgreyDioPinSpiDeviceCsb = 19,
- TopEarlgreyDioPinSpiDeviceSck = 20,
- TopEarlgreyDioPinCount = 21
- } top_earlgrey_dio_pin_e;
+ IoBankVcc = 0,
+ IoBankAvcc = 1,
+ IoBankVioa = 2,
+ IoBankViob = 3,
+ IoBankCount = 4
+ } pwr_dom_e;
+
+ // Enumeration for MIO signals on the top-level.
+ typedef enum {
+ MioInGpioGpio0 = 0,
+ MioInGpioGpio1 = 1,
+ MioInGpioGpio2 = 2,
+ MioInGpioGpio3 = 3,
+ MioInGpioGpio4 = 4,
+ MioInGpioGpio5 = 5,
+ MioInGpioGpio6 = 6,
+ MioInGpioGpio7 = 7,
+ MioInGpioGpio8 = 8,
+ MioInGpioGpio9 = 9,
+ MioInGpioGpio10 = 10,
+ MioInGpioGpio11 = 11,
+ MioInGpioGpio12 = 12,
+ MioInGpioGpio13 = 13,
+ MioInGpioGpio14 = 14,
+ MioInGpioGpio15 = 15,
+ MioInGpioGpio16 = 16,
+ MioInGpioGpio17 = 17,
+ MioInGpioGpio18 = 18,
+ MioInGpioGpio19 = 19,
+ MioInGpioGpio20 = 20,
+ MioInGpioGpio21 = 21,
+ MioInGpioGpio22 = 22,
+ MioInGpioGpio23 = 23,
+ MioInGpioGpio24 = 24,
+ MioInGpioGpio25 = 25,
+ MioInGpioGpio26 = 26,
+ MioInGpioGpio27 = 27,
+ MioInGpioGpio28 = 28,
+ MioInGpioGpio29 = 29,
+ MioInGpioGpio30 = 30,
+ MioInGpioGpio31 = 31,
+ MioInI2c0Sda = 32,
+ MioInI2c0Scl = 33,
+ MioInI2c1Sda = 34,
+ MioInI2c1Scl = 35,
+ MioInI2c2Sda = 36,
+ MioInI2c2Scl = 37,
+ MioInSpiHost1Sd0 = 38,
+ MioInSpiHost1Sd1 = 39,
+ MioInSpiHost1Sd2 = 40,
+ MioInSpiHost1Sd3 = 41,
+ MioInUart0Rx = 42,
+ MioInUart1Rx = 43,
+ MioInUart2Rx = 44,
+ MioInUart3Rx = 45,
+ MioInFlashCtrlTck = 46,
+ MioInFlashCtrlTms = 47,
+ MioInFlashCtrlTdi = 48,
+ MioInSensorCtrlAonAstDebugIn0 = 49,
+ MioInSensorCtrlAonAstDebugIn1 = 50,
+ MioInSensorCtrlAonAstDebugIn2 = 51,
+ MioInSensorCtrlAonAstDebugIn3 = 52,
+ MioInSensorCtrlAonAstDebugIn4 = 53,
+ MioInSensorCtrlAonAstDebugIn5 = 54,
+ MioInSensorCtrlAonAstDebugIn6 = 55,
+ MioInSensorCtrlAonAstDebugIn7 = 56,
+ MioInSensorCtrlAonAstDebugIn8 = 57,
+ MioInSensorCtrlAonAstDebugIn9 = 58,
+ MioInCount = 59
+ } mio_in_e;
+
+ typedef enum {
+ MioOutGpioGpio0 = 0,
+ MioOutGpioGpio1 = 1,
+ MioOutGpioGpio2 = 2,
+ MioOutGpioGpio3 = 3,
+ MioOutGpioGpio4 = 4,
+ MioOutGpioGpio5 = 5,
+ MioOutGpioGpio6 = 6,
+ MioOutGpioGpio7 = 7,
+ MioOutGpioGpio8 = 8,
+ MioOutGpioGpio9 = 9,
+ MioOutGpioGpio10 = 10,
+ MioOutGpioGpio11 = 11,
+ MioOutGpioGpio12 = 12,
+ MioOutGpioGpio13 = 13,
+ MioOutGpioGpio14 = 14,
+ MioOutGpioGpio15 = 15,
+ MioOutGpioGpio16 = 16,
+ MioOutGpioGpio17 = 17,
+ MioOutGpioGpio18 = 18,
+ MioOutGpioGpio19 = 19,
+ MioOutGpioGpio20 = 20,
+ MioOutGpioGpio21 = 21,
+ MioOutGpioGpio22 = 22,
+ MioOutGpioGpio23 = 23,
+ MioOutGpioGpio24 = 24,
+ MioOutGpioGpio25 = 25,
+ MioOutGpioGpio26 = 26,
+ MioOutGpioGpio27 = 27,
+ MioOutGpioGpio28 = 28,
+ MioOutGpioGpio29 = 29,
+ MioOutGpioGpio30 = 30,
+ MioOutGpioGpio31 = 31,
+ MioOutI2c0Sda = 32,
+ MioOutI2c0Scl = 33,
+ MioOutI2c1Sda = 34,
+ MioOutI2c1Scl = 35,
+ MioOutI2c2Sda = 36,
+ MioOutI2c2Scl = 37,
+ MioOutSpiHost1Sd0 = 38,
+ MioOutSpiHost1Sd1 = 39,
+ MioOutSpiHost1Sd2 = 40,
+ MioOutSpiHost1Sd3 = 41,
+ MioOutUart0Tx = 42,
+ MioOutUart1Tx = 43,
+ MioOutUart2Tx = 44,
+ MioOutUart3Tx = 45,
+ MioOutPattgenPda0Tx = 46,
+ MioOutPattgenPcl0Tx = 47,
+ MioOutPattgenPda1Tx = 48,
+ MioOutPattgenPcl1Tx = 49,
+ MioOutSpiHost1Sck = 50,
+ MioOutSpiHost1Csb = 51,
+ MioOutFlashCtrlTdo = 52,
+ MioOutSensorCtrlAonAstDebugOut0 = 53,
+ MioOutSensorCtrlAonAstDebugOut1 = 54,
+ MioOutSensorCtrlAonAstDebugOut2 = 55,
+ MioOutSensorCtrlAonAstDebugOut3 = 56,
+ MioOutSensorCtrlAonAstDebugOut4 = 57,
+ MioOutSensorCtrlAonAstDebugOut5 = 58,
+ MioOutSensorCtrlAonAstDebugOut6 = 59,
+ MioOutSensorCtrlAonAstDebugOut7 = 60,
+ MioOutSensorCtrlAonAstDebugOut8 = 61,
+ MioOutSensorCtrlAonAstDebugOut9 = 62,
+ MioOutCount = 63
+ } mio_out_e;
+
+ // Enumeration for DIO signals, used on both the top and chip-levels.
+ typedef enum {
+ DioSpiHost0Sd0 = 0,
+ DioSpiHost0Sd1 = 1,
+ DioSpiHost0Sd2 = 2,
+ DioSpiHost0Sd3 = 3,
+ DioSpiDeviceSd0 = 4,
+ DioSpiDeviceSd1 = 5,
+ DioSpiDeviceSd2 = 6,
+ DioSpiDeviceSd3 = 7,
+ DioUsbdevD = 8,
+ DioUsbdevDp = 9,
+ DioUsbdevDn = 10,
+ DioSpiDeviceSck = 11,
+ DioSpiDeviceCsb = 12,
+ DioUsbdevSense = 13,
+ DioSpiHost0Sck = 14,
+ DioSpiHost0Csb = 15,
+ DioUsbdevSe0 = 16,
+ DioUsbdevDpPullup = 17,
+ DioUsbdevDnPullup = 18,
+ DioUsbdevTxModeSe = 19,
+ DioUsbdevSuspend = 20,
+ DioCount = 21
+ } dio_e;
+
+ // Raw MIO/DIO input array indices on chip-level.
+ // TODO: Does not account for target specific stubbed/added pads.
+ // Need to make a target-specific package for those.
+ typedef enum {
+ MioPadIoa0 = 0,
+ MioPadIoa1 = 1,
+ MioPadIoa2 = 2,
+ MioPadIoa3 = 3,
+ MioPadIoa4 = 4,
+ MioPadIoa5 = 5,
+ MioPadIob0 = 6,
+ MioPadIob1 = 7,
+ MioPadIob2 = 8,
+ MioPadIob3 = 9,
+ MioPadIob4 = 10,
+ MioPadIob5 = 11,
+ MioPadIob6 = 12,
+ MioPadIob7 = 13,
+ MioPadIob8 = 14,
+ MioPadIob9 = 15,
+ MioPadIob10 = 16,
+ MioPadIob11 = 17,
+ MioPadIoc0 = 18,
+ MioPadIoc1 = 19,
+ MioPadIoc2 = 20,
+ MioPadIoc3 = 21,
+ MioPadIoc4 = 22,
+ MioPadIoc5 = 23,
+ MioPadIoc6 = 24,
+ MioPadIoc7 = 25,
+ MioPadIoc8 = 26,
+ MioPadIoc9 = 27,
+ MioPadIoc10 = 28,
+ MioPadIoc11 = 29,
+ MioPadIor0 = 30,
+ MioPadIor1 = 31,
+ MioPadIor2 = 32,
+ MioPadIor3 = 33,
+ MioPadIor4 = 34,
+ MioPadIor5 = 35,
+ MioPadIor6 = 36,
+ MioPadIor7 = 37,
+ MioPadIor8 = 38,
+ MioPadIor9 = 39,
+ MioPadIor10 = 40,
+ MioPadIor11 = 41,
+ MioPadIor12 = 42,
+ MioPadIor13 = 43,
+ MioPadCount
+ } mio_pad_e;
+
+ typedef enum {
+ DioPadPorN = 0,
+ DioPadSpiHostD0 = 1,
+ DioPadSpiHostD1 = 2,
+ DioPadSpiHostD2 = 3,
+ DioPadSpiHostD3 = 4,
+ DioPadSpiHostClk = 5,
+ DioPadSpiHostCsL = 6,
+ DioPadSpiDevD0 = 7,
+ DioPadSpiDevD1 = 8,
+ DioPadSpiDevD2 = 9,
+ DioPadSpiDevD3 = 10,
+ DioPadSpiDevClk = 11,
+ DioPadSpiDevCsL = 12,
+ DioPadUsbP = 13,
+ DioPadUsbN = 14,
+ DioPadCc1 = 15,
+ DioPadCc2 = 16,
+ DioPadFlashTestMode0 = 17,
+ DioPadFlashTestMode1 = 18,
+ DioPadFlashTestMode2 = 19,
+ DioPadFlashTestMode3 = 20,
+ DioPadFlashTestVolt = 21,
+ DioPadCount
+ } dio_pad_e;
// TODO: Enumeration for PLIC Interrupt source peripheral.
// TODO: Enumeration for PLIC Interrupt Ids.
diff --git a/hw/top_earlgrey/rtl/clkgen_xil7series.sv b/hw/top_earlgrey/rtl/clkgen_xil7series.sv
index d931b9c..5c3a3f3 100644
--- a/hw/top_earlgrey/rtl/clkgen_xil7series.sv
+++ b/hw/top_earlgrey/rtl/clkgen_xil7series.sv
@@ -6,13 +6,13 @@
// Add BUFG if not done by downstream logic
parameter bit AddClkBuf = 1
) (
- input IO_CLK,
- input IO_RST_N,
- input jtag_srst_n,
- output clk_main,
- output clk_48MHz,
- output clk_aon,
- output rst_n
+ input clk_i,
+ input rst_ni,
+ input jtag_srst_ni,
+ output clk_main_o,
+ output clk_48MHz_o,
+ output clk_aon_o,
+ output rst_no
);
logic locked_pll;
logic io_clk_buf;
@@ -26,18 +26,6 @@
logic clk_aon_buf;
logic clk_aon_unbuf;
- // input clock buffer
- IBUF io_clk_ibuf (
- .I (IO_CLK),
- .O (io_clk_buf)
- );
-
- // input reset buffer
- IBUF io_rst_ibuf (
- .I (IO_RST_N),
- .O (io_rst_buf_n)
- );
-
PLLE2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
@@ -65,7 +53,7 @@
.CLKOUT5 (),
// Input clock control
.CLKFBIN (clk_fb_buf),
- .CLKIN1 (io_clk_buf),
+ .CLKIN1 (clk_i),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
@@ -112,10 +100,10 @@
// outputs
// clock
- assign clk_main = clk_10_buf;
- assign clk_48MHz = clk_48_buf;
- assign clk_aon = clk_aon_buf;
+ assign clk_main_o = clk_10_buf;
+ assign clk_48MHz_o = clk_48_buf;
+ assign clk_aon_o = clk_aon_buf;
// reset
- assign rst_n = locked_pll & io_rst_buf_n & jtag_srst_n;
+ assign rst_no = locked_pll & rst_ni & jtag_srst_ni;
endmodule
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
deleted file mode 100644
index 0fb45bf..0000000
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ /dev/null
@@ -1,746 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_earlgrey_asic (
- // Clock and Reset
- inout POR_N,
- // Bank A (VIOA domain)
- inout SPI_HOST_D0,
- inout SPI_HOST_D1,
- inout SPI_HOST_D2,
- inout SPI_HOST_D3,
- inout SPI_HOST_CLK,
- inout SPI_HOST_CS_L,
- inout SPI_DEV_D0,
- inout SPI_DEV_D1,
- inout SPI_DEV_D2,
- inout SPI_DEV_D3,
- inout SPI_DEV_CLK,
- inout SPI_DEV_CS_L,
- inout IOA0, // MIO 0
- inout IOA1, // MIO 1
- inout IOA2, // MIO 2
- inout IOA3, // MIO 3
- inout IOA4, // MIO 4
- inout IOA5, // MIO 5
- // Bank B (VIOB domain)
- inout IOB0, // MIO 6
- inout IOB1, // MIO 7
- inout IOB2, // MIO 8
- inout IOB3, // MIO 9
- inout IOB4, // MIO 10
- inout IOB5, // MIO 11
- inout IOB6, // MIO 12
- inout IOB7, // MIO 13
- inout IOB8, // MIO 14
- inout IOB9, // MIO 15
- inout IOB10, // MIO 16
- inout IOB11, // MIO 17
- // Bank C (VCC domain)
- inout IOC0, // MIO 18
- inout IOC1, // MIO 19
- inout IOC2, // MIO 20
- inout IOC3, // MIO 21
- inout IOC4, // MIO 22
- inout IOC5, // MIO 23
- inout IOC6, // MIO 24
- inout IOC7, // MIO 25
- inout IOC8, // MIO 26
- inout IOC9, // MIO 27
- inout IOC10, // MIO 28
- inout IOC11, // MIO 29
- // Bank R (VCC domain)
- inout IOR0, // MIO 30
- inout IOR1, // MIO 31
- inout IOR2, // MIO 32
- inout IOR3, // MIO 33
- inout IOR4, // MIO 34
- inout IOR5, // MIO 35
- inout IOR6, // MIO 36
- inout IOR7, // MIO 37
- inout IOR8, // MIO 38
- inout IOR9, // MIO 39
- inout IOR10, // MIO 40
- inout IOR11, // MIO 41
- inout IOR12, // MIO 42
- inout IOR13, // MIO 43
- // DCD (VCC domain)
- inout CC1,
- inout CC2,
- // USB (VCC domain)
- inout USB_P,
- inout USB_N,
- // FLASH
- inout [3:0] FLASH_TEST_MODE,
- inout FLASH_TEST_VOLT
-
-);
-
- import top_earlgrey_pkg::*;
-
- ////////////////////////
- // Signal definitions //
- ////////////////////////
-
- //////////////////////
- // Padring Instance //
- //////////////////////
-
- logic rst_n;
- logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr;
- logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_umux;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_umux;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_umux;
-
- // unused pad signals. need to hook these wires up since lint does not like module ports that are
- // tied to 1'bz.
- wire unused_usbdev_se0, unused_usbdev_tx_mode, unused_usbdev_suspend;
- wire unused_usbdev_d, unused_usbdev_aon_sense;
- wire unused_usbdev_dp_pullup_en, unused_usbdev_dn_pullup_en;
- wire unused_spi_device_s2, unused_spi_device_s3;
- wire unused_clk;
-
- padring #(
- // The clock pad is not connected since
- // AST contains an internal oscillator model.
- .ConnectClk ( 0 ),
- // All MIOs are connected
- .ConnectMioIn ( 44'hFFF_FFFF_FFFF ),
- .ConnectMioOut ( 44'hFFF_FFFF_FFFF ),
- // Tied off DIOs:
- // 2-8 (USB)
- .ConnectDioIn ( 21'h1FFE03 ),
- .ConnectDioOut ( 21'h1FFE03 ),
- // MIO pad types
- .MioPadVariant ( { // RBox
- 2'd3, // IOR13 -- open drain
- 2'd3, // IOR12 -- open drain
- 2'd3, // IOR11 -- open drain
- 2'd3, // IOR10 -- open drain
- 2'd3, // IOR9 -- open drain
- 2'd3, // IOR8 -- open drain
- 2'd0, // IOR7 -- bidir
- 2'd0, // IOR6 -- bidir
- 2'd0, // IOR5 -- bidir
- 2'd0, // IOR4 -- bidir
- 2'd0, // IOR3 -- bidir
- 2'd0, // IOR2 -- bidir
- 2'd0, // IOR1 -- bidir
- 2'd0, // IOR0 -- bidir
- // Bank C
- 2'd3, // IOC11 -- open drain
- 2'd3, // IOC10 -- open drain
- 2'd3, // IOC9 -- open drain
- 2'd3, // IOC8 -- open drain
- 2'd0, // IOC7 -- bidir
- 2'd0, // IOC6 -- bidir
- 2'd0, // IOC5 -- bidir
- 2'd0, // IOC4 -- bidir
- 2'd0, // IOC3 -- bidir
- 2'd0, // IOC2 -- bidir
- 2'd0, // IOC1 -- bidir
- 2'd0, // IOC0 -- bidir
- // Bank B
- 2'd3, // IOB11 -- open drain
- 2'd3, // IOB10 -- open drain
- 2'd3, // IOB9 -- open drain
- 2'd3, // IOB8 -- open drain
- 2'd0, // IOB7 -- birid
- 2'd0, // IOB6 -- birid
- 2'd0, // IOB5 -- birid
- 2'd0, // IOB4 -- birid
- 2'd0, // IOB3 -- bidir
- 2'd0, // IOB2 -- bidir
- 2'd0, // IOB1 -- bidir
- 2'd0, // IOB0 -- bidir
- // Bank A
- 2'd3, // IOA5 -- open drain
- 2'd3, // IOA4 -- open drain
- 2'd0, // IOA3 -- bidir
- 2'd0, // IOA2 -- bidir
- 2'd0, // IOA1 -- bidir
- 2'd0 // IOA0 -- bidir
- } ),
- // DIO pad types
- .DioPadVariant ( { 2'd1, // SPI_DEV_CLK -- input only
- 2'd1, // SPI_DEV_CS_L -- input only
- 2'd0, // SPI_DEV_D3 -- bidir
- 2'd0, // SPI_DEV_D2 -- bidir
- 2'd0, // SPI_DEV_D1 -- bidir
- 2'd0, // SPI_DEV_D0 -- bidir
- 2'd0, // SPI_HOST_CLK -- bidir
- 2'd0, // SPI_HOST_CS_L -- bidir
- 2'd0, // SPI_HOST_D3 -- bidir
- 2'd0, // SPI_HOST_D2 -- bidir
- 2'd0, // SPI_HOST_D1 -- bidir
- 2'd0, // SPI_HOST_D0 -- bidir
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd2, // USB_P -- tolerant
- 2'd2 // USB_N -- tolerant
- } )
- ) u_padring (
- // Clk / Rst
- .clk_pad_i ( unused_clk ),
- .rst_pad_ni ( POR_N ),
- .clk_o ( ),
- .rst_no ( rst_n ),
- .cc1_i ( CC1 ),
- .cc2_i ( CC2 ),
- // "special"
- // MIO Pads
- .mio_pad_io ( { // RBox
- IOR13, // MIO 43
- IOR12, // MIO 42
- IOR11, // MIO 41
- IOR10, // MIO 40
- IOR9, // MIO 39
- IOR8, // MIO 38
- IOR7, // MIO 37
- IOR6, // MIO 36
- IOR5, // MIO 35
- IOR4, // MIO 34
- IOR3, // MIO 33
- IOR2, // MIO 32
- IOR1, // MIO 31
- IOR0, // MIO 30
- // Bank C
- IOC11, // MIO 29
- IOC10, // MIO 28
- IOC9, // MIO 27
- IOC8, // MIO 26
- IOC7, // MIO 25
- IOC6, // MIO 24
- IOC5, // MIO 23
- IOC4, // MIO 22
- IOC3, // MIO 21
- IOC2, // MIO 20
- IOC1, // MIO 19
- IOC0, // MIO 18
- // Bank B
- IOB11, // MIO 17
- IOB10, // MIO 16
- IOB9, // MIO 15
- IOB8, // MIO 14
- IOB7, // MIO 13
- IOB6, // MIO 12
- IOB5, // MIO 11
- IOB4, // MIO 10
- IOB3, // MIO 9
- IOB2, // MIO 8
- IOB1, // MIO 7
- IOB0, // MIO 6
- // Bank A
- IOA5, // MIO 5
- IOA4, // MIO 4
- IOA3, // MIO 3
- IOA2, // MIO 2
- IOA1, // MIO 1
- IOA0 // MIO 0
- } ),
- // DIO Pads
- .dio_pad_io ( { SPI_DEV_CLK, // cio_spi_device_sck_p2d
- SPI_DEV_CS_L, // cio_spi_device_csb_p2d
- SPI_DEV_D3, // cio_spi_device_s_p2d[3]
- SPI_DEV_D2, // cio_spi_device_s_p2d[2]
- SPI_DEV_D1, // cio_spi_device_s_p2d[1]
- SPI_DEV_D0, // cio_spi_device_s_p2d[0]
- SPI_HOST_CLK, // cio_spi_host0_sck_p2d
- SPI_HOST_CS_L, // cio_spi_host0_csb_p2d
- SPI_HOST_D3, // cio_spi_host0_s_p2d[3]
- SPI_HOST_D2, // cio_spi_host0_s_p2d[2]
- SPI_HOST_D1, // cio_spi_host0_s_p2d[1]
- SPI_HOST_D0, // cio_spi_host0_s_p2d[0]
- unused_usbdev_aon_sense, // cio_usbdev_aon_sense_p2d
- unused_usbdev_se0, // cio_usbdev_aon_se0
- unused_usbdev_dp_pullup_en, // cio_usbdev_aon_dp_pullup
- unused_usbdev_dn_pullup_en, // cio_usbdev_aon_dn_pullup
- unused_usbdev_tx_mode, // cio_usbdev_aon_tx_mode_se
- unused_usbdev_suspend, // cio_usbdev_aon_suspend
- unused_usbdev_d, // cio_usbdev_aon_d_p2d
- USB_P, // cio_usbdev_aon_dp_p2d
- USB_N // cio_usbdev_aon_dn_p2d
- } ),
- // Muxed IOs
- .mio_in_o ( mio_in_core ),
- .mio_out_i ( mio_out_core ),
- .mio_oe_i ( mio_oe_core ),
- // Dedicated IOs
- .dio_in_o ( dio_in_umux ),
- .dio_out_i ( dio_out_umux ),
- .dio_oe_i ( dio_oe_umux ),
- // Pad Attributes
- .mio_attr_i ( mio_attr ),
- .dio_attr_i ( dio_attr )
- );
-
-
- /////////////////////
- // USB Overlay Mux //
- /////////////////////
-
- // TODO: generalize this USB mux code and align with other tops.
- logic usbdev_aon_usb_rx_enable;
- logic usb_pullup_p_en;
- logic usb_pullup_n_en;
- logic usb_diff_input;
- logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
-
- assign usb_pullup_p_en = dio_out_core[top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDpPullup] &
- dio_oe_core[top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDpPullup];
- assign usb_pullup_n_en = dio_out_core[top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDnPullup] &
- dio_oe_core[top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDnPullup];
-
- // Input tie-off muxes
- for (genvar k = 0; k < pinmux_reg_pkg::NDioPads; k++) begin : gen_input_tie_off
- if (k == top_earlgrey_pkg::TopEarlgreyDioPinUsbdevD) begin : gen_usb_diff_in
- logic unused_in;
- assign unused_in = dio_in_umux[k];
- assign dio_in_core[k] = usb_diff_input;
- end else begin : gen_other_inputs
- assign dio_in_core[k] = dio_in_umux[k];
- end
- end
-
- assign dio_out_umux = dio_out_core;
- assign dio_oe_umux = dio_oe_core;
-
- //////////////////////
- // AST //
- //////////////////////
- // TLUL interface
- tlul_pkg::tl_h2d_t base_ast_bus;
- tlul_pkg::tl_d2h_t ast_base_bus;
-
- // assorted ast status
- ast_pkg::ast_status_t ast_status;
-
- // ast clocks and resets
- logic aon_pok;
- ast_pkg::ast_clks_t ast_base_clks;
-
- // pwrmgr interface
- pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
- pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
-
- // synchronization clocks / rests
- clkmgr_pkg::clkmgr_ast_out_t clks_ast;
- rstmgr_pkg::rstmgr_ast_out_t rsts_ast;
-
- // otp power sequence
- otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
- otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
-
- logic usb_ref_pulse;
- logic usb_ref_val;
-
- // adc
- // The adc package definition should eventually be moved to the adc module
- ast_pkg::adc_ast_req_t adc_i;
- ast_pkg::adc_ast_rsp_t adc_o;
-
- // entropy source interface
- // The entropy source pacakge definition should eventually be moved to es
- entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
- entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
- logic es_rng_fips;
-
- // entropy distribution network
- edn_pkg::edn_req_t ast_edn_edn_req;
- edn_pkg::edn_rsp_t ast_edn_edn_rsp;
-
- // alerts interface
- ast_pkg::ast_alert_rsp_t ast_alert_rsp;
- ast_pkg::ast_alert_req_t ast_alert_req;
-
- // Flash connections
- lc_ctrl_pkg::lc_tx_t flash_bist_enable;
- logic flash_power_down_h;
- logic flash_power_ready_h;
-
- // Life cycle clock bypass req/ack
- lc_ctrl_pkg::lc_tx_t ast_clk_byp_req;
- lc_ctrl_pkg::lc_tx_t ast_clk_byp_ack;
-
- // DFT connections
- logic scan_rst_n;
- logic scan_en;
- lc_ctrl_pkg::lc_tx_t scanmode;
- lc_ctrl_pkg::lc_tx_t dft_en;
- pinmux_pkg::dft_strap_test_req_t dft_strap_test;
-
- // Debug connections
- logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
- logic [ast_pkg::Pad2AstInWidth-1:0] pinmux2ast;
-
- // Jitter enable
- logic jen;
-
- // Alert connections
- import sensor_ctrl_reg_pkg::AsSel;
- import sensor_ctrl_reg_pkg::CgSel;
- import sensor_ctrl_reg_pkg::GdSel;
- import sensor_ctrl_reg_pkg::TsHiSel;
- import sensor_ctrl_reg_pkg::TsLoSel;
- import sensor_ctrl_reg_pkg::LsSel;
- import sensor_ctrl_reg_pkg::OtSel;
-
- // reset domain connections
- import rstmgr_pkg::PowerDomains;
- import rstmgr_pkg::DomainAonSel;
- import rstmgr_pkg::Domain0Sel;
-
- // adc connections
- ast_pkg::adc_ast_req_t adc_req;
- ast_pkg::adc_ast_rsp_t adc_rsp;
-
- // TODO: need to mux the external clock.
- logic ext_clk;
- assign ext_clk = 1'b0;
-
- // Memory configuration connections
- ast_pkg::spm_rm_t ast_ram_1p_cfg;
- ast_pkg::spm_rm_t ast_rf_cfg;
- ast_pkg::spm_rm_t ast_rom_cfg;
- ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
- ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
-
- prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
- prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
- prim_rom_pkg::rom_cfg_t rom_cfg;
-
- // conversion from ast structure to memory centric structures
- assign ram_1p_cfg = '{
- ram_cfg: '{
- cfg_en: ast_ram_1p_cfg.marg_en,
- cfg: ast_ram_1p_cfg.marg
- },
- rf_cfg: '{
- cfg_en: ast_rf_cfg.marg_en,
- cfg: ast_rf_cfg.marg
- }
- };
-
- assign ram_2p_cfg = '{
- a_ram_fcfg: '{
- cfg_en: ast_ram_2p_fcfg.marg_en_a,
- cfg: ast_ram_2p_fcfg.marg_a
- },
- a_ram_lcfg: '{
- cfg_en: ast_ram_2p_lcfg.marg_en_a,
- cfg: ast_ram_2p_lcfg.marg_a
- },
- b_ram_fcfg: '{
- cfg_en: ast_ram_2p_fcfg.marg_en_b,
- cfg: ast_ram_2p_fcfg.marg_b
- },
- b_ram_lcfg: '{
- cfg_en: ast_ram_2p_lcfg.marg_en_b,
- cfg: ast_ram_2p_lcfg.marg_b
- }
- };
-
- assign rom_cfg = '{
- cfg_en: ast_rom_cfg.marg_en,
- cfg: ast_rom_cfg.marg
- };
-
-
- // AST does not use all clocks / resets forwarded to it
- logic unused_slow_clk_en;
- logic unused_usb_clk_aon;
- logic unused_usb_clk_io_div4;
- assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
- assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri;
- assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri;
-
- logic unused_usb_usb_rst;
- logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst;
- logic [PowerDomains-1:0] unused_usb_sys_aon_rst;
- logic unused_ast_sys_io_div4_rst;
- logic unused_sensor_ctrl_sys_io_div4_rst;
- logic unused_adc_ctrl_sys_io_div4_rst;
- logic unused_entropy_sys_rst;
- logic unused_edn_sys_rst;
- assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel];
- assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n;
- assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n;
- assign unused_ast_sys_io_div4_rst =
- rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel];
- assign unused_sensor_ctrl_sys_io_div4_rst =
- rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[Domain0Sel];
- assign unused_adc_ctrl_sys_io_div4_rst =
- rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[Domain0Sel];
- assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel];
- assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel];
-
-
- ast #(
- .EntropyStreams(top_pkg::ENTROPY_STREAM),
- .AdcChannels(top_pkg::ADC_CHANNELS),
- .AdcDataWidth(top_pkg::ADC_DATAW),
- .UsbCalibWidth(ast_pkg::UsbCalibWidth),
- .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
- .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
- ) u_ast (
- // tlul
- .tl_i ( base_ast_bus ),
- .tl_o ( ast_base_bus ),
- // buffered clocks & resets
- // Reset domain connection is manual at the moment
- .clk_ast_adc_i ( clks_ast.clk_ast_adc_ctrl_aon_io_div4_peri ),
- .rst_ast_adc_ni ( rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
- .clk_ast_alert_i ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ),
- .rst_ast_alert_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
- .clk_ast_es_i ( clks_ast.clk_ast_edn0_main_secure ),
- .rst_ast_es_ni ( rsts_ast.rst_ast_edn0_sys_n[Domain0Sel] ),
- .clk_ast_rng_i ( clks_ast.clk_ast_entropy_src_main_secure ),
- .rst_ast_rng_ni ( rsts_ast.rst_ast_entropy_src_sys_n[Domain0Sel] ),
- .clk_ast_tlul_i ( clks_ast.clk_ast_ast_io_div4_secure ),
- .rst_ast_tlul_ni ( rsts_ast.rst_ast_ast_sys_io_div4_n[DomainAonSel] ),
- .clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ),
- .rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ),
- .clk_ast_ext_i ( ext_clk ),
- .por_ni ( rst_n ),
- // pok test for FPGA
- .vcc_supp_i ( 1'b1 ),
- .vcaon_supp_i ( 1'b1 ),
- .vcmain_supp_i ( 1'b1 ),
- .vioa_supp_i ( 1'b1 ),
- .viob_supp_i ( 1'b1 ),
- // pok
- .vcaon_pok_o ( aon_pok ),
- .vcmain_pok_o ( ast_base_pwr.main_pok ),
- .vioa_pok_o ( ast_status.io_pok[0] ),
- .viob_pok_o ( ast_status.io_pok[1] ),
- // main regulator
- .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
- .main_pd_ni ( base_ast_pwr.main_pd_n ),
- // pdm control (flash)/otp
- .flash_power_down_h_o ( flash_power_down_h ),
- .flash_power_ready_h_o ( flash_power_ready_h ),
- .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
- .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
- // system source clock
- .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
- // need to add function in clkmgr
- .clk_src_sys_jen_i ( jen ),
- .clk_src_sys_o ( ast_base_clks.clk_sys ),
- .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
- // aon source clock
- .clk_src_aon_o ( ast_base_clks.clk_aon ),
- .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
- // io source clock
- .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
- .clk_src_io_o ( ast_base_clks.clk_io ),
- .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
- // usb source clock
- .usb_ref_pulse_i ( usb_ref_pulse ),
- .usb_ref_val_i ( usb_ref_val ),
- .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
- .clk_src_usb_o ( ast_base_clks.clk_usb ),
- .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
- // USB IO Pull-up Calibration Setting
- .usb_io_pu_cal_o ( usb_io_pu_cal ),
- // adc
- .adc_a0_ai ( CC1 ),
- .adc_a1_ai ( CC2 ),
- .adc_pd_i ( adc_req.pd ),
- .adc_chnsel_i ( adc_req.channel_sel ),
- .adc_d_o ( adc_rsp.data ),
- .adc_d_val_o ( adc_rsp.data_valid ),
- // rng
- .rng_en_i ( es_rng_req.rng_enable ),
- .rng_fips_i ( es_rng_fips ),
- .rng_val_o ( es_rng_rsp.rng_valid ),
- .rng_b_o ( es_rng_rsp.rng_b ),
- // entropy
- .entropy_rsp_i ( ast_edn_edn_rsp ),
- .entropy_req_o ( ast_edn_edn_req ),
- // alerts
- .as_alert_trig_i ( ast_alert_rsp.alerts_trig[AsSel] ),
- .as_alert_ack_i ( ast_alert_rsp.alerts_ack[AsSel] ),
- .as_alert_o ( ast_alert_req.alerts[AsSel] ),
- .cg_alert_trig_i ( ast_alert_rsp.alerts_trig[CgSel] ),
- .cg_alert_ack_i ( ast_alert_rsp.alerts_ack[CgSel] ),
- .cg_alert_o ( ast_alert_req.alerts[CgSel] ),
- .gd_alert_trig_i ( ast_alert_rsp.alerts_trig[GdSel] ),
- .gd_alert_ack_i ( ast_alert_rsp.alerts_ack[GdSel] ),
- .gd_alert_o ( ast_alert_req.alerts[GdSel] ),
- .ts_alert_hi_trig_i ( ast_alert_rsp.alerts_trig[TsHiSel] ),
- .ts_alert_hi_ack_i ( ast_alert_rsp.alerts_ack[TsHiSel] ),
- .ts_alert_hi_o ( ast_alert_req.alerts[TsHiSel] ),
- .ts_alert_lo_trig_i ( ast_alert_rsp.alerts_trig[TsLoSel] ),
- .ts_alert_lo_ack_i ( ast_alert_rsp.alerts_ack[TsLoSel] ),
- .ts_alert_lo_o ( ast_alert_req.alerts[TsLoSel] ),
- .ls_alert_trig_i ( ast_alert_rsp.alerts_trig[LsSel] ),
- .ls_alert_ack_i ( ast_alert_rsp.alerts_ack[LsSel] ),
- .ls_alert_o ( ast_alert_req.alerts[LsSel] ),
- .ot_alert_trig_i ( ast_alert_rsp.alerts_trig[OtSel] ),
- .ot_alert_ack_i ( ast_alert_rsp.alerts_ack[OtSel] ),
- .ot_alert_o ( ast_alert_req.alerts[OtSel] ),
- // dft
- .dft_strap_test_i ( dft_strap_test ),
- .lc_dft_en_i ( dft_en ),
- // pinmux related
- .padmux2ast_i ( pinmux2ast ),
- .ast2padmux_o ( ast2pinmux ),
- // Direct short to PAD
- .pad2ast_t0_ai ( IOA4 ),
- .pad2ast_t1_ai ( IOA5 ),
- .ast2pad_t0_ao ( IOA2 ),
- .ast2pad_t1_ao ( IOA3 ),
- .lc_clk_byp_req_i ( ast_clk_byp_req ),
- .lc_clk_byp_ack_o ( ast_clk_byp_ack ),
- .flash_bist_en_o ( flash_bist_enable ),
- // Memory configuration connections
- .dpram_rmf_o ( ast_ram_2p_fcfg ),
- .dpram_rml_o ( ast_ram_2p_lcfg ),
- .spram_rm_o ( ast_ram_1p_cfg ),
- .sprgf_rm_o ( ast_rf_cfg ),
- .sprom_rm_o ( ast_rom_cfg ),
- // scan
- .dft_scan_md_o ( scanmode ),
- .scan_shift_en_o ( scan_en ),
- .scan_reset_no ( scan_rst_n )
- );
-
- ///////////////////////////////
- // Differential USB Receiver //
- ///////////////////////////////
-
- // TODO: overhaul these USB connections
- assign usbdev_aon_usb_rx_enable = 1'b0;
-
- prim_usb_diff_rx #(
- .CalibW(ast_pkg::UsbCalibWidth)
- ) u_prim_usb_diff_rx (
- .input_pi ( USB_P ),
- .input_ni ( USB_N ),
- .input_en_i ( usbdev_aon_usb_rx_enable ),
- .core_pok_i ( ast_base_pwr.main_pok ),
- .pullup_p_en_i ( usb_pullup_p_en ),
- .pullup_n_en_i ( usb_pullup_n_en ),
- .calibration_i ( usb_io_pu_cal ),
- .input_o ( usb_diff_input )
- );
-
- //////////////////////
- // Top-level design //
- //////////////////////
-
- // TODO: this is temporary and will be removed in the future.
- // This specifies the tie-off values of the muxed MIO/DIOs
- // when the JTAG is active. SPI CSB is active low.
- localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << (
- pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb));
-
- // DFT and Debug signal positions in the pinout.
- // TODO: generate these indices from the target-specific
- // pinout configuration.
- localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
- const_sampling: 1'b1,
- tie_offs: TieOffValues,
- tck_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSck,
- tms_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb,
- trst_idx: 18, // MIO 18
- tdi_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSd0,
- tdo_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSd1,
- tap_strap0_idx: 26, // MIO 26
- tap_strap1_idx: 23, // MIO 23
- dft_strap0_idx: 21, // MIO 21
- dft_strap1_idx: 22 // MIO 22
- };
-
- top_earlgrey #(
- .AesMasking(1'b1),
- .AesSBoxImpl(aes_pkg::SBoxImplDom),
- .SecAesStartTriggerDelay(0),
- .SecAesAllowForcingMasks(1'b0),
- .KmacEnMasking(1), // DOM AND + Masking scheme
- .KmacReuseShare(0),
- .SramCtrlRetAonInstrExec(0),
- .SramCtrlMainInstrExec(1),
- .PinmuxAonTargetCfg(PinmuxTargetCfg)
- ) top_earlgrey (
- .rst_ni ( aon_pok ),
- // ast connections
- .clk_main_i ( ast_base_clks.clk_sys ),
- .clk_io_i ( ast_base_clks.clk_io ),
- .clk_usb_i ( ast_base_clks.clk_usb ),
- .clk_aon_i ( ast_base_clks.clk_aon ),
- .clks_ast_o ( clks_ast ),
- .clk_main_jitter_en_o ( jen ),
- .rsts_ast_o ( rsts_ast ),
- .pwrmgr_ast_req_o ( base_ast_pwr ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
- .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
- .sensor_ctrl_ast_status_i ( ast_status ),
- .usbdev_usb_ref_val_o ( usb_ref_pulse ),
- .usbdev_usb_ref_pulse_o ( usb_ref_val ),
- .ast_tl_req_o ( base_ast_bus ),
- .ast_tl_rsp_i ( ast_base_bus ),
- .adc_req_o ( adc_req ),
- .adc_rsp_i ( adc_rsp ),
- .ast_edn_req_i ( ast_edn_edn_req ),
- .ast_edn_rsp_o ( ast_edn_edn_rsp ),
- .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
- .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
- .flash_bist_enable_i ( flash_bist_enable ),
- .flash_power_down_h_i ( flash_power_down_h ),
- .flash_power_ready_h_i ( flash_power_ready_h ),
- .es_rng_req_o ( es_rng_req ),
- .es_rng_rsp_i ( es_rng_rsp ),
- .es_rng_fips_o ( es_rng_fips ),
- .ast_clk_byp_req_o ( ast_clk_byp_req ),
- .ast_clk_byp_ack_i ( ast_clk_byp_ack ),
- .pinmux2ast_o ( pinmux2ast ),
- .ast2pinmux_i ( ast2pinmux ),
-
- // Flash test mode voltages
- .flash_test_mode_a_io ( FLASH_TEST_MODE ),
- .flash_test_voltage_h_io ( FLASH_TEST_VOLT ),
-
- // Multiplexed I/O
- .mio_in_i ( mio_in_core ),
- .mio_out_o ( mio_out_core ),
- .mio_oe_o ( mio_oe_core ),
-
- // Dedicated I/O
- .dio_in_i ( dio_in_core ),
- .dio_out_o ( dio_out_core ),
- .dio_oe_o ( dio_oe_core ),
-
- // Pad attributes
- .mio_attr_o ( mio_attr ),
- .dio_attr_o ( dio_attr ),
-
- // Memory attributes
- .ram_1p_cfg_i ( ram_1p_cfg ),
- .ram_2p_cfg_i ( ram_2p_cfg ),
- .rom_cfg_i ( rom_cfg ),
-
- // DFT signals
- .ast_lc_dft_en_o ( dft_en ),
- .dft_strap_test_o ( dft_strap_test ),
- .scan_rst_ni ( scan_rst_n ),
- .scan_en_i ( scan_en ),
- .scanmode_i ( scanmode )
- );
-
-endmodule : top_earlgrey_asic
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
deleted file mode 100644
index b6d89fe..0000000
--- a/hw/top_earlgrey/rtl/top_earlgrey_nexysvideo.sv
+++ /dev/null
@@ -1,516 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_earlgrey_nexysvideo #(
- // Path to a VMEM file containing the contents of the boot ROM, which will be
- // baked into the FPGA bitstream.
- parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem",
- // Path to a VMEM file containing the contents of the emulated OTP, which will be
- // baked into the FPGA bitstream.
- parameter OtpCtrlMemInitFile = "otp_img_fpga_nexysvideo.vmem"
-) (
- // Clock and Reset
- input IO_CLK,
- input IO_RST_N,
- // JTAG interface
- inout IO_DPS0, // IO_JTCK, IO_SDCK
- inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDSDI
- inout IO_DPS4, // IO_JTRST_N,
- inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_SDO
- inout IO_DPS6, // JTAG=1, SPI=0
- inout IO_DPS7, // BOOTSTRAP=1
- // UART interface
- inout IO_URX,
- inout IO_UTX,
- // USB interface
- inout IO_USB_DP0,
- inout IO_USB_DN0,
- inout IO_USB_SENSE0,
- inout IO_USB_DNPULLUP0,
- inout IO_USB_DPPULLUP0,
- // USB interface for testing with TI1106 USB PHY
- output IO_UPHY_DP_TX,
- output IO_UPHY_DN_TX,
- input IO_UPHY_DP_RX,
- input IO_UPHY_DN_RX,
- input IO_UPHY_D_RX,
- output IO_UPHY_OE_N,
- input IO_UPHY_SENSE,
- output IO_UPHY_DPPULLUP,
- // GPIO x 16 interface
- inout IO_GP0,
- inout IO_GP1,
- inout IO_GP2,
- inout IO_GP3,
- inout IO_GP4,
- inout IO_GP5,
- inout IO_GP6,
- inout IO_GP7,
- inout IO_GP8,
- inout IO_GP9,
- inout IO_GP10,
- inout IO_GP11,
- inout IO_GP12,
- inout IO_GP13,
- inout IO_GP14,
- inout IO_GP15,
- // GPIOs going to PMOD JA
- inout IO_GP24,
- inout IO_GP25,
- inout IO_GP26,
- inout IO_GP27,
- inout IO_GP28,
- inout IO_GP29,
- inout IO_GP30,
- inout IO_GP31
-);
-
- import top_earlgrey_pkg::*;
-
- //////////////////////
- // Padring Instance //
- //////////////////////
-
-
- logic clk_main, clk_usb_48mhz, clk_aon, rst_n;
- logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr;
- logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core, dio_out_umux;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core, dio_oe_umux;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core, dio_in_umux;
-
- padring #(
- // MIOs 43:34 and 23:20 are currently not
- // connected to pads and hence tied off
- .ConnectMioIn ( 44'h003_FF0F_FFFF ),
- .ConnectMioOut ( 44'h003_FF0F_FFFF ),
- // Tied off DIOs:
- // 2: usbdev_d
- // 3: usbdev_suspend
- // 4: usbdev_tx_mode
- // 7: usbdev_se
- // 9-14: spi_host all signals
- // 17-18: spi_device unused quad signals
- .ConnectDioIn ( 21'h19_8163 ),
- .ConnectDioOut ( 21'h19_8163 ),
- // MIO pad types
- .MioPadVariant ( { // RBox
- 2'd3, // IOR13 -- open drain
- 2'd3, // IOR12 -- open drain
- 2'd3, // IOR11 -- open drain
- 2'd3, // IOR10 -- open drain
- 2'd3, // IOR9 -- open drain
- 2'd3, // IOR8 -- open drain
- 2'd0, // IOR7 -- bidir
- 2'd0, // IOR6 -- bidir
- 2'd0, // IOR5 -- bidir
- 2'd0, // IOR4 -- bidir
- 2'd0, // IOR3 -- bidir
- 2'd0, // IOR2 -- bidir
- 2'd0, // IOR1 -- bidir
- 2'd0, // IOR0 -- bidir
- // Bank C
- 2'd3, // IOC11 -- open drain
- 2'd3, // IOC10 -- open drain
- 2'd3, // IOC9 -- open drain
- 2'd3, // IOC8 -- open drain
- 2'd0, // IOC7 -- bidir
- 2'd0, // IOC6 -- bidir
- 2'd0, // IOC5 -- bidir
- 2'd0, // IOC4 -- bidir
- 2'd0, // IOC3 -- bidir
- 2'd0, // IOC2 -- bidir
- 2'd0, // IOC1 -- bidir
- 2'd0, // IOC0 -- bidir
- // Bank B
- 2'd3, // IOB11 -- open drain
- 2'd3, // IOB10 -- open drain
- 2'd3, // IOB9 -- open drain
- 2'd3, // IOB8 -- open drain
- 2'd0, // IOB7 -- birid
- 2'd0, // IOB6 -- birid
- 2'd0, // IOB5 -- birid
- 2'd0, // IOB4 -- birid
- 2'd0, // IOB3 -- bidir
- 2'd0, // IOB2 -- bidir
- 2'd0, // IOB1 -- bidir
- 2'd0, // IOB0 -- bidir
- // Bank A
- 2'd3, // IOA5 -- open drain
- 2'd3, // IOA4 -- open drain
- 2'd0, // IOA3 -- bidir
- 2'd0, // IOA2 -- bidir
- 2'd0, // IOA1 -- bidir
- 2'd0 // IOA0 -- bidir
- } ),
- // DIO pad types
- .DioPadVariant ( { 2'd1, // SPI_DEV_CLK -- input only
- 2'd1, // SPI_DEV_CS_L -- input only
- 2'd0, // SPI_DEV_D3 -- bidir
- 2'd0, // SPI_DEV_D2 -- bidir
- 2'd0, // SPI_DEV_D1 -- bidir
- 2'd0, // SPI_DEV_D0 -- bidir
- 2'd0, // SPI_HOST_CLK -- bidir
- 2'd0, // SPI_HOST_CS_L -- bidir
- 2'd0, // SPI_HOST_D3 -- bidir
- 2'd0, // SPI_HOST_D2 -- bidir
- 2'd0, // SPI_HOST_D1 -- bidir
- 2'd0, // SPI_HOST_D0 -- bidir
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd2, // USB_P -- tolerant
- 2'd2 // USB_N -- tolerant
- } )
- ) padring (
- // Clk / Rst
- .clk_pad_i ( 1'b0 ),
- .rst_pad_ni ( 1'b0 ),
- .clk_o ( ),
- .rst_no ( ),
- .cc1_i ( 1'b0 ),
- .cc2_i ( 1'b0 ),
- // MIO Pads
- .mio_pad_io ( { 10'bz, // Note that 43:34 are currently not mapped
- IO_UTX,
- IO_URX,
- IO_GP31,
- IO_GP30,
- IO_GP29,
- IO_GP28,
- IO_GP27,
- IO_GP26,
- IO_GP25,
- IO_GP24,
- 4'bz, // Note that 23:20 are currently not mapped
- IO_DPS5, // Use GPIO19 to pass JTAG_SRST
- IO_DPS4, // Use GPIO18 to pass JTAG_TRST
- IO_DPS7, // Use GPIO17 to pass rom boot_strap indication
- IO_DPS6, // Use GPIO16 to pass SPI/JTAG control flag
- IO_GP15,
- IO_GP14,
- IO_GP13,
- IO_GP12,
- IO_GP11,
- IO_GP10,
- IO_GP9,
- IO_GP8,
- IO_GP7,
- IO_GP6,
- IO_GP5,
- IO_GP4,
- IO_GP3,
- IO_GP2,
- IO_GP1,
- IO_GP0 } ),
- // DIO Pads
- .dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
- IO_DPS3, // CSB, JTAG_TMS
- 2'bz, // quad SPI device signals are not mapped
- IO_DPS2, // SDO, JTAG_TDO
- IO_DPS1, // SDI, JTAG_TDI
- 6'bz, // SPI host signals are not mapped
- IO_USB_SENSE0,
- 1'bz, // usbdev_se0
- IO_USB_DPPULLUP0,
- IO_USB_DNPULLUP0,
- 1'bz, // usbdev_tx_mode
- 1'bz, // usbdev_suspend
- 1'bz, // usbdev_d
- IO_USB_DP0,
- IO_USB_DN0 } ),
- // Muxed IOs
- .mio_in_o ( mio_in_core ),
- .mio_out_i ( mio_out_core ),
- .mio_oe_i ( mio_oe_core ),
- // Dedicated IOs
- .dio_in_o ( dio_in_umux ),
- .dio_out_i ( dio_out_umux ),
- .dio_oe_i ( dio_oe_umux ),
- // Pad Attributes
- .mio_attr_i ( mio_attr ),
- .dio_attr_i ( dio_attr )
- );
-
-
- /////////////////////
- // USB Overlay Mux //
- /////////////////////
-
- // TODO: generalize this USB mux code and align with other tops.
-
- // Software can enable the pinflip feature inside usbdev.
- // The example hello_usbdev does this based on GPIO0 (a switch on the board)
- //
- // Here, we use the state of the DN pullup to effectively undo the
- // swapping such that the PCB always sees the unflipped D+/D-. We
- // could do the same inside the .xdc file but then two FPGA
- // bitstreams would be needed for testing.
- //
- // dio_in/out/oe map is: PADS <- _padring <- JTAG mux -> _umux -> USB mux -> _core
- localparam int DioIdxUsbDn0 = top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDn;
- localparam int DioIdxUsbDp0 = top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDp;
- localparam int DioIdxUsbD0 = top_earlgrey_pkg::TopEarlgreyDioPinUsbdevD;
- localparam int DioIdxUsbSense0 = top_earlgrey_pkg::TopEarlgreyDioPinUsbdevSense;
- localparam int DioIdxUsbDnPullup0 = top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDnPullup;
- localparam int DioIdxUsbDpPullup0 = top_earlgrey_pkg::TopEarlgreyDioPinUsbdevDpPullup;
-
-
- // Split out for differential PHY testing
-
- // Outputs always drive and just copy the value
- // Let them go to the normal place too because it won't do any harm
- // and it simplifies the changes needed
- OBUF o_uphy_dp (
- .O (IO_UPHY_DP_TX),
- .I (dio_out_umux[DioIdxUsbDp0])
- );
- OBUF o_uphy_dn (
- .O (IO_UPHY_DN_TX),
- .I (dio_out_umux[DioIdxUsbDn0])
- );
- OBUF o_uphy_pu (
- .O (IO_UPHY_DPPULLUP),
- .I (dio_out_umux[DioIdxUsbDpPullup0] & dio_oe_umux[DioIdxUsbDpPullup0])
- );
- OBUF o_uphy_oe_N (
- .O (IO_UPHY_OE_N),
- .I (~dio_oe_umux[DioIdxUsbDp0])
- );
-
- // Input: pull to local signals and mux in loop below
- logic uphy_dp_rx, uphy_dn_rx, uphy_d_rx, uphy_sense;
-
- IBUF i_uphy_dp (
- .I (IO_UPHY_DP_RX),
- .O (uphy_dp_rx)
- );
- IBUF i_uphy_dn (
- .I (IO_UPHY_DN_RX),
- .O (uphy_dn_rx)
- );
- IBUF i_uphy_d (
- .I (IO_UPHY_D_RX),
- .O (uphy_d_rx)
- );
- IBUF i_uphy_sense (
- .I (IO_UPHY_SENSE),
- .O (uphy_sense)
- );
-
-
- // The output enable for IO_USB_DNPULLUP0 is used to decide whether we need to undo the swapping.
- logic undo_swap;
- assign undo_swap = dio_oe_core[DioIdxUsbDnPullup0];
-
- // GPIO[2] = Switch 2 on board is used to select using the UPHY
- // Keep GPIO[1] for selecting differential in sw
- logic use_uphy;
- assign use_uphy = mio_in_core[2];
-
- for (genvar i = 0; i < pinmux_reg_pkg::NDioPads; i++) begin : gen_dio
- if (i == DioIdxUsbDn0) begin
- assign dio_out_umux[i] = undo_swap ? dio_out_core[DioIdxUsbDp0] :
- dio_out_core[DioIdxUsbDn0];
- assign dio_oe_umux[i] = undo_swap ? dio_oe_core[DioIdxUsbDp0] :
- dio_oe_core[DioIdxUsbDn0];
- assign dio_in_core[i] = use_uphy ?
- (undo_swap ? uphy_dp_rx : uphy_dn_rx) :
- (undo_swap ? dio_in_umux[DioIdxUsbDp0] :
- dio_in_umux[DioIdxUsbDn0]);
- end else if (i == DioIdxUsbDp0) begin
- assign dio_out_umux[i] = undo_swap ? dio_out_core[DioIdxUsbDn0] :
- dio_out_core[DioIdxUsbDp0];
- assign dio_oe_umux[i] = undo_swap ? dio_oe_core[DioIdxUsbDn0] :
- dio_oe_core[DioIdxUsbDp0];
- assign dio_in_core[i] = use_uphy ?
- (undo_swap ? uphy_dn_rx : uphy_dp_rx) :
- (undo_swap ? dio_in_umux[DioIdxUsbDn0] :
- dio_in_umux[DioIdxUsbDp0]);
- end else if (i == DioIdxUsbD0) begin
- assign dio_out_umux[i] = undo_swap ? ~dio_out_core[DioIdxUsbD0] :
- dio_out_core[DioIdxUsbD0];
- assign dio_oe_umux[i] = dio_oe_core[i];
- assign dio_in_core[i] = use_uphy ?
- (undo_swap ? ~uphy_d_rx : uphy_d_rx) :
- (undo_swap ? ~dio_in_umux[DioIdxUsbD0] :
- dio_in_umux[DioIdxUsbD0]);
- end else if (i == DioIdxUsbDnPullup0) begin
- assign dio_out_umux[i] = undo_swap ? dio_out_core[DioIdxUsbDpPullup0] :
- dio_out_core[DioIdxUsbDnPullup0];
- assign dio_oe_umux[i] = undo_swap ? dio_oe_core[DioIdxUsbDpPullup0] :
- dio_oe_core[DioIdxUsbDnPullup0];
- assign dio_in_core[i] = dio_in_umux[i];
- end else if (i == DioIdxUsbDpPullup0) begin
- assign dio_out_umux[i] = undo_swap ? dio_out_core[DioIdxUsbDnPullup0] :
- dio_out_core[DioIdxUsbDpPullup0];
- assign dio_oe_umux[i] = undo_swap ? dio_oe_core[DioIdxUsbDnPullup0] :
- dio_oe_core[DioIdxUsbDpPullup0];
- assign dio_in_core[i] = dio_in_umux[i];
- end else if (i == DioIdxUsbSense0) begin
- assign dio_out_umux[i] = dio_out_core[i];
- assign dio_oe_umux[i] = dio_oe_core[i];
- assign dio_in_core[i] = use_uphy ? uphy_sense : dio_in_umux[i];
- end else begin
- assign dio_out_umux[i] = dio_out_core[i];
- assign dio_oe_umux[i] = dio_oe_core[i];
- assign dio_in_core[i] = dio_in_umux[i];
- end
- end
-
- //////////////////
- // PLL for FPGA //
- //////////////////
-
- // TODO: This needs to become a dedicated custom pin for FPGAs
- logic jtag_srst_n;
- assign jtag_srst_n = mio_in_core[19];
-
- clkgen_xil7series # (
- .AddClkBuf(0)
- ) clkgen (
- .IO_CLK,
- .IO_RST_N,
- .jtag_srst_n,
- .clk_main(clk_main),
- .clk_48MHz(clk_usb_48mhz),
- .clk_aon(clk_aon),
- .rst_n(rst_n)
- );
-
- //////////////////////
- // Top-level design //
- //////////////////////
- pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
- ast_pkg::ast_alert_req_t ast_base_alerts;
- ast_pkg::ast_status_t ast_base_status;
-
- assign ast_base_pwr.slow_clk_val = 1'b1;
- assign ast_base_pwr.core_clk_val = 1'b1;
- assign ast_base_pwr.io_clk_val = 1'b1;
- assign ast_base_pwr.usb_clk_val = 1'b1;
- assign ast_base_pwr.main_pok = 1'b1;
-
- ast_pkg::ast_dif_t silent_alert = '{
- p: 1'b0,
- n: 1'b1
- };
-
- assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
- assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
-
- // the rst_ni pin only goes to AST
- // the rest of the logic generates reset based on the 'pok' signal.
- // for verilator purposes, make these two the same.
- lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
-
- // TODO: this is temporary and will be removed in the future.
- // This specifies the tie-off values of the muxed MIO/DIOs
- // when the JTAG is active. SPI CSB is active low.
- localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << (
- pinmux_reg_pkg::NMioPads + top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb));
-
- // DFT and Debug signal positions in the pinout.
- // TODO: generate these indices from the target-specific
- // pinout configuration.
- localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
- const_sampling: 1'b1,
- tie_offs: TieOffValues,
- tck_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSck,
- tms_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb,
- trst_idx: 18, // MIO 18
- tdi_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSd0,
- tdo_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSd1,
- tap_strap0_idx: 20, // MIO 20 (tied off)
- tap_strap1_idx: 16, // MIO 16 (used as JTAG/SPI select signal)
- dft_strap0_idx: 21, // MIO 21 (tied off)
- dft_strap1_idx: 22 // MIO 22 (tied off)
- };
-
- top_earlgrey #(
- .AesMasking(1'b0),
- .AesSBoxImpl(aes_pkg::SBoxImplLut),
- .SecAesStartTriggerDelay(0),
- .SecAesAllowForcingMasks(1'b0),
- .SecAesSkipPRNGReseeding(1'b0),
- .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
- .IbexRegFile(ibex_pkg::RegFileFPGA),
- .IbexPipeLine(1),
- .OtbnRegFile(otbn_pkg::RegFileFPGA),
- .RomCtrlBootRomInitFile(BootRomInitFile),
- .OtpCtrlMemInitFile(OtpCtrlMemInitFile),
- .SramCtrlRetAonInstrExec(0),
- .SramCtrlMainInstrExec(1),
- .PinmuxAonTargetCfg(PinmuxTargetCfg)
- ) top_earlgrey (
- // Clocks, resets
- .rst_ni ( rst_n ),
- .clk_main_i ( clk_main ),
- .clk_io_i ( clk_main ),
- .clk_usb_i ( clk_usb_48mhz ),
- .clk_aon_i ( clk_aon ),
- .clks_ast_o ( ),
- .rsts_ast_o ( ),
- .pwrmgr_ast_req_o ( ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
- .usbdev_usb_ref_val_o ( ),
- .usbdev_usb_ref_pulse_o ( ),
- .ast_tl_req_o ( ),
- .ast_tl_rsp_i ( '0 ),
- .ast_edn_req_i ( '0 ),
- .ast_edn_rsp_o ( ),
- .otp_ctrl_otp_ast_pwr_seq_o ( ),
- .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
- .flash_bist_enable_i ( 1'b0 ),
- .flash_power_down_h_i ( 1'b0 ),
- .flash_power_ready_h_i ( 1'b1 ),
- // Need to modle this logic at some point, otherwise entropy
- // on verilator will hang
- .es_rng_req_o ( ),
- .es_rng_rsp_i ( '0 ),
- .ast_clk_byp_req_o ( lc_clk_bypass ),
- .ast_clk_byp_ack_i ( lc_clk_bypass ),
-
- // Multiplexed I/O
- .mio_in_i ( mio_in_core ),
- .mio_out_o ( mio_out_core ),
- .mio_oe_o ( mio_oe_core ),
-
- // Dedicated I/O
- .dio_in_i ( dio_in_core ),
- .dio_out_o ( dio_out_core ),
- .dio_oe_o ( dio_oe_core ),
-
- // Pad attributes
- .mio_attr_o ( mio_attr ),
- .dio_attr_o ( dio_attr ),
-
- // Memory attributes
- .ram_1p_cfg_i ( '0 ),
- .ram_2p_cfg_i ( '0 ),
- .rom_cfg_i ( '0 ),
-
- // DFT signals
- .scan_rst_ni ( 1'b1 ),
- .scan_en_i ( 1'b0 ),
- .scanmode_i ( lc_ctrl_pkg::Off )
- );
-
-endmodule : top_earlgrey_nexysvideo
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
index fe25d24..3143dc0 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
@@ -8,6 +8,8 @@
input rst_ni
);
+ import top_earlgrey_pkg::*;
+
logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
@@ -32,47 +34,36 @@
logic [20:0] dio_out;
logic [20:0] dio_oe;
- assign dio_in = {cio_spi_device_sck_p2d,
- cio_spi_device_csb_p2d,
- 1'b0,
- 1'b0,
- 1'b0,
- cio_spi_device_sdi_p2d,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- cio_usbdev_sense_p2d,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- cio_usbdev_d_p2d,
- cio_usbdev_dp_p2d,
- cio_usbdev_dn_p2d};
+ always_comb begin : assign_dio_in
+ dio_in = '0;
+ dio_in[DioSpiDeviceSck] = cio_spi_device_sck_p2d;
+ dio_in[DioSpiDeviceCsb] = cio_spi_device_csb_p2d;
+ dio_in[DioSpiDeviceSd0] = cio_spi_device_sdi_p2d;
+ dio_in[DioUsbdevSense] = cio_usbdev_sense_p2d;
+ dio_in[DioUsbdevD] = cio_usbdev_d_p2d;
+ dio_in[DioUsbdevDp] = cio_usbdev_dp_p2d;
+ dio_in[DioUsbdevDn] = cio_usbdev_dn_p2d;
+ end
- assign cio_usbdev_dn_d2p = dio_out[0];
- assign cio_usbdev_dp_d2p = dio_out[1];
- assign cio_usbdev_d_d2p = dio_out[2];
- assign cio_usbdev_suspend_d2p = dio_out[3];
- assign cio_usbdev_tx_mode_se_d2p = dio_out[4];
- assign cio_usbdev_dn_pullup_d2p = dio_out[5];
- assign cio_usbdev_dp_pullup_d2p = dio_out[6];
- assign cio_usbdev_se0_d2p = dio_out[7];
- assign cio_spi_device_sdo_d2p = dio_out[16];
+ assign cio_usbdev_dn_d2p = dio_out[DioUsbdevDn];
+ assign cio_usbdev_dp_d2p = dio_out[DioUsbdevDp];
+ assign cio_usbdev_d_d2p = dio_out[DioUsbdevD];
+ assign cio_usbdev_suspend_d2p = dio_out[DioUsbdevSuspend];
+ assign cio_usbdev_tx_mode_se_d2p = dio_out[DioUsbdevTxModeSe];
+ assign cio_usbdev_dn_pullup_d2p = dio_out[DioUsbdevDnPullup];
+ assign cio_usbdev_dp_pullup_d2p = dio_out[DioUsbdevDpPullup];
+ assign cio_usbdev_se0_d2p = dio_out[DioUsbdevSe0];
+ assign cio_spi_device_sdo_d2p = dio_out[DioSpiDeviceSd1];
- assign cio_usbdev_dn_en_d2p = dio_oe[0];
- assign cio_usbdev_dp_en_d2p = dio_oe[1];
- assign cio_usbdev_d_en_d2p = dio_oe[2];
- assign cio_usbdev_suspend_en_d2p = dio_oe[3];
- assign cio_usbdev_tx_mode_se_en_d2p = dio_oe[4];
- assign cio_usbdev_dn_pullup_en_d2p = dio_oe[5];
- assign cio_usbdev_dp_pullup_en_d2p = dio_oe[6];
- assign cio_usbdev_se0_en_d2p = dio_oe[7];
- assign cio_spi_device_sdo_en_d2p = dio_oe[16];
+ assign cio_usbdev_dn_en_d2p = dio_oe[DioUsbdevDn];
+ assign cio_usbdev_dp_en_d2p = dio_oe[DioUsbdevDp];
+ assign cio_usbdev_d_en_d2p = dio_oe[DioUsbdevD];
+ assign cio_usbdev_suspend_en_d2p = dio_oe[DioUsbdevSuspend];
+ assign cio_usbdev_tx_mode_se_en_d2p = dio_oe[DioUsbdevTxModeSe];
+ assign cio_usbdev_dn_pullup_en_d2p = dio_oe[DioUsbdevDnPullup];
+ assign cio_usbdev_dp_pullup_en_d2p = dio_oe[DioUsbdevDpPullup];
+ assign cio_usbdev_se0_en_d2p = dio_oe[DioUsbdevSe0];
+ assign cio_spi_device_sdo_en_d2p = dio_oe[DioSpiDeviceSd1];
logic [43:0] mio_in;
logic [43:0] mio_out;
@@ -127,25 +118,31 @@
.clk_o(clk_aon)
);
- // DFT and Debug signal positions in the pinout.
// TODO: generate these indices from the target-specific
- // pinout configuration.
+ // pinout configuration. But first, this verilator top needs
+ // to be split into a Verilator TB and a Verilator chiplevel.
+ // DFT and Debug signal positions in the pinout.
localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
const_sampling: 1'b1,
tie_offs: '0,
tck_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSck,
+ top_earlgrey_pkg::DioSpiDeviceSck,
tms_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceCsb,
+ top_earlgrey_pkg::DioSpiDeviceCsb,
trst_idx: 18, // MIO 18
tdi_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSd0,
+ top_earlgrey_pkg::DioSpiDeviceSd0,
tdo_idx: pinmux_reg_pkg::NMioPads +
- top_earlgrey_pkg::TopEarlgreyDioPinSpiDeviceSd1,
+ top_earlgrey_pkg::DioSpiDeviceSd1,
tap_strap0_idx: 26, // MIO 26
tap_strap1_idx: 16, // MIO 16 (this is different in the ASIC top)
dft_strap0_idx: 21, // MIO 21
- dft_strap1_idx: 22 // MIO 22
+ dft_strap1_idx: 22, // MIO 22
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevDp,
+ usb_dn_idx: DioUsbdevDn,
+ usb_dp_pullup_idx: DioUsbdevDpPullup,
+ usb_dn_pullup_idx: DioUsbdevDnPullup
};
lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 2a3ce32..0289e3e 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1117,10 +1117,10 @@
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
-// PERIPH_INSEL ranges from 0 to NUM_MIO + 2 -1}
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
// 0 and 1 are tied to value 0 and 1
-#define NUM_MIO 44
-#define NUM_DIO 21
+#define NUM_MIO_PADS 44
+#define NUM_DIO_PADS 21
#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
@@ -1128,65 +1128,65 @@
* Pinmux Peripheral Input.
*/
typedef enum top_earlgrey_pinmux_peripheral_in {
- kTopEarlgreyPinmuxPeripheralInGpioGpio0 = 0, /**< gpio_gpio 0 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio1 = 1, /**< gpio_gpio 1 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio2 = 2, /**< gpio_gpio 2 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio3 = 3, /**< gpio_gpio 3 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio4 = 4, /**< gpio_gpio 4 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio5 = 5, /**< gpio_gpio 5 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio6 = 6, /**< gpio_gpio 6 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio7 = 7, /**< gpio_gpio 7 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio8 = 8, /**< gpio_gpio 8 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio9 = 9, /**< gpio_gpio 9 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio10 = 10, /**< gpio_gpio 10 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio11 = 11, /**< gpio_gpio 11 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio12 = 12, /**< gpio_gpio 12 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio13 = 13, /**< gpio_gpio 13 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio14 = 14, /**< gpio_gpio 14 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio15 = 15, /**< gpio_gpio 15 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio16 = 16, /**< gpio_gpio 16 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio17 = 17, /**< gpio_gpio 17 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio18 = 18, /**< gpio_gpio 18 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio19 = 19, /**< gpio_gpio 19 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio20 = 20, /**< gpio_gpio 20 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio21 = 21, /**< gpio_gpio 21 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio22 = 22, /**< gpio_gpio 22 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio23 = 23, /**< gpio_gpio 23 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio24 = 24, /**< gpio_gpio 24 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio25 = 25, /**< gpio_gpio 25 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio26 = 26, /**< gpio_gpio 26 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio27 = 27, /**< gpio_gpio 27 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio28 = 28, /**< gpio_gpio 28 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio29 = 29, /**< gpio_gpio 29 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio30 = 30, /**< gpio_gpio 30 */
- kTopEarlgreyPinmuxPeripheralInGpioGpio31 = 31, /**< gpio_gpio 31 */
- kTopEarlgreyPinmuxPeripheralInUart0Rx = 32, /**< uart0_rx */
- kTopEarlgreyPinmuxPeripheralInUart1Rx = 33, /**< uart1_rx */
- kTopEarlgreyPinmuxPeripheralInUart2Rx = 34, /**< uart2_rx */
- kTopEarlgreyPinmuxPeripheralInUart3Rx = 35, /**< uart3_rx */
- kTopEarlgreyPinmuxPeripheralInI2c0Sda = 36, /**< i2c0_sda */
- kTopEarlgreyPinmuxPeripheralInI2c0Scl = 37, /**< i2c0_scl */
- kTopEarlgreyPinmuxPeripheralInI2c1Sda = 38, /**< i2c1_sda */
- kTopEarlgreyPinmuxPeripheralInI2c1Scl = 39, /**< i2c1_scl */
- kTopEarlgreyPinmuxPeripheralInI2c2Sda = 40, /**< i2c2_sda */
- kTopEarlgreyPinmuxPeripheralInI2c2Scl = 41, /**< i2c2_scl */
- kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 42, /**< spi_host1_sd 0 */
- kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 43, /**< spi_host1_sd 1 */
- kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 44, /**< spi_host1_sd 2 */
- kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 45, /**< spi_host1_sd 3 */
- kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 46, /**< flash_ctrl_tck */
- kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 47, /**< flash_ctrl_tms */
- kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 48, /**< flash_ctrl_tdi */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn0 = 49, /**< sensor_ctrl_aon_ast_debug_in 0 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn1 = 50, /**< sensor_ctrl_aon_ast_debug_in 1 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn2 = 51, /**< sensor_ctrl_aon_ast_debug_in 2 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn3 = 52, /**< sensor_ctrl_aon_ast_debug_in 3 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn4 = 53, /**< sensor_ctrl_aon_ast_debug_in 4 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn5 = 54, /**< sensor_ctrl_aon_ast_debug_in 5 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn6 = 55, /**< sensor_ctrl_aon_ast_debug_in 6 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn7 = 56, /**< sensor_ctrl_aon_ast_debug_in 7 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn8 = 57, /**< sensor_ctrl_aon_ast_debug_in 8 */
- kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn9 = 58, /**< sensor_ctrl_aon_ast_debug_in 9 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio0 = 0, /**< Peripheral Input 0 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio1 = 1, /**< Peripheral Input 1 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio2 = 2, /**< Peripheral Input 2 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio3 = 3, /**< Peripheral Input 3 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio4 = 4, /**< Peripheral Input 4 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio5 = 5, /**< Peripheral Input 5 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio6 = 6, /**< Peripheral Input 6 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio7 = 7, /**< Peripheral Input 7 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio8 = 8, /**< Peripheral Input 8 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio9 = 9, /**< Peripheral Input 9 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio10 = 10, /**< Peripheral Input 10 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio11 = 11, /**< Peripheral Input 11 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio12 = 12, /**< Peripheral Input 12 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio13 = 13, /**< Peripheral Input 13 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio14 = 14, /**< Peripheral Input 14 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio15 = 15, /**< Peripheral Input 15 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio16 = 16, /**< Peripheral Input 16 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio17 = 17, /**< Peripheral Input 17 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio18 = 18, /**< Peripheral Input 18 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio19 = 19, /**< Peripheral Input 19 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio20 = 20, /**< Peripheral Input 20 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio21 = 21, /**< Peripheral Input 21 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio22 = 22, /**< Peripheral Input 22 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio23 = 23, /**< Peripheral Input 23 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio24 = 24, /**< Peripheral Input 24 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio25 = 25, /**< Peripheral Input 25 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio26 = 26, /**< Peripheral Input 26 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio27 = 27, /**< Peripheral Input 27 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio28 = 28, /**< Peripheral Input 28 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio29 = 29, /**< Peripheral Input 29 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio30 = 30, /**< Peripheral Input 30 */
+ kTopEarlgreyPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */
+ kTopEarlgreyPinmuxPeripheralInI2c0Sda = 32, /**< Peripheral Input 32 */
+ kTopEarlgreyPinmuxPeripheralInI2c0Scl = 33, /**< Peripheral Input 33 */
+ kTopEarlgreyPinmuxPeripheralInI2c1Sda = 34, /**< Peripheral Input 34 */
+ kTopEarlgreyPinmuxPeripheralInI2c1Scl = 35, /**< Peripheral Input 35 */
+ kTopEarlgreyPinmuxPeripheralInI2c2Sda = 36, /**< Peripheral Input 36 */
+ kTopEarlgreyPinmuxPeripheralInI2c2Scl = 37, /**< Peripheral Input 37 */
+ kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 38, /**< Peripheral Input 38 */
+ kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 39, /**< Peripheral Input 39 */
+ kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 40, /**< Peripheral Input 40 */
+ kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 41, /**< Peripheral Input 41 */
+ kTopEarlgreyPinmuxPeripheralInUart0Rx = 42, /**< Peripheral Input 42 */
+ kTopEarlgreyPinmuxPeripheralInUart1Rx = 43, /**< Peripheral Input 43 */
+ kTopEarlgreyPinmuxPeripheralInUart2Rx = 44, /**< Peripheral Input 44 */
+ kTopEarlgreyPinmuxPeripheralInUart3Rx = 45, /**< Peripheral Input 45 */
+ kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 46, /**< Peripheral Input 46 */
+ kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 47, /**< Peripheral Input 47 */
+ kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 48, /**< Peripheral Input 48 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn0 = 49, /**< Peripheral Input 49 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn1 = 50, /**< Peripheral Input 50 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn2 = 51, /**< Peripheral Input 51 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn3 = 52, /**< Peripheral Input 52 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn4 = 53, /**< Peripheral Input 53 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn5 = 54, /**< Peripheral Input 54 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn6 = 55, /**< Peripheral Input 55 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn7 = 56, /**< Peripheral Input 56 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn8 = 57, /**< Peripheral Input 57 */
+ kTopEarlgreyPinmuxPeripheralInSensorCtrlAonAstDebugIn9 = 58, /**< Peripheral Input 58 */
kTopEarlgreyPinmuxPeripheralInLast = 58, /**< \internal Last valid peripheral input */
} top_earlgrey_pinmux_peripheral_in_t;
@@ -1196,50 +1196,50 @@
typedef enum top_earlgrey_pinmux_insel {
kTopEarlgreyPinmuxInselConstantZero = 0, /**< Tie constantly to zero */
kTopEarlgreyPinmuxInselConstantOne = 1, /**< Tie constantly to one */
- kTopEarlgreyPinmuxInselMio0 = 2, /**< MIO Pad 0 */
- kTopEarlgreyPinmuxInselMio1 = 3, /**< MIO Pad 1 */
- kTopEarlgreyPinmuxInselMio2 = 4, /**< MIO Pad 2 */
- kTopEarlgreyPinmuxInselMio3 = 5, /**< MIO Pad 3 */
- kTopEarlgreyPinmuxInselMio4 = 6, /**< MIO Pad 4 */
- kTopEarlgreyPinmuxInselMio5 = 7, /**< MIO Pad 5 */
- kTopEarlgreyPinmuxInselMio6 = 8, /**< MIO Pad 6 */
- kTopEarlgreyPinmuxInselMio7 = 9, /**< MIO Pad 7 */
- kTopEarlgreyPinmuxInselMio8 = 10, /**< MIO Pad 8 */
- kTopEarlgreyPinmuxInselMio9 = 11, /**< MIO Pad 9 */
- kTopEarlgreyPinmuxInselMio10 = 12, /**< MIO Pad 10 */
- kTopEarlgreyPinmuxInselMio11 = 13, /**< MIO Pad 11 */
- kTopEarlgreyPinmuxInselMio12 = 14, /**< MIO Pad 12 */
- kTopEarlgreyPinmuxInselMio13 = 15, /**< MIO Pad 13 */
- kTopEarlgreyPinmuxInselMio14 = 16, /**< MIO Pad 14 */
- kTopEarlgreyPinmuxInselMio15 = 17, /**< MIO Pad 15 */
- kTopEarlgreyPinmuxInselMio16 = 18, /**< MIO Pad 16 */
- kTopEarlgreyPinmuxInselMio17 = 19, /**< MIO Pad 17 */
- kTopEarlgreyPinmuxInselMio18 = 20, /**< MIO Pad 18 */
- kTopEarlgreyPinmuxInselMio19 = 21, /**< MIO Pad 19 */
- kTopEarlgreyPinmuxInselMio20 = 22, /**< MIO Pad 20 */
- kTopEarlgreyPinmuxInselMio21 = 23, /**< MIO Pad 21 */
- kTopEarlgreyPinmuxInselMio22 = 24, /**< MIO Pad 22 */
- kTopEarlgreyPinmuxInselMio23 = 25, /**< MIO Pad 23 */
- kTopEarlgreyPinmuxInselMio24 = 26, /**< MIO Pad 24 */
- kTopEarlgreyPinmuxInselMio25 = 27, /**< MIO Pad 25 */
- kTopEarlgreyPinmuxInselMio26 = 28, /**< MIO Pad 26 */
- kTopEarlgreyPinmuxInselMio27 = 29, /**< MIO Pad 27 */
- kTopEarlgreyPinmuxInselMio28 = 30, /**< MIO Pad 28 */
- kTopEarlgreyPinmuxInselMio29 = 31, /**< MIO Pad 29 */
- kTopEarlgreyPinmuxInselMio30 = 32, /**< MIO Pad 30 */
- kTopEarlgreyPinmuxInselMio31 = 33, /**< MIO Pad 31 */
- kTopEarlgreyPinmuxInselMio32 = 34, /**< MIO Pad 32 */
- kTopEarlgreyPinmuxInselMio33 = 35, /**< MIO Pad 33 */
- kTopEarlgreyPinmuxInselMio34 = 36, /**< MIO Pad 34 */
- kTopEarlgreyPinmuxInselMio35 = 37, /**< MIO Pad 35 */
- kTopEarlgreyPinmuxInselMio36 = 38, /**< MIO Pad 36 */
- kTopEarlgreyPinmuxInselMio37 = 39, /**< MIO Pad 37 */
- kTopEarlgreyPinmuxInselMio38 = 40, /**< MIO Pad 38 */
- kTopEarlgreyPinmuxInselMio39 = 41, /**< MIO Pad 39 */
- kTopEarlgreyPinmuxInselMio40 = 42, /**< MIO Pad 40 */
- kTopEarlgreyPinmuxInselMio41 = 43, /**< MIO Pad 41 */
- kTopEarlgreyPinmuxInselMio42 = 44, /**< MIO Pad 42 */
- kTopEarlgreyPinmuxInselMio43 = 45, /**< MIO Pad 43 */
+ kTopEarlgreyPinmuxInselIoa0 = 2, /**< MIO Pad 0 */
+ kTopEarlgreyPinmuxInselIoa1 = 3, /**< MIO Pad 1 */
+ kTopEarlgreyPinmuxInselIoa2 = 4, /**< MIO Pad 2 */
+ kTopEarlgreyPinmuxInselIoa3 = 5, /**< MIO Pad 3 */
+ kTopEarlgreyPinmuxInselIoa4 = 6, /**< MIO Pad 4 */
+ kTopEarlgreyPinmuxInselIoa5 = 7, /**< MIO Pad 5 */
+ kTopEarlgreyPinmuxInselIob0 = 8, /**< MIO Pad 6 */
+ kTopEarlgreyPinmuxInselIob1 = 9, /**< MIO Pad 7 */
+ kTopEarlgreyPinmuxInselIob2 = 10, /**< MIO Pad 8 */
+ kTopEarlgreyPinmuxInselIob3 = 11, /**< MIO Pad 9 */
+ kTopEarlgreyPinmuxInselIob4 = 12, /**< MIO Pad 10 */
+ kTopEarlgreyPinmuxInselIob5 = 13, /**< MIO Pad 11 */
+ kTopEarlgreyPinmuxInselIob6 = 14, /**< MIO Pad 12 */
+ kTopEarlgreyPinmuxInselIob7 = 15, /**< MIO Pad 13 */
+ kTopEarlgreyPinmuxInselIob8 = 16, /**< MIO Pad 14 */
+ kTopEarlgreyPinmuxInselIob9 = 17, /**< MIO Pad 15 */
+ kTopEarlgreyPinmuxInselIob10 = 18, /**< MIO Pad 16 */
+ kTopEarlgreyPinmuxInselIob11 = 19, /**< MIO Pad 17 */
+ kTopEarlgreyPinmuxInselIoc0 = 20, /**< MIO Pad 18 */
+ kTopEarlgreyPinmuxInselIoc1 = 21, /**< MIO Pad 19 */
+ kTopEarlgreyPinmuxInselIoc2 = 22, /**< MIO Pad 20 */
+ kTopEarlgreyPinmuxInselIoc3 = 23, /**< MIO Pad 21 */
+ kTopEarlgreyPinmuxInselIoc4 = 24, /**< MIO Pad 22 */
+ kTopEarlgreyPinmuxInselIoc5 = 25, /**< MIO Pad 23 */
+ kTopEarlgreyPinmuxInselIoc6 = 26, /**< MIO Pad 24 */
+ kTopEarlgreyPinmuxInselIoc7 = 27, /**< MIO Pad 25 */
+ kTopEarlgreyPinmuxInselIoc8 = 28, /**< MIO Pad 26 */
+ kTopEarlgreyPinmuxInselIoc9 = 29, /**< MIO Pad 27 */
+ kTopEarlgreyPinmuxInselIoc10 = 30, /**< MIO Pad 28 */
+ kTopEarlgreyPinmuxInselIoc11 = 31, /**< MIO Pad 29 */
+ kTopEarlgreyPinmuxInselIor0 = 32, /**< MIO Pad 30 */
+ kTopEarlgreyPinmuxInselIor1 = 33, /**< MIO Pad 31 */
+ kTopEarlgreyPinmuxInselIor2 = 34, /**< MIO Pad 32 */
+ kTopEarlgreyPinmuxInselIor3 = 35, /**< MIO Pad 33 */
+ kTopEarlgreyPinmuxInselIor4 = 36, /**< MIO Pad 34 */
+ kTopEarlgreyPinmuxInselIor5 = 37, /**< MIO Pad 35 */
+ kTopEarlgreyPinmuxInselIor6 = 38, /**< MIO Pad 36 */
+ kTopEarlgreyPinmuxInselIor7 = 39, /**< MIO Pad 37 */
+ kTopEarlgreyPinmuxInselIor8 = 40, /**< MIO Pad 38 */
+ kTopEarlgreyPinmuxInselIor9 = 41, /**< MIO Pad 39 */
+ kTopEarlgreyPinmuxInselIor10 = 42, /**< MIO Pad 40 */
+ kTopEarlgreyPinmuxInselIor11 = 43, /**< MIO Pad 41 */
+ kTopEarlgreyPinmuxInselIor12 = 44, /**< MIO Pad 42 */
+ kTopEarlgreyPinmuxInselIor13 = 45, /**< MIO Pad 43 */
kTopEarlgreyPinmuxInselLast = 45, /**< \internal Last valid insel value */
} top_earlgrey_pinmux_insel_t;
@@ -1247,50 +1247,50 @@
* Pinmux MIO Output.
*/
typedef enum top_earlgrey_pinmux_mio_out {
- kTopEarlgreyPinmuxMioOut0 = 0, /**< MIO Pad 0 */
- kTopEarlgreyPinmuxMioOut1 = 1, /**< MIO Pad 1 */
- kTopEarlgreyPinmuxMioOut2 = 2, /**< MIO Pad 2 */
- kTopEarlgreyPinmuxMioOut3 = 3, /**< MIO Pad 3 */
- kTopEarlgreyPinmuxMioOut4 = 4, /**< MIO Pad 4 */
- kTopEarlgreyPinmuxMioOut5 = 5, /**< MIO Pad 5 */
- kTopEarlgreyPinmuxMioOut6 = 6, /**< MIO Pad 6 */
- kTopEarlgreyPinmuxMioOut7 = 7, /**< MIO Pad 7 */
- kTopEarlgreyPinmuxMioOut8 = 8, /**< MIO Pad 8 */
- kTopEarlgreyPinmuxMioOut9 = 9, /**< MIO Pad 9 */
- kTopEarlgreyPinmuxMioOut10 = 10, /**< MIO Pad 10 */
- kTopEarlgreyPinmuxMioOut11 = 11, /**< MIO Pad 11 */
- kTopEarlgreyPinmuxMioOut12 = 12, /**< MIO Pad 12 */
- kTopEarlgreyPinmuxMioOut13 = 13, /**< MIO Pad 13 */
- kTopEarlgreyPinmuxMioOut14 = 14, /**< MIO Pad 14 */
- kTopEarlgreyPinmuxMioOut15 = 15, /**< MIO Pad 15 */
- kTopEarlgreyPinmuxMioOut16 = 16, /**< MIO Pad 16 */
- kTopEarlgreyPinmuxMioOut17 = 17, /**< MIO Pad 17 */
- kTopEarlgreyPinmuxMioOut18 = 18, /**< MIO Pad 18 */
- kTopEarlgreyPinmuxMioOut19 = 19, /**< MIO Pad 19 */
- kTopEarlgreyPinmuxMioOut20 = 20, /**< MIO Pad 20 */
- kTopEarlgreyPinmuxMioOut21 = 21, /**< MIO Pad 21 */
- kTopEarlgreyPinmuxMioOut22 = 22, /**< MIO Pad 22 */
- kTopEarlgreyPinmuxMioOut23 = 23, /**< MIO Pad 23 */
- kTopEarlgreyPinmuxMioOut24 = 24, /**< MIO Pad 24 */
- kTopEarlgreyPinmuxMioOut25 = 25, /**< MIO Pad 25 */
- kTopEarlgreyPinmuxMioOut26 = 26, /**< MIO Pad 26 */
- kTopEarlgreyPinmuxMioOut27 = 27, /**< MIO Pad 27 */
- kTopEarlgreyPinmuxMioOut28 = 28, /**< MIO Pad 28 */
- kTopEarlgreyPinmuxMioOut29 = 29, /**< MIO Pad 29 */
- kTopEarlgreyPinmuxMioOut30 = 30, /**< MIO Pad 30 */
- kTopEarlgreyPinmuxMioOut31 = 31, /**< MIO Pad 31 */
- kTopEarlgreyPinmuxMioOut32 = 32, /**< MIO Pad 32 */
- kTopEarlgreyPinmuxMioOut33 = 33, /**< MIO Pad 33 */
- kTopEarlgreyPinmuxMioOut34 = 34, /**< MIO Pad 34 */
- kTopEarlgreyPinmuxMioOut35 = 35, /**< MIO Pad 35 */
- kTopEarlgreyPinmuxMioOut36 = 36, /**< MIO Pad 36 */
- kTopEarlgreyPinmuxMioOut37 = 37, /**< MIO Pad 37 */
- kTopEarlgreyPinmuxMioOut38 = 38, /**< MIO Pad 38 */
- kTopEarlgreyPinmuxMioOut39 = 39, /**< MIO Pad 39 */
- kTopEarlgreyPinmuxMioOut40 = 40, /**< MIO Pad 40 */
- kTopEarlgreyPinmuxMioOut41 = 41, /**< MIO Pad 41 */
- kTopEarlgreyPinmuxMioOut42 = 42, /**< MIO Pad 42 */
- kTopEarlgreyPinmuxMioOut43 = 43, /**< MIO Pad 43 */
+ kTopEarlgreyPinmuxMioOutIoa0 = 0, /**< MIO Pad 0 */
+ kTopEarlgreyPinmuxMioOutIoa1 = 1, /**< MIO Pad 1 */
+ kTopEarlgreyPinmuxMioOutIoa2 = 2, /**< MIO Pad 2 */
+ kTopEarlgreyPinmuxMioOutIoa3 = 3, /**< MIO Pad 3 */
+ kTopEarlgreyPinmuxMioOutIoa4 = 4, /**< MIO Pad 4 */
+ kTopEarlgreyPinmuxMioOutIoa5 = 5, /**< MIO Pad 5 */
+ kTopEarlgreyPinmuxMioOutIob0 = 6, /**< MIO Pad 6 */
+ kTopEarlgreyPinmuxMioOutIob1 = 7, /**< MIO Pad 7 */
+ kTopEarlgreyPinmuxMioOutIob2 = 8, /**< MIO Pad 8 */
+ kTopEarlgreyPinmuxMioOutIob3 = 9, /**< MIO Pad 9 */
+ kTopEarlgreyPinmuxMioOutIob4 = 10, /**< MIO Pad 10 */
+ kTopEarlgreyPinmuxMioOutIob5 = 11, /**< MIO Pad 11 */
+ kTopEarlgreyPinmuxMioOutIob6 = 12, /**< MIO Pad 12 */
+ kTopEarlgreyPinmuxMioOutIob7 = 13, /**< MIO Pad 13 */
+ kTopEarlgreyPinmuxMioOutIob8 = 14, /**< MIO Pad 14 */
+ kTopEarlgreyPinmuxMioOutIob9 = 15, /**< MIO Pad 15 */
+ kTopEarlgreyPinmuxMioOutIob10 = 16, /**< MIO Pad 16 */
+ kTopEarlgreyPinmuxMioOutIob11 = 17, /**< MIO Pad 17 */
+ kTopEarlgreyPinmuxMioOutIoc0 = 18, /**< MIO Pad 18 */
+ kTopEarlgreyPinmuxMioOutIoc1 = 19, /**< MIO Pad 19 */
+ kTopEarlgreyPinmuxMioOutIoc2 = 20, /**< MIO Pad 20 */
+ kTopEarlgreyPinmuxMioOutIoc3 = 21, /**< MIO Pad 21 */
+ kTopEarlgreyPinmuxMioOutIoc4 = 22, /**< MIO Pad 22 */
+ kTopEarlgreyPinmuxMioOutIoc5 = 23, /**< MIO Pad 23 */
+ kTopEarlgreyPinmuxMioOutIoc6 = 24, /**< MIO Pad 24 */
+ kTopEarlgreyPinmuxMioOutIoc7 = 25, /**< MIO Pad 25 */
+ kTopEarlgreyPinmuxMioOutIoc8 = 26, /**< MIO Pad 26 */
+ kTopEarlgreyPinmuxMioOutIoc9 = 27, /**< MIO Pad 27 */
+ kTopEarlgreyPinmuxMioOutIoc10 = 28, /**< MIO Pad 28 */
+ kTopEarlgreyPinmuxMioOutIoc11 = 29, /**< MIO Pad 29 */
+ kTopEarlgreyPinmuxMioOutIor0 = 30, /**< MIO Pad 30 */
+ kTopEarlgreyPinmuxMioOutIor1 = 31, /**< MIO Pad 31 */
+ kTopEarlgreyPinmuxMioOutIor2 = 32, /**< MIO Pad 32 */
+ kTopEarlgreyPinmuxMioOutIor3 = 33, /**< MIO Pad 33 */
+ kTopEarlgreyPinmuxMioOutIor4 = 34, /**< MIO Pad 34 */
+ kTopEarlgreyPinmuxMioOutIor5 = 35, /**< MIO Pad 35 */
+ kTopEarlgreyPinmuxMioOutIor6 = 36, /**< MIO Pad 36 */
+ kTopEarlgreyPinmuxMioOutIor7 = 37, /**< MIO Pad 37 */
+ kTopEarlgreyPinmuxMioOutIor8 = 38, /**< MIO Pad 38 */
+ kTopEarlgreyPinmuxMioOutIor9 = 39, /**< MIO Pad 39 */
+ kTopEarlgreyPinmuxMioOutIor10 = 40, /**< MIO Pad 40 */
+ kTopEarlgreyPinmuxMioOutIor11 = 41, /**< MIO Pad 41 */
+ kTopEarlgreyPinmuxMioOutIor12 = 42, /**< MIO Pad 42 */
+ kTopEarlgreyPinmuxMioOutIor13 = 43, /**< MIO Pad 43 */
kTopEarlgreyPinmuxMioOutLast = 43, /**< \internal Last valid mio output */
} top_earlgrey_pinmux_mio_out_t;
@@ -1301,69 +1301,69 @@
kTopEarlgreyPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */
kTopEarlgreyPinmuxOutselConstantOne = 1, /**< Tie constantly to one */
kTopEarlgreyPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */
- kTopEarlgreyPinmuxOutselGpioGpio0 = 3, /**< gpio_gpio 0 */
- kTopEarlgreyPinmuxOutselGpioGpio1 = 4, /**< gpio_gpio 1 */
- kTopEarlgreyPinmuxOutselGpioGpio2 = 5, /**< gpio_gpio 2 */
- kTopEarlgreyPinmuxOutselGpioGpio3 = 6, /**< gpio_gpio 3 */
- kTopEarlgreyPinmuxOutselGpioGpio4 = 7, /**< gpio_gpio 4 */
- kTopEarlgreyPinmuxOutselGpioGpio5 = 8, /**< gpio_gpio 5 */
- kTopEarlgreyPinmuxOutselGpioGpio6 = 9, /**< gpio_gpio 6 */
- kTopEarlgreyPinmuxOutselGpioGpio7 = 10, /**< gpio_gpio 7 */
- kTopEarlgreyPinmuxOutselGpioGpio8 = 11, /**< gpio_gpio 8 */
- kTopEarlgreyPinmuxOutselGpioGpio9 = 12, /**< gpio_gpio 9 */
- kTopEarlgreyPinmuxOutselGpioGpio10 = 13, /**< gpio_gpio 10 */
- kTopEarlgreyPinmuxOutselGpioGpio11 = 14, /**< gpio_gpio 11 */
- kTopEarlgreyPinmuxOutselGpioGpio12 = 15, /**< gpio_gpio 12 */
- kTopEarlgreyPinmuxOutselGpioGpio13 = 16, /**< gpio_gpio 13 */
- kTopEarlgreyPinmuxOutselGpioGpio14 = 17, /**< gpio_gpio 14 */
- kTopEarlgreyPinmuxOutselGpioGpio15 = 18, /**< gpio_gpio 15 */
- kTopEarlgreyPinmuxOutselGpioGpio16 = 19, /**< gpio_gpio 16 */
- kTopEarlgreyPinmuxOutselGpioGpio17 = 20, /**< gpio_gpio 17 */
- kTopEarlgreyPinmuxOutselGpioGpio18 = 21, /**< gpio_gpio 18 */
- kTopEarlgreyPinmuxOutselGpioGpio19 = 22, /**< gpio_gpio 19 */
- kTopEarlgreyPinmuxOutselGpioGpio20 = 23, /**< gpio_gpio 20 */
- kTopEarlgreyPinmuxOutselGpioGpio21 = 24, /**< gpio_gpio 21 */
- kTopEarlgreyPinmuxOutselGpioGpio22 = 25, /**< gpio_gpio 22 */
- kTopEarlgreyPinmuxOutselGpioGpio23 = 26, /**< gpio_gpio 23 */
- kTopEarlgreyPinmuxOutselGpioGpio24 = 27, /**< gpio_gpio 24 */
- kTopEarlgreyPinmuxOutselGpioGpio25 = 28, /**< gpio_gpio 25 */
- kTopEarlgreyPinmuxOutselGpioGpio26 = 29, /**< gpio_gpio 26 */
- kTopEarlgreyPinmuxOutselGpioGpio27 = 30, /**< gpio_gpio 27 */
- kTopEarlgreyPinmuxOutselGpioGpio28 = 31, /**< gpio_gpio 28 */
- kTopEarlgreyPinmuxOutselGpioGpio29 = 32, /**< gpio_gpio 29 */
- kTopEarlgreyPinmuxOutselGpioGpio30 = 33, /**< gpio_gpio 30 */
- kTopEarlgreyPinmuxOutselGpioGpio31 = 34, /**< gpio_gpio 31 */
- kTopEarlgreyPinmuxOutselUart0Tx = 35, /**< uart0_tx */
- kTopEarlgreyPinmuxOutselUart1Tx = 36, /**< uart1_tx */
- kTopEarlgreyPinmuxOutselUart2Tx = 37, /**< uart2_tx */
- kTopEarlgreyPinmuxOutselUart3Tx = 38, /**< uart3_tx */
- kTopEarlgreyPinmuxOutselI2c0Sda = 39, /**< i2c0_sda */
- kTopEarlgreyPinmuxOutselI2c0Scl = 40, /**< i2c0_scl */
- kTopEarlgreyPinmuxOutselI2c1Sda = 41, /**< i2c1_sda */
- kTopEarlgreyPinmuxOutselI2c1Scl = 42, /**< i2c1_scl */
- kTopEarlgreyPinmuxOutselI2c2Sda = 43, /**< i2c2_sda */
- kTopEarlgreyPinmuxOutselI2c2Scl = 44, /**< i2c2_scl */
- kTopEarlgreyPinmuxOutselPattgenPda0Tx = 45, /**< pattgen_pda0_tx */
- kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 46, /**< pattgen_pcl0_tx */
- kTopEarlgreyPinmuxOutselPattgenPda1Tx = 47, /**< pattgen_pda1_tx */
- kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 48, /**< pattgen_pcl1_tx */
- kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 49, /**< spi_host1_sd 0 */
- kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 50, /**< spi_host1_sd 1 */
- kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 51, /**< spi_host1_sd 2 */
- kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 52, /**< spi_host1_sd 3 */
- kTopEarlgreyPinmuxOutselSpiHost1Sck = 53, /**< spi_host1_sck */
- kTopEarlgreyPinmuxOutselSpiHost1Csb = 54, /**< spi_host1_csb */
- kTopEarlgreyPinmuxOutselFlashCtrlTdo = 55, /**< flash_ctrl_tdo */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 56, /**< sensor_ctrl_aon_ast_debug_out 0 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 57, /**< sensor_ctrl_aon_ast_debug_out 1 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 58, /**< sensor_ctrl_aon_ast_debug_out 2 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3 = 59, /**< sensor_ctrl_aon_ast_debug_out 3 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4 = 60, /**< sensor_ctrl_aon_ast_debug_out 4 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5 = 61, /**< sensor_ctrl_aon_ast_debug_out 5 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6 = 62, /**< sensor_ctrl_aon_ast_debug_out 6 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7 = 63, /**< sensor_ctrl_aon_ast_debug_out 7 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8 = 64, /**< sensor_ctrl_aon_ast_debug_out 8 */
- kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut9 = 65, /**< sensor_ctrl_aon_ast_debug_out 9 */
+ kTopEarlgreyPinmuxOutselGpioGpio0 = 3, /**< Peripheral Output 0 */
+ kTopEarlgreyPinmuxOutselGpioGpio1 = 4, /**< Peripheral Output 1 */
+ kTopEarlgreyPinmuxOutselGpioGpio2 = 5, /**< Peripheral Output 2 */
+ kTopEarlgreyPinmuxOutselGpioGpio3 = 6, /**< Peripheral Output 3 */
+ kTopEarlgreyPinmuxOutselGpioGpio4 = 7, /**< Peripheral Output 4 */
+ kTopEarlgreyPinmuxOutselGpioGpio5 = 8, /**< Peripheral Output 5 */
+ kTopEarlgreyPinmuxOutselGpioGpio6 = 9, /**< Peripheral Output 6 */
+ kTopEarlgreyPinmuxOutselGpioGpio7 = 10, /**< Peripheral Output 7 */
+ kTopEarlgreyPinmuxOutselGpioGpio8 = 11, /**< Peripheral Output 8 */
+ kTopEarlgreyPinmuxOutselGpioGpio9 = 12, /**< Peripheral Output 9 */
+ kTopEarlgreyPinmuxOutselGpioGpio10 = 13, /**< Peripheral Output 10 */
+ kTopEarlgreyPinmuxOutselGpioGpio11 = 14, /**< Peripheral Output 11 */
+ kTopEarlgreyPinmuxOutselGpioGpio12 = 15, /**< Peripheral Output 12 */
+ kTopEarlgreyPinmuxOutselGpioGpio13 = 16, /**< Peripheral Output 13 */
+ kTopEarlgreyPinmuxOutselGpioGpio14 = 17, /**< Peripheral Output 14 */
+ kTopEarlgreyPinmuxOutselGpioGpio15 = 18, /**< Peripheral Output 15 */
+ kTopEarlgreyPinmuxOutselGpioGpio16 = 19, /**< Peripheral Output 16 */
+ kTopEarlgreyPinmuxOutselGpioGpio17 = 20, /**< Peripheral Output 17 */
+ kTopEarlgreyPinmuxOutselGpioGpio18 = 21, /**< Peripheral Output 18 */
+ kTopEarlgreyPinmuxOutselGpioGpio19 = 22, /**< Peripheral Output 19 */
+ kTopEarlgreyPinmuxOutselGpioGpio20 = 23, /**< Peripheral Output 20 */
+ kTopEarlgreyPinmuxOutselGpioGpio21 = 24, /**< Peripheral Output 21 */
+ kTopEarlgreyPinmuxOutselGpioGpio22 = 25, /**< Peripheral Output 22 */
+ kTopEarlgreyPinmuxOutselGpioGpio23 = 26, /**< Peripheral Output 23 */
+ kTopEarlgreyPinmuxOutselGpioGpio24 = 27, /**< Peripheral Output 24 */
+ kTopEarlgreyPinmuxOutselGpioGpio25 = 28, /**< Peripheral Output 25 */
+ kTopEarlgreyPinmuxOutselGpioGpio26 = 29, /**< Peripheral Output 26 */
+ kTopEarlgreyPinmuxOutselGpioGpio27 = 30, /**< Peripheral Output 27 */
+ kTopEarlgreyPinmuxOutselGpioGpio28 = 31, /**< Peripheral Output 28 */
+ kTopEarlgreyPinmuxOutselGpioGpio29 = 32, /**< Peripheral Output 29 */
+ kTopEarlgreyPinmuxOutselGpioGpio30 = 33, /**< Peripheral Output 30 */
+ kTopEarlgreyPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */
+ kTopEarlgreyPinmuxOutselI2c0Sda = 35, /**< Peripheral Output 32 */
+ kTopEarlgreyPinmuxOutselI2c0Scl = 36, /**< Peripheral Output 33 */
+ kTopEarlgreyPinmuxOutselI2c1Sda = 37, /**< Peripheral Output 34 */
+ kTopEarlgreyPinmuxOutselI2c1Scl = 38, /**< Peripheral Output 35 */
+ kTopEarlgreyPinmuxOutselI2c2Sda = 39, /**< Peripheral Output 36 */
+ kTopEarlgreyPinmuxOutselI2c2Scl = 40, /**< Peripheral Output 37 */
+ kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 41, /**< Peripheral Output 38 */
+ kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 42, /**< Peripheral Output 39 */
+ kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 43, /**< Peripheral Output 40 */
+ kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 44, /**< Peripheral Output 41 */
+ kTopEarlgreyPinmuxOutselUart0Tx = 45, /**< Peripheral Output 42 */
+ kTopEarlgreyPinmuxOutselUart1Tx = 46, /**< Peripheral Output 43 */
+ kTopEarlgreyPinmuxOutselUart2Tx = 47, /**< Peripheral Output 44 */
+ kTopEarlgreyPinmuxOutselUart3Tx = 48, /**< Peripheral Output 45 */
+ kTopEarlgreyPinmuxOutselPattgenPda0Tx = 49, /**< Peripheral Output 46 */
+ kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 50, /**< Peripheral Output 47 */
+ kTopEarlgreyPinmuxOutselPattgenPda1Tx = 51, /**< Peripheral Output 48 */
+ kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 52, /**< Peripheral Output 49 */
+ kTopEarlgreyPinmuxOutselSpiHost1Sck = 53, /**< Peripheral Output 50 */
+ kTopEarlgreyPinmuxOutselSpiHost1Csb = 54, /**< Peripheral Output 51 */
+ kTopEarlgreyPinmuxOutselFlashCtrlTdo = 55, /**< Peripheral Output 52 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 56, /**< Peripheral Output 53 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 57, /**< Peripheral Output 54 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 58, /**< Peripheral Output 55 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut3 = 59, /**< Peripheral Output 56 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut4 = 60, /**< Peripheral Output 57 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut5 = 61, /**< Peripheral Output 58 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut6 = 62, /**< Peripheral Output 59 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut7 = 63, /**< Peripheral Output 60 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut8 = 64, /**< Peripheral Output 61 */
+ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut9 = 65, /**< Peripheral Output 62 */
kTopEarlgreyPinmuxOutselLast = 65, /**< \internal Last valid outsel value */
} top_earlgrey_pinmux_outsel_t;
diff --git a/hw/top_earlgrey/syn/asic.constraints.sdc b/hw/top_earlgrey/syn/asic.constraints.sdc
index 94794ce..f71d943 100644
--- a/hw/top_earlgrey/syn/asic.constraints.sdc
+++ b/hw/top_earlgrey/syn/asic.constraints.sdc
@@ -311,6 +311,5 @@
# Case analysis for quasi-static signals #
##########################################
-# assume a value of 0 for the pad attribute at index [9]
-#set_case_analysis 0 [get_pins u_padring/u_*_pad/attr_i[9]]
-set_case_analysis 0 [get_pins u_padring/gen_*gen_*u_*_pad/attr_i[9]]
+# assume a value of 0 for the open drain pad attribute
+set_case_analysis 0 [get_pins u_padring/*_pad/attr_i\[od_en\]]
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index fea3d9a..895c169 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -53,6 +53,7 @@
- lowrisc:tlul:headers
- lowrisc:prim:all
- lowrisc:prim:usb_diff_rx
+ - lowrisc:systems:top_earlgrey_pkg
files:
- rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
- rtl/autogen/top_earlgrey.sv
diff --git a/hw/top_earlgrey/top_earlgrey_asic.core b/hw/top_earlgrey/top_earlgrey_asic.core
index a7cdbd4..3b480d9 100644
--- a/hw/top_earlgrey/top_earlgrey_asic.core
+++ b/hw/top_earlgrey/top_earlgrey_asic.core
@@ -12,7 +12,7 @@
- "!fileset_partner ? (lowrisc:systems:ast)"
- "fileset_partner ? (partner:systems:ast)"
files:
- - rtl/top_earlgrey_asic.sv
+ - rtl/autogen/top_earlgrey_asic.sv
file_type: systemVerilogSource
files_verilator_waiver:
diff --git a/hw/top_earlgrey/top_earlgrey_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
index 0050c8f..658ab49 100644
--- a/hw/top_earlgrey/top_earlgrey_nexysvideo.core
+++ b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
@@ -12,7 +12,7 @@
- lowrisc:tool:top_earlgrey_nexysvideo_size_check
files:
- rtl/clkgen_xil7series.sv
- - rtl/top_earlgrey_nexysvideo.sv
+ - rtl/autogen/top_earlgrey_nexysvideo.sv
file_type: systemVerilogSource
files_constraints:
diff --git a/hw/top_englishbreakfast/clkgen_xil7series.core b/hw/top_englishbreakfast/clkgen_xil7series.core
new file mode 120000
index 0000000..c098f06
--- /dev/null
+++ b/hw/top_englishbreakfast/clkgen_xil7series.core
@@ -0,0 +1 @@
+../top_earlgrey/clkgen_xil7series.core
\ No newline at end of file
diff --git a/hw/top_englishbreakfast/data/pins_cw305.xdc b/hw/top_englishbreakfast/data/pins_cw305.xdc
index ca9a808..a6d678a 100644
--- a/hw/top_englishbreakfast/data/pins_cw305.xdc
+++ b/hw/top_englishbreakfast/data/pins_cw305.xdc
@@ -8,41 +8,41 @@
## set via clocks.xdc
## LEDs
-set_property -dict { PACKAGE_PIN T2 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IO_GP8 }]
-set_property -dict { PACKAGE_PIN T3 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IO_GP9 }]
-set_property -dict { PACKAGE_PIN T4 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IO_GP10 }]
+set_property -dict { PACKAGE_PIN T2 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB2 }]
+set_property -dict { PACKAGE_PIN T3 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB3 }]
+set_property -dict { PACKAGE_PIN T4 DRIVE 8 IOSTANDARD LVCMOS33 } [get_ports { IOB4 }]
## Buttons
-set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }]; #pushbutton
+set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { POR_N }]; #pushbutton
## Switches
-set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { IO_GP0 }]; #sw1
-set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { IO_GP1 }]; #sw2
-set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { IO_GP2 }]; #sw3
-set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { IO_GP3 }]; #sw4
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { IOA0 }]; #sw1
+set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { IOA1 }]; #sw2
+set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { IOA2 }]; #sw3
+set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { IOA3 }]; #sw4
## SPI/JTAG
-set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS0 }]; #SCK (USB_A13)
-set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS1 }]; #SDI (USB_A14)
-set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS2 }]; #SDO (USB_A15)
-set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS3 }]; #CSB (USB_A16)
-set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { IO_DPS4 }]; #JTAG TRST (USB_A17)
-set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_DPS5 }]; #JTAG SRST (USB_A18)
-set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IO_DPS6 }]; #JTAG/SPI (USB_A19)
-set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IO_DPS7 }]; #Bootstrap (USB_A20)
+set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CLK }]; #SCK (USB_A13)
+set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D0 }]; #SDI (USB_A14)
+set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D1 }]; #SDO (USB_A15)
+set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CS_L }]; #CSB (USB_A16)
+set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { IOC0 }]; #JTAG TRST (USB_A17)
+set_property -dict { PACKAGE_PIN D6 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #JTAG SRST (USB_A18)
+set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB10 }]; #JTAG/SPI (USB_A19)
+set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB11 }]; #Bootstrap (USB_A20)
## OTHER IO
-set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { IO_GP4 }]; #JP3.B16
-set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { IO_GP5 }]; #JP3.C13
-set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { IO_GP6 }]; #JP3.D15
-set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { IO_GP7 }]; #JP3.E15
-set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { IO_GP11 }]; #JP3.E13
-set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { IO_GP12 }]; #JP3.F15
-set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports { IO_GP13 }]; #JP3.E11
-set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { IO_GP14 }]; #JP3.F13
+set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { IOA4 }]; #JP3.B16
+set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS33 } [get_ports { IOA5 }]; #JP3.C13
+set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { IOB0 }]; #JP3.D15
+set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { IOB1 }]; #JP3.E15
+set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS33 } [get_ports { IOB5 }]; #JP3.E13
+set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { IOB6 }]; #JP3.F15
+set_property -dict { PACKAGE_PIN E11 IOSTANDARD LVCMOS33 } [get_ports { IOB7 }]; #JP3.E11
+set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { IOB8 }]; #JP3.F13
-set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DP0 }]; #JP3.C16
-set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN0 }]; #JP3.D13
+set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_P }]; #JP3.C16
+set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_N }]; #JP3.D13
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DPPULLUP0 }]; #JP3.H16
set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE0 }]; #JP3.D16
set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DNPULLUP0 }]; #JP3.E16
@@ -53,9 +53,9 @@
## 20-Pin Connector (JP1)
-set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { IO_UTX }]; #JP1 PIN 10 (UART)
-set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { IO_URX }]; #JP1 PIN 12 (UART)
-set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { IO_GP15 }]; #JP1 PIN 16 TIO4 (Trigger)
+set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { IOR3 }]; #JP1 PIN 10 (UART)
+set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { IOR2 }]; #JP1 PIN 12 (UART)
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { IOB9 }]; #JP1 PIN 16 TIO4 (Trigger)
set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { TIO_CLKOUT }]; #JP1 PIN 4 TIO_HS1. Clock sync capture board.
diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
index edf2691..c26ad14 100644
--- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -722,6 +722,9 @@
// ext is to create port in the top.
'external': {
+ // 'adc_ctrl_aon.adc' : 'adc'
+ 'ast.edn' : '',
+ 'ast.lc_dft_en' : '',
'ast.ram_1p_cfg' : 'ram_1p_cfg',
'ast.ram_2p_cfg' : 'ram_2p_cfg',
'ast.rom_cfg' : 'rom_cfg',
@@ -735,12 +738,17 @@
'eflash.flash_bist_enable' : 'flash_bist_enable',
'eflash.flash_power_down_h' : 'flash_power_down_h',
'eflash.flash_power_ready_h' : 'flash_power_ready_h',
- 'eflash.flash_test_mode_a' : 'flash_test_mode_a',
- 'eflash.flash_test_voltage_h' : 'flash_test_voltage_h',
+ # 'entropy_src.entropy_src_rng' : '',
+ # 'entropy_src.rng_fips' : '',
+ # 'peri.tl_ast' : '',
'pinmux_aon.dft_strap_test' : 'dft_strap_test'
'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast',
+ # 'otp_ctrl.otp_ast_pwr_seq' : '',
+ # 'otp_ctrl.otp_ast_pwr_seq_h' : '',
'sensor_ctrl_aon.ast_alert' : 'sensor_ctrl_ast_alert',
'sensor_ctrl_aon.ast_status' : 'sensor_ctrl_ast_status',
+ 'sensor_ctrl_aon.pinmux2ast' : '',
+ 'sensor_ctrl_aon.ast2pinmux' : '',
'usbdev.usb_ref_val' : '',
'usbdev.usb_ref_pulse' : '',
},
@@ -766,75 +774,223 @@
}
],
- // ===== INTERRUPT CTRL =====================================================
+ // ===== PINMUX & PINOUT ======================================================
- // RV_PLIC has two searching algorithm internally to pick the most highest priority interrupt
- // source. "sequential" is smaller but slower, "matrix" is larger but faster.
- // Choose depends on the criteria. Currently it is set to "matrix" to meet FPGA timing @ 50MHz
-
- // ===== ALERT HANDLER ======================================================
-
- // TODO: need to overhaul this datastructure.
- pinmux: {
-
- // Total number of Multiplexed I/O
- // All the input/outputs from IPs are muxed in pinmux, and it has # of I/O
- // talks to the outside of top_earlgrey.
- // This field will be replaced to the length of PAD if padctrl is defined
- num_mio: 44
-
- // Dedicated IO modules. The in/out ports of the modules below are connected
- // to TOP IO port through PADS directly. It bypasses PINMUX multiplexers
- dio_modules: [
- { name: "spi_device", pad: ["ChC[0..5]"] },
- { name: "spi_host0", pad: ["ChB[0..5]"] },
- { name: "usbdev", pad: ["ChA[0..8]"] },
- ],
-
- // Multiplexing IO modules. The in/out ports of the modules below are
- // connected through PINMUX, which gives controllability of the connection
- // between the modules and the IO PADS.
- // If `mio_modules` aren't defined, it uses all remaining modules from
- // module list except defined in `dio_modules`.
- mio_modules: ["gpio", "uart0"]
-
- // If any module isn't defined in above two lists, its inputs will be tied
- // to 0, and the output/OE signals will be floating (or connected to
- // unused signal). `rv_plic` is special module, shouldn't be defined here.
- nc_modules: ["rv_timer", "hmac"]
-
- // Number of wakeup detectors to instantiate, and bitwidth for the wakeup
- // counters. Note that all MIO pad inputs are connected to the wakeup detectors,
- // and there is no way to disable this. DIO inputs on the other hand are by
- // default not connected.
- // TODO: need to add mechanism to mark them as wakeup pins.
- num_wkup_detect: 8
- wkup_cnt_width: 8
-
- // Below fields are generated.
- // inputs: [
- // { name: "xxx", width: xx },
- // ]
- // outputs: [
- // { name: "xxx", width: xx },
- // ]
- // inouts: [
- // { name: "xxx", width: xx },
- // ]
- }
-
- // TODO: need to overhaul this datastructure.
- // PADS instantiation
- // Number of in/outs and the numer of PAD instances doesn't have to be
- // same. The number given below excludes clock/reset and other necessary
- // PADS but only defines GPIO pads.
- padctrl: {
- attr_default: ["STRONG"],
+ pinout: {
+ // IO power bank declaration.
+ // This list defines the IO bank power domains on the ASIC.
+ // Each individual pad must be in one of the declared power domains.
+ banks: ['VCC', 'AVCC', 'VIOA', 'VIOB'],
+ // Pad declaration.
+ // Each entry must have the following four keys:
+ //
+ // - name: Name of the pad (this will be exposed at the chiplevel).
+ //
+ // - type: Pad type (this maps to the pad types defined in prim_pad_wrapper_pkg.sv)
+ //
+ // - bank: Specifies in which of the IO power banks this pad lives.
+ //
+ // - connection: Can have either of the following values:
+ //
+ // 1) 'direct': This is a dedicated IO Pad that is directly connected to a peripheral.
+ //
+ // 2) 'manual': This is a dedicated IO signal that is not directly connected to a
+ // peripheral. It needs to be manually wired up in the template.
+ //
+ // 3) 'muxed': This is a muxed IO pad that will be connected to the pinmux.
+ //
+ // Optionally, each pad can also have a 'desc' field for further description.
pads: [
- { name: "ChA" type: "IO_33V", count: 32 }, // Accessing as ChA[0] .. ChA[31]
- { name: "ChB" type: "IO_33V", count: 4, attr: ["KEEP", "WEAK"]},
- { name: "ChC" type: "IO_33V", count: 4, attr: ["KEEP", "STRONG"]},
+ // TODO: this needs to be updated to the latest ASIC pinout.
+ // Dedicated
+ { name: 'POR_N' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'System reset'},
+ { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host data'},
+ { name: 'SPI_HOST_CLK' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host clock'},
+ { name: 'SPI_HOST_CS_L' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI host chip select'},
+ { name: 'SPI_DEV_D0' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D1' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D2' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_D3' , type: 'BidirStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device data'},
+ { name: 'SPI_DEV_CLK' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device clock'},
+ { name: 'SPI_DEV_CS_L' , type: 'InputStd', bank: 'VIOA', connection: 'direct', desc: 'SPI device chip select'},
+ { name: 'USB_P' , type: 'BidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB P signal'},
+ { name: 'USB_N' , type: 'BidirTol', bank: 'VCC' , connection: 'manual', desc: 'USB N signal'},
+ { name: 'CC1' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 1'},
+ { name: 'CC2' , type: 'InputStd', bank: 'AVCC', connection: 'manual', desc: 'ADC input 2'},
+ { name: 'FLASH_TEST_MODE0', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE1', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE2', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_MODE3', type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test mode signal'},
+ { name: 'FLASH_TEST_VOLT' , type: 'InputStd', bank: 'VCC' , connection: 'manual', desc: 'Flash test voltage input'},
+ // IOA
+ { name: 'IOA0' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA1' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA2' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA3' , type: 'InputStd', bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA4' , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOA5' , type: 'BidirOd' , bank: 'VIOA', connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOB
+ { name: 'IOB0' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB1' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB2' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB3' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB4' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB5' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB6' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB7' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB8' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB9' , type: 'BidirOd' , bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB10' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOB11' , type: 'InputStd', bank: 'VIOB', connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOC
+ { name: 'IOC0' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC1' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC2' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC3' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC4' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC5' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC6' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC7' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC8' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC9' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOC11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ // IOR
+ { name: 'IOR0' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR1' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR2' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR3' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR4' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR5' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR6' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR7' , type: 'InputStd', bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR8' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR9' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR10' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR11' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR12' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
+ { name: 'IOR13' , type: 'BidirOd' , bank: 'VCC' , connection: 'muxed' , desc: 'Muxed IO pad'},
]
}
+ pinmux: {
+ // Signal to pinmux/pad mapping.
+ // Each entry in the list below must have the following two mandatory keys:
+ //
+ // - instance: This is the comportable IO instance name where the IO signal comes from.
+ //
+ // - connection: Can have either of the following values:
+ //
+ // 1) 'direct': This is a dedicated IO signal that is directly connected to a pad.
+ // Such an IO signal must also specify the 'port' and 'pad' keys
+ // (see further below).
+ //
+ // 2) 'manual': This is a dedicated IO signal that is not directly connected to a pad.
+ // It needs to be manually wired up in the template.
+ // Such an IO signal may have a 'port' key, but no 'pad' key.
+ //
+ // 3) 'muxed': This is a muxed IO signal that will be connected to the pinmux.
+ // Such an IO signal may have a 'port' key, but no 'pad' key.
+ //
+ // Depending on the connection type specified, each entry may have the following optional keys:
+ //
+ // - port: Name of the available IO signal of the instance.
+ // This is required for 'direct' connections, but optional for the others.
+ // Individual signals of a bus IO signal must be indexed with square brackets, e.g. mybus[1].
+ // Not specifying this key or setting it to an empty string acts as a wild card
+ // and includes all available IOs of this instance.
+ //
+ // - pad: Name of the pad the 'direct' connection should connect to.
+ // This is not required for 'muxed' and 'manual' connections.
+ //
+ // - desc: Optional description field.
+ signals: [
+ // SPI Host0
+ { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''},
+ { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L', desc: ''},
+ { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''},
+ { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''},
+ // SPI Device
+ { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''},
+ { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''},
+ { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''},
+ { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''},
+ { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''},
+ { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''},
+ // USBDEV
+ { instance: 'usbdev', port: '', connection: 'manual', pad: '' , desc: ''},
+ // MIOs
+ { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''},
+ ],
+
+ // Number of wakeup detectors to instantiate, and bitwidth for the wakeup counters.
+ num_wkup_detect: 8
+ wkup_cnt_width: 8
+ }
+
+ // Implementation targets.
+ // This defines the configuration of the target-specific chip-levels to
+ // generate from the shared template. Each target uses the same base
+ // configuration for the pinmux and pinout as defined above, and the
+ // generated software constants for the pinmux DIF do not change among the
+ // implementation targets. However, in order to accommodate slight
+ // differences among the ASIC, FPGA emulation and simulation environments,
+ // it is possible to make very limited pinout changes below. In particular,
+ // it is possible to remove and tie-off specific pads, or add more 'manual'
+ // pads that need to be manually connected in the template. It is also possible
+ // to override the JTAG and strap locations indices, since the testing and DFT
+ // setups may differ among the targets.
+ targets: [
+ { name: 'cw305',
+ pinout: {
+ remove_pads: [
+ 'CC1', 'CC2',
+ 'IOC1', 'IOC2','IOC3','IOC4','IOC5','IOC6','IOC7','IOC8','IOC9','IOC10','IOC11',
+ 'SPI_DEV_D2', 'SPI_DEV_D3'
+ 'SPI_HOST_CLK', 'SPI_HOST_CS_L',
+ 'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3',
+ 'FLASH_TEST_VOLT',
+ 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1', 'FLASH_TEST_MODE2', 'FLASH_TEST_MODE3',
+ 'IOR0','IOR1','IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
+ ],
+
+ add_pads: [
+ // Additional infrastucture pads
+ { name: 'IO_CLK', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
+ { name: 'IO_JSRST_N', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Dedicated JTAG system reset input'}
+ // Custom USB pads
+ { name: 'IO_USB_SENSE0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
+ { name: 'IO_USB_DNPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
+ { name: 'IO_USB_DPPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
+ // ChipWhisperer IO
+ { name: 'TIO_CLKOUT', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual clock output for SCA setup'}
+ { name: 'IO_UTX_DEBUG', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual UART TX debug output' }
+ ],
+ }
+
+ pinmux: {
+ special_signals: [
+ // Straps
+ { name: 'tap0', pad: 'IOC2' , desc: 'TAP strap signal, maps to a stubbed-off MIO.' },
+ { name: 'tap1', pad: 'IOB10', desc: 'TAP strap signal, maps to MIO pad 16.' },
+ { name: 'dft0', pad: 'IOC3' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
+ { name: 'dft1', pad: 'IOC4' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
+ // JTAG
+ { name: 'tck', pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.' },
+ { name: 'tms', pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.' },
+ { name: 'trst_n', pad: 'IOC0' , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
+ { name: 'tdi', pad: 'SPI_DEV_D0' , desc: 'JTAG tdi signal, overlaid on SPI_DEV.' },
+ { name: 'tdo', pad: 'SPI_DEV_D1' , desc: 'JTAG tdo signal, overlaid on SPI_DEV.' },
+ ],
+ }
+ }
+ ]
}
diff --git a/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv b/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv
deleted file mode 100644
index d070fb5..0000000
--- a/hw/top_englishbreakfast/rtl/top_englishbreakfast_cw305.sv
+++ /dev/null
@@ -1,378 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_englishbreakfast_cw305 #(
- // Path to a VMEM file containing the contents of the boot ROM, which will be
- // baked into the FPGA bitstream.
- parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem"
-) (
- // Clock and Reset
- input IO_CLK,
- input IO_RST_N,
- // JTAG interface
- inout IO_DPS0, // IO_JTCK, IO_SDCK
- inout IO_DPS3, // IO_JTMS, IO_SDCSB
- inout IO_DPS1, // IO_JTDI, IO_SDSDI
- inout IO_DPS4, // IO_JTRST_N,
- inout IO_DPS5, // IO_JSRST_N,
- inout IO_DPS2, // IO_JTDO, IO_SDO
- inout IO_DPS6, // JTAG=1, SPI=0
- inout IO_DPS7, // BOOTSTRAP=1
- // UART interface
- inout IO_URX,
- inout IO_UTX,
- // USB interface
- inout IO_USB_DP0,
- inout IO_USB_DN0,
- inout IO_USB_SENSE0,
- inout IO_USB_DNPULLUP0,
- inout IO_USB_DPPULLUP0,
- // GPIO x 16 interface
- inout IO_GP0,
- inout IO_GP1,
- inout IO_GP2,
- inout IO_GP3,
- inout IO_GP4,
- inout IO_GP5,
- inout IO_GP6,
- inout IO_GP7,
- inout IO_GP8,
- inout IO_GP9,
- inout IO_GP10,
- inout IO_GP11,
- inout IO_GP12,
- inout IO_GP13,
- inout IO_GP14,
- inout IO_GP15,
- // ChipWhisperer IO
- output TIO_CLKOUT,
- output IO_UTX_DEBUG
-);
-
- import top_englishbreakfast_pkg::*;
-
- //////////////////////
- // Padring Instance //
- //////////////////////
-
-
- logic clk_main, clk_usb_48mhz, clk_aon, rst_n;
- logic [pinmux_reg_pkg::NMioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] mio_attr;
- logic [pinmux_reg_pkg::NDioPads-1:0][pinmux_reg_pkg::AttrDw-1:0] dio_attr;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_core;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_core;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_core;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_out_core;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe_core;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_in_core;
-
- padring #(
- // MIOs 43:34 and 31:20 are currently not
- // connected to pads and hence tied off
- .ConnectMioIn ( 44'h003_000F_FFFF ),
- .ConnectMioOut ( 44'h003_000F_FFFF ),
- // Tied off DIOs:
- // 2: usbdev_d
- // 3: usbdev_suspend
- // 4: usbdev_tx_mode
- // 7: usbdev_se
- // 9-14: spi_host all signals
- // 17-18: spi_device unused quad signals
- .ConnectDioIn ( 21'h19_8163 ),
- .ConnectDioOut ( 21'h19_8163 ),
- // MIO pad types
- .MioPadVariant ( { // RBox
- 2'd3, // IOR13 -- open drain
- 2'd3, // IOR12 -- open drain
- 2'd3, // IOR11 -- open drain
- 2'd3, // IOR10 -- open drain
- 2'd3, // IOR9 -- open drain
- 2'd3, // IOR8 -- open drain
- 2'd0, // IOR7 -- bidir
- 2'd0, // IOR6 -- bidir
- 2'd0, // IOR5 -- bidir
- 2'd0, // IOR4 -- bidir
- 2'd0, // IOR3 -- bidir
- 2'd0, // IOR2 -- bidir
- 2'd0, // IOR1 -- bidir
- 2'd0, // IOR0 -- bidir
- // Bank C
- 2'd3, // IOC11 -- open drain
- 2'd3, // IOC10 -- open drain
- 2'd3, // IOC9 -- open drain
- 2'd3, // IOC8 -- open drain
- 2'd0, // IOC7 -- bidir
- 2'd0, // IOC6 -- bidir
- 2'd0, // IOC5 -- bidir
- 2'd0, // IOC4 -- bidir
- 2'd0, // IOC3 -- bidir
- 2'd0, // IOC2 -- bidir
- 2'd0, // IOC1 -- bidir
- 2'd0, // IOC0 -- bidir
- // Bank B
- 2'd3, // IOB11 -- open drain
- 2'd3, // IOB10 -- open drain
- 2'd3, // IOB9 -- open drain
- 2'd3, // IOB8 -- open drain
- 2'd0, // IOB7 -- birid
- 2'd0, // IOB6 -- birid
- 2'd0, // IOB5 -- birid
- 2'd0, // IOB4 -- birid
- 2'd0, // IOB3 -- bidir
- 2'd0, // IOB2 -- bidir
- 2'd0, // IOB1 -- bidir
- 2'd0, // IOB0 -- bidir
- // Bank A
- 2'd3, // IOA5 -- open drain
- 2'd3, // IOA4 -- open drain
- 2'd0, // IOA3 -- bidir
- 2'd0, // IOA2 -- bidir
- 2'd0, // IOA1 -- bidir
- 2'd0 // IOA0 -- bidir
- } ),
- // DIO pad types
- .DioPadVariant ( { 2'd1, // SPI_DEV_CLK -- input only
- 2'd1, // SPI_DEV_CS_L -- input only
- 2'd0, // SPI_DEV_D3 -- bidir
- 2'd0, // SPI_DEV_D2 -- bidir
- 2'd0, // SPI_DEV_D1 -- bidir
- 2'd0, // SPI_DEV_D0 -- bidir
- 2'd0, // SPI_HOST_CLK -- bidir
- 2'd0, // SPI_HOST_CS_L -- bidir
- 2'd0, // SPI_HOST_D3 -- bidir
- 2'd0, // SPI_HOST_D2 -- bidir
- 2'd0, // SPI_HOST_D1 -- bidir
- 2'd0, // SPI_HOST_D0 -- bidir
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd0, // unused
- 2'd2, // USB_P -- tolerant
- 2'd2 // USB_N -- tolerant
- } )
- ) padring (
- // Clk / Rst
- .clk_pad_i ( 1'b0 ),
- .rst_pad_ni ( 1'b0 ),
- .clk_o ( ),
- .rst_no ( ),
- .cc1_i ( 1'b0 ),
- .cc2_i ( 1'b0 ),
- // MIO Pads
- .mio_pad_io ( { 10'bz, // Note that 43:34 are currently not mapped
- IO_UTX,
- IO_URX,
- 12'bz, // Note that 31:20 are currently not mapped
- IO_DPS5, // Use GPIO19 to pass JTAG_SRST
- IO_DPS4, // Use GPIO18 to pass JTAG_TRST
- IO_DPS7, // Use GPIO17 to pass rom boot_strap indication
- IO_DPS6, // Use GPIO16 to pass SPI/JTAG control flag
- IO_GP15,
- IO_GP14,
- IO_GP13,
- IO_GP12,
- IO_GP11,
- IO_GP10,
- IO_GP9,
- IO_GP8,
- IO_GP7,
- IO_GP6,
- IO_GP5,
- IO_GP4,
- IO_GP3,
- IO_GP2,
- IO_GP1,
- IO_GP0 } ),
- // DIO Pads
- .dio_pad_io ( { IO_DPS0, // SCK, JTAG_TCK
- IO_DPS3, // CSB, JTAG_TMS
- 2'bz, // quad SPI device signals are not mapped
- IO_DPS2, // SDO, JTAG_TDO
- IO_DPS1, // SDI, JTAG_TDI
- 6'bz, // SPI host signals are not mapped
- IO_USB_SENSE0,
- 1'bz, // usbdev_se0
- IO_USB_DPPULLUP0,
- IO_USB_DNPULLUP0,
- 1'bz, // usbdev_tx_mode
- 1'bz, // usbdev_suspend
- 1'bz, // usbdev_d
- IO_USB_DP0,
- IO_USB_DN0 } ),
- // Muxed IOs
- .mio_in_o ( mio_in_core ),
- .mio_out_i ( mio_out ),
- .mio_oe_i ( mio_oe_core ),
- // Dedicated IOs
- .dio_in_o ( dio_in_core ),
- .dio_out_i ( dio_out_core ),
- .dio_oe_i ( dio_oe_core ),
- // Pad Attributes
- .mio_attr_i ( mio_attr ),
- .dio_attr_i ( dio_attr )
- );
-
- //////////////////
- // PLL for FPGA //
- //////////////////
-
- // TODO: This needs to become a dedicated custom pin for FPGAs
- logic jtag_srst_n;
- assign jtag_srst_n = mio_in_core[19];
-
- clkgen_xil7series # (
- .AddClkBuf(0)
- ) clkgen (
- .IO_CLK,
- .IO_RST_N,
- .jtag_srst_n,
- .clk_main(clk_main),
- .clk_48MHz(clk_usb_48mhz),
- .clk_aon(clk_aon),
- .rst_n(rst_n)
- );
-
- //////////////////////
- // Top-level design //
- //////////////////////
- pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
- ast_pkg::ast_alert_req_t ast_base_alerts;
- ast_pkg::ast_status_t ast_base_status;
-
- assign ast_base_pwr.slow_clk_val = 1'b1;
- assign ast_base_pwr.core_clk_val = 1'b1;
- assign ast_base_pwr.io_clk_val = 1'b1;
- assign ast_base_pwr.usb_clk_val = 1'b1;
- assign ast_base_pwr.main_pok = 1'b1;
-
- ast_pkg::ast_dif_t silent_alert = '{
- p: 1'b0,
- n: 1'b1
- };
- assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
- assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
-
- // the rst_ni pin only goes to AST
- // the rest of the logic generates reset based on the 'pok' signal.
- // for verilator purposes, make these two the same.
- lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
-
- // TODO: this is temporary and will be removed in the future.
- // This specifies the tie-off values of the muxed MIO/DIOs
- // when the JTAG is active. SPI CSB is active low.
- localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << (
- pinmux_reg_pkg::NMioPads + top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceCsb));
-
- // DFT and Debug signal positions in the pinout.
- // TODO: generate these indices from the target-specific
- // pinout configuration.
- localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
- const_sampling: 1'b1,
- tie_offs: TieOffValues,
- tck_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSck,
- tms_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceCsb,
- trst_idx: 18, // MIO 18
- tdi_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSd0,
- tdo_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSd1,
- tap_strap0_idx: 20, // MIO 20 (tied off)
- tap_strap1_idx: 16, // MIO 16 (used as JTAG/SPI select signal)
- dft_strap0_idx: 21, // MIO 21 (tied off)
- dft_strap1_idx: 22 // MIO 22 (tied off)
- };
-
- top_englishbreakfast #(
- .AesMasking(1'b1),
- .AesSBoxImpl(aes_pkg::SBoxImplDom),
- .SecAesStartTriggerDelay(40),
- .SecAesAllowForcingMasks(1'b1),
- .SecAesSkipPRNGReseeding(1'b1),
- .IbexRegFile(ibex_pkg::RegFileFPGA),
- .IbexICache(0),
- .IbexPipeLine(1),
- .BootRomInitFile(BootRomInitFile),
- .PinmuxAonTargetCfg(PinmuxTargetCfg)
- ) top_englishbreakfast (
- // Clocks, resets
- .rst_ni ( rst_n ),
- .clk_main_i ( clk_main ),
- .clk_io_i ( clk_main ),
- .clk_usb_i ( clk_usb_48mhz ),
- .clk_aon_i ( clk_aon ),
- .pwrmgr_ast_req_o ( ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
- .usbdev_usb_ref_val_o ( ),
- .usbdev_usb_ref_pulse_o ( ),
- .flash_bist_enable_i ( 1'b0 ),
- .flash_power_down_h_i ( 1'b0 ),
- .flash_power_ready_h_i ( 1'b1 ),
- .ast_clk_byp_req_o ( lc_clk_bypass ),
- .ast_clk_byp_ack_i ( lc_clk_bypass ),
- .clks_ast_o ( ),
- .rsts_ast_o ( ),
-
- // Multiplexed I/O
- .mio_in_i ( mio_in_core ),
- .mio_out_o ( mio_out_core ),
- .mio_oe_o ( mio_oe_core ),
-
- // Dedicated I/O
- .dio_in_i ( dio_in_core ),
- .dio_out_o ( dio_out_core ),
- .dio_oe_o ( dio_oe_core ),
-
- // Pad attributes
- .mio_attr_o ( mio_attr ),
- .dio_attr_o ( dio_attr ),
-
- // Memory attributes
- .ram_1p_cfg_i ( '0 ),
- .ram_2p_cfg_i ( '0 ),
- .rom_cfg_i ( '0 ),
-
- // DFT signals
- .scan_rst_ni ( 1'b1 ),
- .scan_en_i ( 1'b0 ),
- .scanmode_i ( lc_ctrl_pkg::Off )
- );
-
- //////////////////////////////////////
- // Generate precise capture trigger //
- //////////////////////////////////////
-
- // GPIO15 is used as capture trigger.
- localparam int MioIdxTrigger = 15;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
-
- for (genvar i = 0; i < pinmux_reg_pkg::NMioPads; i++) begin : gen_mio_out
- if (i == MioIdxTrigger) begin
- // To obtain a more precise capture trigger for side-channel analysis, we only forward the
- // software-controlled capture trigger when the AES module is actually busy (performing
- // either encryption/decryption or clearing internal registers).
- assign mio_out[i] = mio_out_core[i] & ~top_englishbreakfast.clkmgr_aon_idle[clkmgr_pkg::Aes];
- end else begin
- assign mio_out[i] = mio_out_core[i];
- end
- end
-
- //////////////////////
- // ChipWhisperer IO //
- //////////////////////
-
- // Clock ouput to capture board.
- assign TIO_CLKOUT = IO_CLK;
-
- // UART Tx for debugging. The UART itself is connected to the capture board.
- assign IO_UTX_DEBUG = top_englishbreakfast.cio_uart0_tx_d2p;
-
-endmodule : top_englishbreakfast_cw305
diff --git a/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
index 519c1d8..30b8343 100644
--- a/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
+++ b/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
@@ -8,8 +8,7 @@
input rst_ni
);
- logic cio_jtag_tck, cio_jtag_tms, cio_jtag_tdi, cio_jtag_tdo;
- logic cio_jtag_trst_n, cio_jtag_srst_n;
+ import top_englishbreakfast_pkg::*;
logic [31:0] cio_gpio_p2d, cio_gpio_d2p, cio_gpio_en_d2p;
logic cio_uart_rx_p2d, cio_uart_tx_d2p, cio_uart_tx_en_d2p;
@@ -35,47 +34,36 @@
logic [20:0] dio_out;
logic [20:0] dio_oe;
- assign dio_in = {cio_spi_device_sck_p2d,
- cio_spi_device_csb_p2d,
- 1'b0,
- 1'b0,
- 1'b0,
- cio_spi_device_sdi_p2d,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- cio_usbdev_sense_p2d,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- 1'b0,
- cio_usbdev_d_p2d,
- cio_usbdev_dp_p2d,
- cio_usbdev_dn_p2d};
+ always_comb begin : assign_dio_in
+ dio_in = '0;
+ dio_in[DioSpiDeviceSck] = cio_spi_device_sck_p2d;
+ dio_in[DioSpiDeviceCsb] = cio_spi_device_csb_p2d;
+ dio_in[DioSpiDeviceSd0] = cio_spi_device_sdi_p2d;
+ dio_in[DioUsbdevSense] = cio_usbdev_sense_p2d;
+ dio_in[DioUsbdevD] = cio_usbdev_d_p2d;
+ dio_in[DioUsbdevDp] = cio_usbdev_dp_p2d;
+ dio_in[DioUsbdevDn] = cio_usbdev_dn_p2d;
+ end
- assign cio_usbdev_dn_d2p = dio_out[0];
- assign cio_usbdev_dp_d2p = dio_out[1];
- assign cio_usbdev_d_d2p = dio_out[2];
- assign cio_usbdev_suspend_d2p = dio_out[3];
- assign cio_usbdev_tx_mode_se_d2p = dio_out[4];
- assign cio_usbdev_dn_pullup_d2p = dio_out[5];
- assign cio_usbdev_dp_pullup_d2p = dio_out[6];
- assign cio_usbdev_se0_d2p = dio_out[7];
- assign cio_spi_device_sdo_d2p = dio_out[16];
+ assign cio_usbdev_dn_d2p = dio_out[DioUsbdevDn];
+ assign cio_usbdev_dp_d2p = dio_out[DioUsbdevDp];
+ assign cio_usbdev_d_d2p = dio_out[DioUsbdevD];
+ assign cio_usbdev_suspend_d2p = dio_out[DioUsbdevSuspend];
+ assign cio_usbdev_tx_mode_se_d2p = dio_out[DioUsbdevTxModeSe];
+ assign cio_usbdev_dn_pullup_d2p = dio_out[DioUsbdevDnPullup];
+ assign cio_usbdev_dp_pullup_d2p = dio_out[DioUsbdevDpPullup];
+ assign cio_usbdev_se0_d2p = dio_out[DioUsbdevSe0];
+ assign cio_spi_device_sdo_d2p = dio_out[DioSpiDeviceSd1];
- assign cio_usbdev_dn_en_d2p = dio_oe[0];
- assign cio_usbdev_dp_en_d2p = dio_oe[1];
- assign cio_usbdev_d_en_d2p = dio_oe[2];
- assign cio_usbdev_suspend_en_d2p = dio_oe[3];
- assign cio_usbdev_tx_mode_se_en_d2p = dio_oe[4];
- assign cio_usbdev_dn_pullup_en_d2p = dio_oe[5];
- assign cio_usbdev_dp_pullup_en_d2p = dio_oe[6];
- assign cio_usbdev_se0_en_d2p = dio_oe[7];
- assign cio_spi_device_sdo_en_d2p = dio_oe[16];
+ assign cio_usbdev_dn_en_d2p = dio_oe[DioUsbdevDn];
+ assign cio_usbdev_dp_en_d2p = dio_oe[DioUsbdevDp];
+ assign cio_usbdev_d_en_d2p = dio_oe[DioUsbdevD];
+ assign cio_usbdev_suspend_en_d2p = dio_oe[DioUsbdevSuspend];
+ assign cio_usbdev_tx_mode_se_en_d2p = dio_oe[DioUsbdevTxModeSe];
+ assign cio_usbdev_dn_pullup_en_d2p = dio_oe[DioUsbdevDnPullup];
+ assign cio_usbdev_dp_pullup_en_d2p = dio_oe[DioUsbdevDpPullup];
+ assign cio_usbdev_se0_en_d2p = dio_oe[DioUsbdevSe0];
+ assign cio_spi_device_sdo_en_d2p = dio_oe[DioSpiDeviceSd1];
logic [43:0] mio_in;
logic [43:0] mio_out;
@@ -105,14 +93,19 @@
p: 1'b0,
n: 1'b1
};
+
assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
- assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
+
+ // the rst_ni pin only goes to AST
+ // the rest of the logic generates reset based on the 'pok' signal.
+ // for verilator purposes, make these two the same.
logic clk_aon;
// reset is not used below becuase verilator uses only sync resets
// and also does not under 'x'.
// if we allow the divider below to reset, clk_aon will be silenced,
- // and as a result all the clk_aon logic inside top_earlgrey does not
+ // and as a result all the clk_aon logic inside top_englishbreakfast does not
// get reset
prim_clock_div #(
.Divisor(4)
@@ -125,30 +118,34 @@
.clk_o(clk_aon)
);
- // DFT and Debug signal positions in the pinout.
// TODO: generate these indices from the target-specific
- // pinout configuration.
+ // pinout configuration. But first, this verilator top needs
+ // to be split into a Verilator TB and a Verilator chiplevel.
+ // DFT and Debug signal positions in the pinout.
localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
const_sampling: 1'b1,
tie_offs: '0,
tck_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSck,
+ top_englishbreakfast_pkg::DioSpiDeviceSck,
tms_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceCsb,
+ top_englishbreakfast_pkg::DioSpiDeviceCsb,
trst_idx: 18, // MIO 18
tdi_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSd0,
+ top_englishbreakfast_pkg::DioSpiDeviceSd0,
tdo_idx: pinmux_reg_pkg::NMioPads +
- top_englishbreakfast_pkg::TopEnglishbreakfastDioPinSpiDeviceSd1,
+ top_englishbreakfast_pkg::DioSpiDeviceSd1,
tap_strap0_idx: 26, // MIO 26
tap_strap1_idx: 16, // MIO 16 (this is different in the ASIC top)
dft_strap0_idx: 21, // MIO 21
- dft_strap1_idx: 22 // MIO 22
+ dft_strap1_idx: 22, // MIO 22
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevDp,
+ usb_dn_idx: DioUsbdevDn,
+ usb_dp_pullup_idx: DioUsbdevDpPullup,
+ usb_dn_pullup_idx: DioUsbdevDnPullup
};
- // the rst_ni pin only goes to AST
- // the rest of the logic generates reset based on the 'pok' signal.
- // for verilator purposes, make these two the same.
+ lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
// Top-level design
top_englishbreakfast #(
.AesMasking(1'b1),
@@ -161,43 +158,52 @@
.SramCtrlMainInstrExec(1),
.PinmuxAonTargetCfg(PinmuxTargetCfg)
) top_englishbreakfast (
- .rst_ni (rst_ni),
- .clk_main_i (clk_i),
- .clk_io_i (clk_i),
- .clk_usb_i (clk_i),
- .clk_aon_i (clk_aon),
- .pwrmgr_ast_req_o ( ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
- .sensor_ctrl_ast_alert_rsp_o ( ),
- .sensor_ctrl_ast_status_i ( ast_base_status ),
- .usbdev_usb_ref_val_o ( ),
- .usbdev_usb_ref_pulse_o ( ),
- .flash_power_down_h_i ( '0 ),
- .flash_power_ready_h_i ( 1'b1 ),
+ .rst_ni (rst_ni ),
+ .clk_main_i (clk_i ),
+ .clk_io_i (clk_i ),
+ .clk_usb_i (clk_i ),
+ .clk_aon_i (clk_aon ),
+ .clks_ast_o ( ),
+ .clk_main_jitter_en_o ( ),
+ .rsts_ast_o ( ),
+ .pwrmgr_ast_req_o ( ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
+ .sensor_ctrl_ast_alert_rsp_o ( ),
+ .sensor_ctrl_ast_status_i ( ast_base_status ),
+ .usbdev_usb_ref_val_o ( ),
+ .usbdev_usb_ref_pulse_o ( ),
+ .ast_edn_req_i ( '0 ),
+ .ast_edn_rsp_o ( ),
+ .flash_bist_enable_i ( lc_ctrl_pkg::Off ),
+ .flash_power_down_h_i ( 1'b0 ),
+ .flash_power_ready_h_i ( 1'b1 ),
+ .ast_clk_byp_req_o ( lc_clk_bypass ),
+ .ast_clk_byp_ack_i ( lc_clk_bypass ),
// Multiplexed I/O
- .mio_in_i (mio_in),
- .mio_out_o (mio_out),
- .mio_oe_o (mio_oe),
+ .mio_in_i (mio_in),
+ .mio_out_o (mio_out),
+ .mio_oe_o (mio_oe),
// Dedicated I/O
- .dio_in_i (dio_in),
- .dio_out_o (dio_out),
- .dio_oe_o (dio_oe),
+ .dio_in_i (dio_in),
+ .dio_out_o (dio_out),
+ .dio_oe_o (dio_oe),
// Pad attributes
- .mio_attr_o ( ),
- .dio_attr_o ( ),
+ .mio_attr_o ( ),
+ .dio_attr_o ( ),
// Memory attributes
- .ram_1p_cfg_i ('0),
- .ram_2p_cfg_i ('0),
- .rom_cfg_i ('0),
+ .ram_1p_cfg_i ('0),
+ .ram_2p_cfg_i ('0),
+ .rom_cfg_i ('0),
// DFT signals
- .scan_rst_ni (1'b1),
- .scanmode_i (lc_ctrl_pkg::Off)
+ .scan_rst_ni (1'b1),
+ .scan_en_i (1'b0),
+ .scanmode_i (lc_ctrl_pkg::Off)
);
// GPIO DPI
@@ -210,10 +216,9 @@
);
// UART DPI
- // The baud rate set to match FPGA implementation; the frequency is
- // "artificial".
- // Both baud rate and frequency must match the settings used in the on-chip
- // software.
+ // The baud rate set to match FPGA implementation; the frequency is "artificial". Both baud rate
+ // frequency must match the settings used in the on-chip software at
+ // `sw/device/lib/arch/device_sim_verilator.c`.
uartdpi #(
.BAUD('d7_200),
.FREQ('d500_000)
@@ -241,18 +246,22 @@
.dmi_rst_n (dmi_rst_n)
);
`else
- // JTAG DPI for OpenOCD
- jtagdpi u_jtagdpi (
- .clk_i,
- .rst_ni,
+ // TODO: this is currently not supported.
+ // connect this to the correct pins once pinout is final and once the
+ // verilator testbench supports DFT/Debug strap sampling.
+ // See also #5221.
+ //
+ // jtagdpi u_jtagdpi (
+ // .clk_i,
+ // .rst_ni,
- .jtag_tck (cio_jtag_tck),
- .jtag_tms (cio_jtag_tms),
- .jtag_tdi (cio_jtag_tdi),
- .jtag_tdo (cio_jtag_tdo),
- .jtag_trst_n (cio_jtag_trst_n),
- .jtag_srst_n (cio_jtag_srst_n)
- );
+ // .jtag_tck (cio_jtag_tck),
+ // .jtag_tms (cio_jtag_tms),
+ // .jtag_tdi (cio_jtag_tdi),
+ // .jtag_tdo (cio_jtag_tdo),
+ // .jtag_trst_n (cio_jtag_trst_n),
+ // .jtag_srst_n (cio_jtag_srst_n)
+ // );
`endif
// SPI DPI
@@ -334,6 +343,7 @@
if (u_sw_test_status_if.sw_test_done) begin
$display("Verilator sim termination requested");
$display("Your simulation wrote to 0x%h", u_sw_test_status_if.sw_test_status_addr);
+ dv_test_status_pkg::dv_test_status(u_sw_test_status_if.sw_test_passed);
$finish;
end
end
diff --git a/hw/top_englishbreakfast/top_englishbreakfast_cw305.core b/hw/top_englishbreakfast/top_englishbreakfast_cw305.core
index bfd0b5c..3ce1f54 100644
--- a/hw/top_englishbreakfast/top_englishbreakfast_cw305.core
+++ b/hw/top_englishbreakfast/top_englishbreakfast_cw305.core
@@ -10,9 +10,6 @@
depend:
- lowrisc:systems:top_englishbreakfast:0.1
- lowrisc:systems:topgen
- files:
- - rtl/clkgen_xil7series.sv
- - rtl/top_englishbreakfast_cw305.sv
file_type: systemVerilogSource
files_constraints:
diff --git a/hw/top_englishbreakfast/top_englishbreakfast_verilator.core b/hw/top_englishbreakfast/top_englishbreakfast_verilator.core
index 42ed261..53508a7 100644
--- a/hw/top_englishbreakfast/top_englishbreakfast_verilator.core
+++ b/hw/top_englishbreakfast/top_englishbreakfast_verilator.core
@@ -20,6 +20,8 @@
- lowrisc:ibex:ibex_tracer
- lowrisc:dv:sim_sram
- lowrisc:dv:sw_test_status
+ - lowrisc:dv:dv_test_status
+ - lowrisc:prim:clock_div
files:
- rtl/top_englishbreakfast_verilator.sv: { file_type: systemVerilogSource }
diff --git a/sw/device/lib/pinmux.c b/sw/device/lib/pinmux.c
index a26f0fc..aa4191f 100644
--- a/sw/device/lib/pinmux.c
+++ b/sw/device/lib/pinmux.c
@@ -11,18 +11,12 @@
#define PINMUX0_BASE_ADDR TOP_EARLGREY_PINMUX_AON_BASE_ADDR
-// TODO: autogenerated constants for this will be available once
-// the pinmux datastructure has been overhauled.
#define NUM_GPIO 32
-#define UART_RX_PERIPH_IDX 32
-#define UART_TX_PERIPH_IDX 32
-#define MIO_32_IOR2_IDX 32
-#define MIO_33_IOR3_IDX 33
-static void init_pinmux_reg(uint32_t reg, uint32_t mask, uint32_t start_v) {
+static void init_gpio_regs(uint32_t reg, uint32_t mask, uint32_t start_v) {
mmio_region_t reg32 = mmio_region_from_addr(reg);
uint32_t reg_value = start_v;
- uint32_t reg_offset = 0;
+ uint32_t reg_offset = kTopEarlgreyPinmuxPeripheralInGpioGpio0 << 2;
// We've got 32 GPIOs
for (uint32_t i = 0; i < NUM_GPIO; ++i) {
@@ -38,28 +32,32 @@
// available, 2) the pinmux and padring design is finalized.
// input: assign MIO0..MIO31 to GPIO0..GPIO31
- init_pinmux_reg(PINMUX0_BASE_ADDR + PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET,
- PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK,
- PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET);
+ init_gpio_regs(PINMUX0_BASE_ADDR + PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET,
+ PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK,
+ PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET);
// output: assign GPIO0..GPIO31 to MIO0..MIO31
- init_pinmux_reg(PINMUX0_BASE_ADDR + PINMUX_MIO_OUTSEL_0_REG_OFFSET,
- PINMUX_MIO_OUTSEL_0_OUT_0_MASK,
- PINMUX_PERIPH_OUTSEL_IDX_OFFSET);
+ init_gpio_regs(PINMUX0_BASE_ADDR + PINMUX_MIO_OUTSEL_0_REG_OFFSET,
+ PINMUX_MIO_OUTSEL_0_OUT_0_MASK,
+ PINMUX_PERIPH_OUTSEL_IDX_OFFSET);
- // Configure UART RX input to connect to MIO pad 32
+ // Configure UART RX input to connect to MIO pad IOR2
mmio_region_t reg32 = mmio_region_from_addr(
PINMUX0_BASE_ADDR + PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET);
- uint32_t reg_value = MIO_32_IOR2_IDX + PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET;
- uint32_t reg_offset = UART_RX_PERIPH_IDX << 2;
+ uint32_t reg_value = kTopEarlgreyPinmuxInselIor2;
+ // We've got one insel configuration field per register. Hence, we have to
+ // convert the enumeration index into a byte address using << 2.
+ uint32_t reg_offset = kTopEarlgreyPinmuxPeripheralInUart0Rx << 2;
uint32_t mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK;
mmio_region_write32(reg32, reg_offset, reg_value & mask);
- // Configure UART TX output to connect to MIO pad 33
+ // Configure UART TX output to connect to MIO pad IOR3
reg32 =
mmio_region_from_addr(PINMUX0_BASE_ADDR + PINMUX_MIO_OUTSEL_0_REG_OFFSET);
- reg_value = UART_TX_PERIPH_IDX + PINMUX_PERIPH_OUTSEL_IDX_OFFSET;
- reg_offset = MIO_33_IOR3_IDX << 2;
+ reg_value = kTopEarlgreyPinmuxOutselUart0Tx;
+ // We've got one insel configuration field per register. Hence, we have to
+ // convert the enumeration index into a byte address using << 2.
+ reg_offset = kTopEarlgreyPinmuxMioOutIor3 << 2;
mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK;
mmio_region_write32(reg32, reg_offset, reg_value & mask);
}
diff --git a/util/reggen/ip_block.py b/util/reggen/ip_block.py
index 9ff7786..a0d31f7 100644
--- a/util/reggen/ip_block.py
+++ b/util/reggen/ip_block.py
@@ -338,3 +338,21 @@
for rb in self.reg_blocks.values():
ret = ret.union(set(rb.name_to_offset.keys()))
return ret
+
+ def get_signals_as_list_of_dicts(self) -> List[Dict]:
+ '''Look up and return signal by name'''
+ result = []
+ for iodir, xput in zip(('inout', 'input', 'output'), self.xputs):
+ for sig in xput:
+ result.append(sig.as_nwt_dict(iodir))
+ return result
+
+ def get_signal_by_name_as_dict(self, name: str) -> Dict:
+ '''Look up and return signal by name'''
+ sig_list = self.get_signals_as_list_of_dicts()
+ for sig in sig_list:
+ if sig['name'] == name:
+ return sig
+ else:
+ raise ValueError("Signal {} does not exist in IP block {}"
+ .format(name, self.name))
diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py
index ed7fe2f..09f7be0 100644
--- a/util/topgen-fusesoc.py
+++ b/util/topgen-fusesoc.py
@@ -134,6 +134,9 @@
'filesets': {
'files_rtl': {
'depend': [
+ # Ibex and OTBN constants
+ 'lowrisc:ibex:ibex_pkg',
+ 'lowrisc:ip:otbn_pkg',
# flash_ctrl
'lowrisc:constants:top_pkg',
'lowrisc:prim:util',
@@ -151,6 +154,8 @@
# ast and sensor_ctrl not auto-generated, re-used from top_earlgrey
'lowrisc:systems:sensor_ctrl',
'lowrisc:systems:ast_pkg',
+ # TODO: absorb this into AST longerm
+ 'lowrisc:systems:clkgen_xil7series',
],
'files': [
# IPs
@@ -164,6 +169,10 @@
'rtl/autogen/%s_rnd_cnst_pkg.sv' % topname,
'rtl/autogen/%s_pkg.sv' % topname,
'rtl/autogen/%s.sv' % topname,
+ # TODO: this is not ideal. we should extract
+ # this info from the target configuration and
+ # possibly generate separate core files for this.
+ 'rtl/autogen/%s_cw305.sv' % topname,
],
'file_type': 'systemVerilogSource'
},
diff --git a/util/topgen.py b/util/topgen.py
index e14f447..696c75e 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -273,141 +273,69 @@
fout.write(genhdr + gencmd + out)
-# returns the dedicated pin positions of a particular module
-# For example, if a module is connected to 6:1 of the dio connections,
-# [6, 1] will be returned.
-def _calc_dio_pin_pos(top, mname):
- dios = top["pinmux"]["dio"]
-
- last_index = dios.index(dios[-1])
- bit_pos = []
- first_index = False
-
- for dio in dios:
- if dio['module_name'] == mname and not first_index:
- bit_pos.append(last_index - dios.index(dio))
- first_index = True
- elif first_index and dio['module_name'] != mname:
- bit_pos.append(last_index - dios.index(dio) - 1)
-
- # The last one, need to insert last element if only the msb
- # position is found
- if len(bit_pos) == 1:
- bit_pos.append(0)
-
- log.debug("bit pos {}".format(bit_pos))
- return bit_pos
-
-
-def _find_dio_pin_pos(top, sname):
- dios = top["pinmux"]["dio"]
-
- last_index = dios.index(dios[-1])
- bit_pos = -1
-
- for dio in dios:
- if dio['name'] == sname:
- bit_pos = last_index - dios.index(dio)
-
- if bit_pos < 0:
- log.error("Could not find bit position of {} in dios".format(sname))
-
- return bit_pos
-
-
def generate_pinmux(top, out_path):
- topname = top["name"]
- # MIO Pads
- n_mio_pads = top["pinmux"]["num_mio"]
- if n_mio_pads <= 0:
- # TODO: add support for no MIO case
- log.error("Topgen does currently not support generation of a top " +
- "without a pinmux.")
- return
- if "padctrl" not in top:
- # TODO: add support for no MIO case
- log.error("Topgen does currently not support generation of a top " +
- "without a padctrl instance.")
- return
+ topname = top['name']
+ pinmux = top['pinmux']
+
+ # Generation without pinmux and pinout configuration is not supported.
+ assert 'pinmux' in top
+ assert 'pinout' in top
# Get number of wakeup detectors
- if "num_wkup_detect" in top["pinmux"]:
- num_wkup_detect = top["pinmux"]["num_wkup_detect"]
+ if 'num_wkup_detect' in pinmux:
+ num_wkup_detect = pinmux['num_wkup_detect']
else:
num_wkup_detect = 1
if num_wkup_detect <= 0:
# TODO: add support for no wakeup counter case
- log.error("Topgen does currently not support generation of a top " +
- "without DIOs.")
+ log.error('Topgen does currently not support generation of a top ' +
+ 'without DIOs.')
return
- if "wkup_cnt_width" in top["pinmux"]:
- wkup_cnt_width = top["pinmux"]["wkup_cnt_width"]
+ if 'wkup_cnt_width' in pinmux:
+ wkup_cnt_width = pinmux['wkup_cnt_width']
else:
wkup_cnt_width = 8
if wkup_cnt_width <= 1:
- log.error("Wakeup counter width must be greater equal 2.")
+ log.error('Wakeup counter width must be greater equal 2.')
return
+ # MIO Pads
+ n_mio_pads = pinmux['io_counts']['muxed']['pads']
+
# Total inputs/outputs
- # Validation ensures that the width field is present.
- num_mio_inputs = sum([x["width"] for x in top["pinmux"]["inputs"]])
- num_mio_outputs = sum([x["width"] for x in top["pinmux"]["outputs"]])
-
- num_dio_inputs = sum([
- x["width"] if x["type"] == "input" else 0 for x in top["pinmux"]["dio"]
- ])
- num_dio_outputs = sum([
- x["width"] if x["type"] == "output" else 0
- for x in top["pinmux"]["dio"]
- ])
- num_dio_inouts = sum([
- x["width"] if x["type"] == "inout" else 0 for x in top["pinmux"]["dio"]
- ])
-
- n_mio_periph_in = num_mio_inputs
- n_mio_periph_out = num_mio_outputs
- n_dio_periph_in = num_dio_inouts + num_dio_inputs
- n_dio_periph_out = num_dio_inouts + num_dio_outputs
- n_dio_pads = num_dio_inouts + num_dio_inputs + num_dio_outputs
+ # Reuse the counts from the merge phase
+ n_mio_periph_in = (pinmux['io_counts']['muxed']['inouts'] +
+ pinmux['io_counts']['muxed']['inputs'])
+ n_mio_periph_out = (pinmux['io_counts']['muxed']['inouts'] +
+ pinmux['io_counts']['muxed']['outputs'])
+ n_dio_periph_in = (pinmux['io_counts']['dedicated']['inouts'] +
+ pinmux['io_counts']['dedicated']['inputs'])
+ n_dio_periph_out = (pinmux['io_counts']['dedicated']['inouts'] +
+ pinmux['io_counts']['dedicated']['outputs'])
+ n_dio_pads = (pinmux['io_counts']['dedicated']['inouts'] +
+ pinmux['io_counts']['dedicated']['inputs'] +
+ pinmux['io_counts']['dedicated']['outputs'])
# TODO: derive this value
- attr_dw = 10
+ attr_dw = 13
- if n_dio_pads <= 0:
- # TODO: add support for no DIO case
- log.error("Topgen does currently not support generation of a top " +
- "without DIOs.")
- return
+ # Generation with zero MIO/DIO pads is currently not supported.
+ assert (n_mio_pads > 0)
+ assert (n_dio_pads > 0)
- # find the start and end pin positions for usbdev
- usb_pin_pos = _calc_dio_pin_pos(top, "usbdev")
- usb_start_pos = usb_pin_pos[-1]
- n_usb_pins = usb_pin_pos[0] - usb_pin_pos[-1] + 1
- usb_dp_sel = _find_dio_pin_pos(top, "usbdev_dp")
- usb_dn_sel = _find_dio_pin_pos(top, "usbdev_dn")
- usb_dp_pull_sel = _find_dio_pin_pos(top, "usbdev_dp_pullup")
- usb_dn_pull_sel = _find_dio_pin_pos(top, "usbdev_dn_pullup")
-
- log.info("Generating pinmux with following info from hjson:")
- log.info("num_mio_inputs: %d" % num_mio_inputs)
- log.info("num_mio_outputs: %d" % num_mio_outputs)
- log.info("num_dio_inputs: %d" % num_dio_inputs)
- log.info("num_dio_outputs: %d" % num_dio_outputs)
- log.info("attr_dw: %d" % attr_dw)
- log.info("num_wkup_detect: %d" % num_wkup_detect)
- log.info("wkup_cnt_width: %d" % wkup_cnt_width)
- log.info("This translates to:")
- log.info("n_mio_periph_in: %d" % n_mio_periph_in)
- log.info("n_mio_periph_out: %d" % n_mio_periph_out)
- log.info("n_dio_periph_in: %d" % n_dio_periph_in)
- log.info("n_dio_periph_out: %d" % n_dio_periph_out)
- log.info("n_dio_pads: %d" % n_dio_pads)
- log.info("usb_start_pos: %d" % usb_start_pos)
- log.info("n_usb_pins: %d" % n_usb_pins)
+ log.info('Generating pinmux with following info from hjson:')
+ log.info('attr_dw: %d' % attr_dw)
+ log.info('num_wkup_detect: %d' % num_wkup_detect)
+ log.info('wkup_cnt_width: %d' % wkup_cnt_width)
+ log.info('n_mio_periph_in: %d' % n_mio_periph_in)
+ log.info('n_mio_periph_out: %d' % n_mio_periph_out)
+ log.info('n_dio_periph_in: %d' % n_dio_periph_in)
+ log.info('n_dio_periph_out: %d' % n_dio_periph_out)
+ log.info('n_dio_pads: %d' % n_dio_pads)
# Target path
# rtl: pinmux_reg_pkg.sv & pinmux_reg_top.sv
@@ -431,11 +359,6 @@
with tpl_path.open(mode='r', encoding='UTF-8') as fin:
hjson_tpl = Template(fin.read())
try:
- # TODO: pass in information about always-on peripherals
- # TODO: pass in information on which DIOs can be selected
- # as wakeup signals
- # TODO: pass in signal names such that we can introduce
- # named enums for select signals
out = hjson_tpl.render(
n_mio_periph_in=n_mio_periph_in,
n_mio_periph_out=n_mio_periph_out,
@@ -448,13 +371,7 @@
n_dio_pads=n_dio_pads,
attr_dw=attr_dw,
n_wkup_detect=num_wkup_detect,
- wkup_cnt_width=wkup_cnt_width,
- usb_start_pos=usb_start_pos,
- n_usb_pins=n_usb_pins,
- usb_dp_sel=usb_dp_sel,
- usb_dn_sel=usb_dn_sel,
- usb_dp_pull_sel=usb_dp_pull_sel,
- usb_dn_pull_sel=usb_dn_pull_sel
+ wkup_cnt_width=wkup_cnt_width
)
except: # noqa: E722
log.error(exceptions.text_error_template().render())
@@ -798,8 +715,8 @@
block = name_to_block[block_name]
if "attr" in module:
if module["attr"] not in ['templated', 'reggen_top', 'reggen_only']:
- raise ValueError('Unsupported value for attr field of {}: {!r}'.
- format(block_name, module["attr"]))
+ raise ValueError('Unsupported value for attr field of {}: {!r}'
+ .format(inst_name, module["attr"]))
attrs[inst_name] = module["attr"]
inst_to_block[inst_name] = block_name
@@ -1177,6 +1094,14 @@
out_path / f"rtl/autogen/top_{topname}.sv",
gencmd=gencmd)
+ # TODO: chiplevel renaming
+ # Multiple chip-levels (ASIC, FPGA, Verilator, etc)
+ for target in topcfg['targets']:
+ render_template(TOPGEN_TEMPLATE_PATH / "chiplevel.sv.tpl",
+ out_path / f"rtl/autogen/top_{topname}_{target['name']}.sv",
+ gencmd=gencmd,
+ target=target)
+
# The C / SV file needs some complex information, so we initialize this
# object to store it.
c_helper = TopGenC(completecfg, name_to_block)
diff --git a/util/topgen/c.py b/util/topgen/c.py
index cca58c8..58760a3 100644
--- a/util/topgen/c.py
+++ b/util/topgen/c.py
@@ -9,52 +9,11 @@
from mako.template import Template
-from .lib import get_base_and_size
+from .lib import get_base_and_size, Name
from reggen.ip_block import IpBlock
-class Name(object):
- """We often need to format names in specific ways; this class does so."""
- def __add__(self, other):
- return Name(self.parts + other.parts)
-
- @staticmethod
- def from_snake_case(input):
- return Name(input.split("_"))
-
- def __init__(self, parts):
- self.parts = list(parts)
- for p in parts:
- assert len(p) > 0, "cannot add zero-length name piece"
-
- def as_snake_case(self):
- return "_".join([p.lower() for p in self.parts])
-
- def as_camel_case(self):
- out = ""
- for p in self.parts:
- # If we're about to join two parts which would introduce adjacent
- # numbers, put an underscore between them.
- if out[-1:].isnumeric() and p[:1].isnumeric():
- out += "_" + p
- else:
- out += p.capitalize()
- return out
-
- def as_c_define(self):
- return "_".join([p.upper() for p in self.parts])
-
- def as_c_enum(self):
- return "k" + self.as_camel_case()
-
- def as_c_type(self):
- return self.as_snake_case() + "_t"
-
- def remove_part(self, part_to_remove):
- return Name([p for p in self.parts if p != part_to_remove])
-
-
class MemoryRegion(object):
def __init__(self, name: Name, base_addr: int, size_bytes: int):
assert isinstance(base_addr, int)
@@ -337,63 +296,63 @@
Insel and outsel have some special values which are captured here too.
"""
- pinmux_info = self.top["pinmux"]
+ pinmux_info = self.top['pinmux']
+ pinout_info = self.top['pinout']
# Peripheral Inputs
peripheral_in = CEnum(self._top_name +
- Name(["pinmux", "peripheral", "in"]))
- for signal in pinmux_info["inputs"]:
- if "width" in signal and int(signal["width"]) != 1:
- for i in range(int(signal["width"])):
- name = Name.from_snake_case(signal["name"]) + Name(
- [str(i)])
- peripheral_in.add_constant(name,
- docstring="{} {}".format(
- signal["name"], i))
- else:
- peripheral_in.add_constant(Name.from_snake_case(
- signal["name"]),
- docstring=signal["name"])
- peripheral_in.add_last_constant("Last valid peripheral input")
+ Name(['pinmux', 'peripheral', 'in']))
+ i = 0
+ for sig in pinmux_info['ios']:
+ if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'input']:
+ index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([])
+ name = Name.from_snake_case(sig['name']) + index
+ peripheral_in.add_constant(name, docstring='Peripheral Input {}'.format(i))
+ i += 1
+
+ peripheral_in.add_last_constant('Last valid peripheral input')
# Pinmux Input Selects
- insel = CEnum(self._top_name + Name(["pinmux", "insel"]))
- insel.add_constant(Name(["constant", "zero"]),
- docstring="Tie constantly to zero")
- insel.add_constant(Name(["constant", "one"]),
- docstring="Tie constantly to one")
- for i in range(int(pinmux_info["num_mio"])):
- insel.add_constant(Name(["mio", str(i)]),
- docstring="MIO Pad {}".format(i))
- insel.add_last_constant("Last valid insel value")
+ insel = CEnum(self._top_name + Name(['pinmux', 'insel']))
+ insel.add_constant(Name(['constant', 'zero']),
+ docstring='Tie constantly to zero')
+ insel.add_constant(Name(['constant', 'one']),
+ docstring='Tie constantly to one')
+ i = 0
+ for pad in pinout_info['pads']:
+ if pad['connection'] == 'muxed':
+ insel.add_constant(Name([pad['name']]),
+ docstring='MIO Pad {}'.format(i))
+ i += 1
+ insel.add_last_constant('Last valid insel value')
# MIO Outputs
- mio_out = CEnum(self._top_name + Name(["pinmux", "mio", "out"]))
- for i in range(int(pinmux_info["num_mio"])):
- mio_out.add_constant(Name([str(i)]),
- docstring="MIO Pad {}".format(i))
- mio_out.add_last_constant("Last valid mio output")
+ mio_out = CEnum(self._top_name + Name(['pinmux', 'mio', 'out']))
+ i = 0
+ for pad in pinout_info['pads']:
+ if pad['connection'] == 'muxed':
+ mio_out.add_constant(Name.from_snake_case(pad['name']),
+ docstring='MIO Pad {}'.format(i))
+ i += 1
+ mio_out.add_last_constant('Last valid mio output')
# Pinmux Output Selects
- outsel = CEnum(self._top_name + Name(["pinmux", "outsel"]))
- outsel.add_constant(Name(["constant", "zero"]),
- docstring="Tie constantly to zero")
- outsel.add_constant(Name(["constant", "one"]),
- docstring="Tie constantly to one")
- outsel.add_constant(Name(["constant", "high", "z"]),
- docstring="Tie constantly to high-Z")
- for signal in pinmux_info["outputs"]:
- if "width" in signal and int(signal["width"]) != 1:
- for i in range(int(signal["width"])):
- name = Name.from_snake_case(signal["name"]) + Name(
- [str(i)])
- outsel.add_constant(name,
- docstring="{} {}".format(
- signal["name"], i))
- else:
- outsel.add_constant(Name.from_snake_case(signal["name"]),
- docstring=signal["name"])
- outsel.add_last_constant("Last valid outsel value")
+ outsel = CEnum(self._top_name + Name(['pinmux', 'outsel']))
+ outsel.add_constant(Name(['constant', 'zero']),
+ docstring='Tie constantly to zero')
+ outsel.add_constant(Name(['constant', 'one']),
+ docstring='Tie constantly to one')
+ outsel.add_constant(Name(['constant', 'high', 'z']),
+ docstring='Tie constantly to high-Z')
+ i = 0
+ for sig in pinmux_info['ios']:
+ if sig['connection'] == 'muxed' and sig['type'] in ['inout', 'output']:
+ index = Name([str(sig['idx'])]) if sig['idx'] != -1 else Name([])
+ name = Name.from_snake_case(sig['name']) + index
+ outsel.add_constant(name, docstring='Peripheral Output {}'.format(i))
+ i += 1
+
+ outsel.add_last_constant('Last valid outsel value')
self.pinmux_peripheral_in = peripheral_in
self.pinmux_insel = insel
diff --git a/util/topgen/intermodule.py b/util/topgen/intermodule.py
index 3ca186a..6a07eb7 100644
--- a/util/topgen/intermodule.py
+++ b/util/topgen/intermodule.py
@@ -60,7 +60,7 @@
return result
-def get_suffixes(ims: OrderedDict) -> (str, str):
+def get_suffixes(ims: OrderedDict) -> Tuple[str, str]:
"""Get suffixes of the struct.
TL-UL struct uses `h2d`, `d2h` suffixes for req, rsp pair.
diff --git a/util/topgen/lib.py b/util/topgen/lib.py
index 53018ef..7c93133 100644
--- a/util/topgen/lib.py
+++ b/util/topgen/lib.py
@@ -8,7 +8,7 @@
from collections import OrderedDict
from copy import deepcopy
from pathlib import Path
-from typing import Dict, Optional, Tuple
+from typing import Dict, Optional, Tuple, List
import hjson
@@ -21,6 +21,61 @@
from .intermodule import get_dangling_im_def # noqa : F401 # isort:skip
+class Name:
+ """
+ We often need to format names in specific ways; this class does so.
+
+ To simplify parsing and reassembling of name strings, this class
+ stores the name parts as a canonical list of strings internally
+ (in self.parts).
+
+ The "from_*" functions parse and split a name string into the canonical
+ list, whereas the "as_*" functions reassemble the canonical list in the
+ format specified.
+
+ For example, ex = Name.from_snake_case("example_name") gets split into
+ ["example", "name"] internally, and ex.as_camel_case() reassembles this
+ internal representation into "ExampleName".
+ """
+ def __add__(self, other):
+ return Name(self.parts + other.parts)
+
+ @staticmethod
+ def from_snake_case(input: str) -> 'Name':
+ return Name(input.split("_"))
+
+ def __init__(self, parts: List[str]):
+ self.parts = parts
+ for p in parts:
+ assert len(p) > 0, "cannot add zero-length name piece"
+
+ def as_snake_case(self) -> str:
+ return "_".join([p.lower() for p in self.parts])
+
+ def as_camel_case(self) -> str:
+ out = ""
+ for p in self.parts:
+ # If we're about to join two parts which would introduce adjacent
+ # numbers, put an underscore between them.
+ if out[-1:].isnumeric() and p[:1].isnumeric():
+ out += "_" + p
+ else:
+ out += p.capitalize()
+ return out
+
+ def as_c_define(self) -> str:
+ return "_".join([p.upper() for p in self.parts])
+
+ def as_c_enum(self) -> str:
+ return "k" + self.as_camel_case()
+
+ def as_c_type(self) -> str:
+ return self.as_snake_case() + "_t"
+
+ def remove_part(self, part_to_remove: str) -> "Name":
+ return Name([p for p in self.parts if p != part_to_remove])
+
+
def is_ipcfg(ip: Path) -> bool: # return bool
log.info("IP Path: %s" % repr(ip))
ip_name = ip.parents[1].name
@@ -365,3 +420,14 @@
assert isinstance(base_addr, int)
return (base_addr, size_byte)
+
+
+def get_io_enum_literal(sig: Dict, prefix: str) -> str:
+ """Returns the DIO pin enum literal with value assignment"""
+ name = Name.from_snake_case(prefix) + Name.from_snake_case(sig["name"])
+ # In this case, the signal is a multibit signal, and hence
+ # we have to make the signal index part of the parameter
+ # name to uniquify it.
+ if sig['width'] > 1:
+ name += Name([str(sig['idx'])])
+ return name.as_camel_case()
diff --git a/util/topgen/merge.py b/util/topgen/merge.py
index d0e0683..bd0f71e 100644
--- a/util/topgen/merge.py
+++ b/util/topgen/merge.py
@@ -6,7 +6,6 @@
import random
from collections import OrderedDict
from copy import deepcopy
-from functools import partial
from math import ceil, log2
from typing import Dict, List
@@ -852,127 +851,186 @@
topcfg["inter_module"]["connect"]))
-def amend_pinmux_io(top: OrderedDict, name_to_block: Dict[str, IpBlock]):
- """ Check dio_modules/ mio_modules. If not exists, add all modules to mio
- """
- pinmux = top["pinmux"]
+def append_io_signal(temp: Dict, sig_inst: Dict) -> None:
+ '''Appends the signal to the correct list'''
+ if sig_inst['type'] == 'inout':
+ temp['inouts'].append(sig_inst)
+ if sig_inst['type'] == 'input':
+ temp['inputs'].append(sig_inst)
+ if sig_inst['type'] == 'output':
+ temp['outputs'].append(sig_inst)
- if "dio_modules" not in pinmux:
- pinmux['dio_modules'] = []
- # list out dedicated IO
- pinmux['dio'] = []
- for e in pinmux["dio_modules"]:
- # Check name if it is module or signal
- mname, sname = lib.get_ms_name(e["name"])
+def get_index_and_incr(ctrs: Dict, connection: str, io_dir: str) -> Dict:
+ '''Get correct index counter and increment'''
- # Parse how many signals
- m = lib.get_module_by_name(top, mname)
+ if connection != 'muxed':
+ connection = 'dedicated'
- if m is None:
- raise SystemExit("Module {} in `dio_modules`"
- " is not searchable.".format(mname))
-
- if sname is not None:
- signals = deepcopy([lib.get_signal_by_name(m, sname)])
+ if io_dir in 'inout':
+ result = ctrs[connection]['inouts']
+ ctrs[connection]['inouts'] += 1
+ elif connection == 'muxed':
+ # For MIOs, the input/output arrays differ in RTL
+ # I.e., the input array contains {inputs, inouts}, whereas
+ # the output array contains {outputs, inouts}.
+ if io_dir == 'input':
+ result = ctrs[connection]['inputs'] + ctrs[connection]['inouts']
+ ctrs[connection]['inputs'] += 1
+ elif io_dir == 'output':
+ result = ctrs[connection]['outputs'] + ctrs[connection]['inouts']
+ ctrs[connection]['outputs'] += 1
else:
- # Get all module signals
- block = name_to_block[m['type']]
- inouts, inputs, outputs = block.xputs
- signals = ([s.as_nwt_dict('input') for s in inputs] +
- [s.as_nwt_dict('output') for s in outputs] +
- [s.as_nwt_dict('inout') for s in inouts])
+ assert(0) # should not happen
+ else:
+ # For DIOs, the input/output arrays are identical in terms of index layout.
+ # Unused inputs are left unconnected and unused outputs are tied off.
+ if io_dir == 'input':
+ result = ctrs[connection]['inputs'] + ctrs[connection]['inouts']
+ ctrs[connection]['inputs'] += 1
+ elif io_dir == 'output':
+ result = (ctrs[connection]['outputs'] +
+ ctrs[connection]['inouts'] +
+ ctrs[connection]['inputs'])
+ ctrs[connection]['outputs'] += 1
+ else:
+ assert(0) # should not happen
- sig_width = sum([s["width"] for s in signals])
+ return result
- # convert signal with module name
- signals = list(
- map(partial(lib.add_module_prefix_to_signal, module=mname),
- signals))
- # Parse how many pads are assigned
- if "pad" not in e:
- raise SystemExit("Should catch pad field in validate.py!")
- # pads are the list of individual pin, each entry is 1 bit width
- pads = []
- for p in e["pad"]:
- pads += lib.get_pad_list(p)
+def amend_pinmux_io(top: Dict, name_to_block: Dict[str, IpBlock]):
+ """ Process pinmux/pinout configuration and assign available IOs
+ """
+ pinmux = top['pinmux']
+ pinout = top['pinout']
+ targets = top['targets']
- # check if #sig and #pads are matched
- if len(pads) != sig_width:
- raise SystemExit("# Pads and # Sig (%s) aren't same: %d" %
- (mname, sig_width))
+ temp = {}
+ temp['inouts'] = []
+ temp['inputs'] = []
+ temp['outputs'] = []
- # add info to pads["dio"]
- for s in signals:
- p = pads[:s["width"]]
- pads = pads[s["width"]:]
- s["pad"] = p
- pinmux["dio"].append(s)
+ for sig in pinmux['signals']:
+ # Get the signal information from the IP block type of this instance/
+ mod_name = sig['instance']
+ m = lib.get_module_by_name(top, mod_name)
- dio_names = [p["name"] for p in pinmux["dio"]]
-
- # Multiplexer IO
- if "mio_modules" not in pinmux:
- # Add all modules having available io to Multiplexer IO
- pinmux["mio_modules"] = []
-
- for m in top["module"]:
- num_io = len(m["available_input_list"] +
- m["available_output_list"] +
- m["available_inout_list"])
- if num_io != 0:
- # Add if not in dio_modules
- pinmux["mio_modules"].append(m["name"])
-
- # List up the dedicated IO to exclude from inputs/outputs
-
- # Add port list to `inputs` and `outputs` fields
- if "inputs" not in pinmux:
- pinmux["inputs"] = []
- if "outputs" not in pinmux:
- pinmux["outputs"] = []
-
- for e in pinmux["mio_modules"]:
- tokens = e.split('.')
- if len(tokens) not in [1, 2]:
- raise SystemExit(
- "Cannot parse signal/module in mio_modules {}".format(e))
- # Add all ports from the module to input/outputs
- m = lib.get_module_by_name(top, tokens[0])
if m is None:
- raise SystemExit("Module {} doesn't exist".format(tokens[0]))
+ raise SystemExit("Module {} is not searchable.".format(mod_name))
- mod_name = m['name'].lower()
+ block = name_to_block[m['type']]
- if len(tokens) == 1:
- block = name_to_block[m['type']]
- inouts, inputs, outputs = block.xputs
- for signal in inouts:
- rel = signal.as_nwt_dict('inout')
- qual = lib.add_module_prefix_to_signal(rel, mod_name)
- if qual['name'] not in dio_names:
- pinmux['inputs'].append(qual)
- pinmux['outputs'].append(qual)
+ # If the signal is explicitly named.
+ if sig['port'] != '':
- for signal in inputs:
- rel = signal.as_nwt_dict('input')
- qual = lib.add_module_prefix_to_signal(rel, mod_name)
- if qual['name'] not in dio_names:
- pinmux['inputs'].append(qual)
+ # If this is a bus signal with explicit indexes.
+ if '[' in sig['port']:
+ name_split = sig['port'].split('[')
+ sig_name = name_split[0]
+ idx = int(name_split[1][:-1])
+ else:
+ idx = -1
+ sig_name = sig['port']
- for signal in outputs:
- rel = signal.as_nwt_dict('output')
- qual = lib.add_module_prefix_to_signal(rel, mod_name)
- if qual['name'] not in dio_names:
- pinmux['outputs'].append(qual)
+ sig_inst = deepcopy(block.get_signal_by_name_as_dict(sig_name))
- elif len(tokens) == 2:
- # Current version doesn't consider signal in mio_modules
- # only in dio_modules
- raise SystemExit(
- "Curren version doesn't support signal in mio_modules {}".
- format(e))
+ if idx >= 0 and idx >= sig_inst['width']:
+ raise SystemExit("Index {} is out of bounds for signal {}"
+ " with width {}.".format(idx, sig_name, sig_inst['width']))
+ if idx == -1 and sig_inst['width'] != 1:
+ raise SystemExit("Bus signal {} requires an index.".format(sig_name))
+
+ # If we got this far we know that the signal is valid and exists.
+ # Augment this signal instance with additional information.
+ sig_inst.update({'idx': idx,
+ 'pad': sig['pad'],
+ 'connection': sig['connection']})
+ sig_inst['name'] = mod_name + '_' + sig_inst['name']
+ append_io_signal(temp, sig_inst)
+
+ # Otherwise the name is a wildcard for selecting all available IO signals
+ # of this block and we need to extract them here one by one signals here.
+ else:
+ sig_list = deepcopy(block.get_signals_as_list_of_dicts())
+
+ for sig_inst in sig_list:
+ # If this is a multibit signal, unroll the bus and
+ # generate a single bit IO signal entry for each one.
+ if sig_inst['width'] > 1:
+ for idx in range(sig_inst['width']):
+ sig_inst_copy = deepcopy(sig_inst)
+ sig_inst_copy.update({'idx': idx,
+ 'pad': sig['pad'],
+ 'connection': sig['connection']})
+ sig_inst_copy['name'] = sig['instance'] + '_' + sig_inst_copy['name']
+ append_io_signal(temp, sig_inst_copy)
+ else:
+ sig_inst.update({'idx': -1,
+ 'pad': sig['pad'],
+ 'connection': sig['connection']})
+ sig_inst['name'] = sig['instance'] + '_' + sig_inst['name']
+ append_io_signal(temp, sig_inst)
+
+ # Now that we've collected all input and output signals,
+ # we can go through once again and stack them into one unified
+ # list, and calculate MIO/DIO global indices.
+ pinmux['ios'] = (temp['inouts'] +
+ temp['inputs'] +
+ temp['outputs'])
+
+ # Remember these counts to facilitate the RTL generation
+ pinmux['io_counts'] = {'dedicated': {'inouts': 0, 'inputs': 0, 'outputs': 0, 'pads': 0},
+ 'muxed': {'inouts': 0, 'inputs': 0, 'outputs': 0, 'pads': 0}}
+
+ for sig in pinmux['ios']:
+ glob_idx = get_index_and_incr(pinmux['io_counts'], sig['connection'], sig['type'])
+ sig['glob_idx'] = glob_idx
+
+ # Calculate global indices for pads.
+ j = k = 0
+ for pad in pinout['pads']:
+ if pad['connection'] == 'muxed':
+ pad['idx'] = j
+ j += 1
+ else:
+ pad['idx'] = k
+ k += 1
+ pinmux['io_counts']['muxed']['pads'] = j
+ pinmux['io_counts']['dedicated']['pads'] = k
+
+ # For each target configuration, calculate the special signal indices.
+ known_muxed_pads = {}
+ for pad in pinout['pads']:
+ if pad['connection'] == 'muxed':
+ known_muxed_pads[pad['name']] = pad
+
+ known_mapped_dio_pads = {}
+ for sig in pinmux['ios']:
+ if sig['connection'] in ['muxed', 'manual']:
+ continue
+ if sig['pad'] in known_mapped_dio_pads:
+ raise SystemExit('Cannot have multiple IOs mapped to the same DIO pad {}'
+ .format(sig['pad']))
+ known_mapped_dio_pads[sig['pad']] = sig
+
+ for target in targets:
+ for entry in target['pinmux']['special_signals']:
+ # If this is a muxed pad, the resolution is
+ # straightforward. I.e., we just assign the MIO index.
+ if entry['pad'] in known_muxed_pads:
+ entry['idx'] = known_muxed_pads[entry['pad']]['idx']
+ # Otherwise we need to find out which DIO this pad is mapped to.
+ # Note that we can't have special_signals that are manual, since
+ # there needs to exist a DIO connection.
+ elif entry['pad'] in known_mapped_dio_pads:
+ # This index refers to the stacked {dio, mio} array
+ # on the chip-level, hence we have to add the amount of MIO pads.
+ idx = (known_mapped_dio_pads[entry['pad']]['glob_idx'] +
+ pinmux['io_counts']['muxed']['pads'])
+ entry['idx'] = idx
+ else:
+ assert(0) # Entry should be guaranteed to exist at this point
def merge_top(topcfg: OrderedDict,
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
new file mode 100644
index 0000000..eea403f
--- /dev/null
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -0,0 +1,1190 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+${gencmd}
+<%
+import re
+import topgen.lib as lib
+from copy import deepcopy
+
+# Provide shortcuts for some commonly used variables
+pinmux = top['pinmux']
+pinout = top['pinout']
+
+num_mio_inputs = pinmux['io_counts']['muxed']['inouts'] + \
+ pinmux['io_counts']['muxed']['inputs']
+num_mio_outputs = pinmux['io_counts']['muxed']['inouts'] + \
+ pinmux['io_counts']['muxed']['outputs']
+num_mio_pads = pinmux['io_counts']['muxed']['pads']
+
+num_dio_inputs = pinmux['io_counts']['dedicated']['inouts'] + \
+ pinmux['io_counts']['dedicated']['inputs']
+num_dio_outputs = pinmux['io_counts']['dedicated']['inouts'] + \
+ pinmux['io_counts']['dedicated']['outputs']
+num_dio_total = pinmux['io_counts']['dedicated']['inouts'] + \
+ pinmux['io_counts']['dedicated']['inputs'] + \
+ pinmux['io_counts']['dedicated']['outputs']
+
+def get_dio_sig(pinmux: {}, pad: {}):
+ '''Get DIO signal associated with this pad or return None'''
+ for sig in pinmux["ios"]:
+ if sig["connection"] == "direct" and pad["name"] == sig["pad"]:
+ return sig
+ else:
+ return None
+
+# Modify the pad lists on the fly, based on target config
+maxwidth = 0
+muxed_pads = []
+dedicated_pads = []
+k = 0
+for pad in pinout["pads"]:
+ if pad["connection"] == "muxed":
+ if pad["name"] not in target["pinout"]["remove_pads"]:
+ maxwidth = max(maxwidth, len(pad["name"]))
+ muxed_pads.append(pad)
+ else:
+ k = pad["idx"]
+ if pad["name"] not in target["pinout"]["remove_pads"]:
+ maxwidth = max(maxwidth, len(pad["name"]))
+ dedicated_pads.append(pad)
+
+for pad in target["pinout"]["add_pads"]:
+ # Since these additional pads have not been elaborated in the merge phase,
+ # we need to add their global index here.
+ amended_pad = deepcopy(pad)
+ amended_pad.update({"idx" : k})
+ dedicated_pads.append(pad)
+ k += 1
+
+num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]])
+
+max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["ios"]])
+max_sigwidth = len("{}".format(max_sigwidth))
+
+clks_attr = top['clocks']
+cpu_clk = top['clocks']['hier_paths']['top'] + "clk_proc_main"
+cpu_rst = top["reset_paths"]["sys"]
+dm_rst = top["reset_paths"]["lc"]
+esc_clk = top['clocks']['hier_paths']['top'] + "clk_io_div4_timers"
+esc_rst = top["reset_paths"]["sys_io_div4"]
+
+unused_resets = lib.get_unused_resets(top)
+unused_im_defs, undriven_im_defs = lib.get_dangling_im_def(top["inter_signal"]["definitions"])
+
+%>\
+// TODO: change the naming to chip_${top["name"]}_${target["name"]}
+% if target["name"] != "asic":
+module top_${top["name"]}_${target["name"]} #(
+ // Path to a VMEM file containing the contents of the boot ROM, which will be
+ // baked into the FPGA bitstream.
+ parameter BootRomInitFile = "boot_rom_fpga_${target["name"]}.32.vmem",
+ // Path to a VMEM file containing the contents of the emulated OTP, which will be
+ // baked into the FPGA bitstream.
+ parameter OtpCtrlMemInitFile = "otp_img_fpga_${target["name"]}.vmem"
+) (
+% else:
+module top_${top["name"]}_${target["name"]} (
+% endif
+<%
+
+%>\
+ // Dedicated Pads
+% for pad in dedicated_pads:
+<%
+ sig = get_dio_sig(pinmux, pad)
+ if sig is not None:
+ comment = "// Dedicated Pad for {}".format(sig["name"])
+ else:
+ comment = "// Manual Pad"
+%>\
+ inout ${pad["name"]}, ${comment}
+% endfor
+
+ // Muxed Pads
+% for pad in muxed_pads:
+ inout ${pad["name"]}${" " if loop.last else ","} // MIO Pad ${pad["idx"]}
+% endfor
+);
+
+ import top_${top["name"]}_pkg::*;
+ import prim_pad_wrapper_pkg::*;
+
+% if target["pinmux"]["special_signals"]:
+ ////////////////////////////
+ // Special Signal Indices //
+ ////////////////////////////
+
+ % for entry in target["pinmux"]["special_signals"]:
+<% param_name = (lib.Name.from_snake_case(entry["name"]) +
+ lib.Name(["pad", "idx"])).as_camel_case()
+%>\
+ parameter int ${param_name} = ${entry["idx"]};
+ % endfor
+% endif
+
+ // TODO: this is temporary and will be removed in the future.
+ // This specifies the tie-off values of the muxed MIO/DIOs
+ // when the JTAG is active. SPI CSB is active low.
+ localparam logic [pinmux_pkg::NumIOs-1:0] TieOffValues = pinmux_pkg::NumIOs'(1'b1 << (
+ pinmux_reg_pkg::NMioPads + DioSpiDeviceCsb));
+
+ // DFT and Debug signal positions in the pinout.
+ localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
+ const_sampling: 1'b1,
+ tie_offs: TieOffValues, // TODO: can we remove this and just set it to zero?
+ tck_idx: TckPadIdx,
+ tms_idx: TmsPadIdx,
+ trst_idx: TrstNPadIdx,
+ tdi_idx: TdiPadIdx,
+ tdo_idx: TdoPadIdx,
+ tap_strap0_idx: Tap0PadIdx,
+ tap_strap1_idx: Tap1PadIdx,
+ dft_strap0_idx: Dft0PadIdx,
+ dft_strap1_idx: Dft1PadIdx,
+ // TODO: check whether there is a better way to pass these USB-specific params
+ usb_dp_idx: DioUsbdevDp,
+ usb_dn_idx: DioUsbdevDn,
+ usb_dp_pullup_idx: DioUsbdevDpPullup,
+ usb_dn_pullup_idx: DioUsbdevDnPullup
+ };
+
+ ////////////////////////
+ // Signal definitions //
+ ////////////////////////
+
+ pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
+ pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
+ logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
+
+ // Manual pads
+% for pad in dedicated_pads:
+<%
+ pad_prefix = pad["name"].lower()
+%>\
+% if not get_dio_sig(pinmux, pad):
+ logic manual_in_${pad_prefix}, manual_out_${pad_prefix}, manual_oe_${pad_prefix};
+% endif
+% endfor
+
+% for pad in dedicated_pads:
+<%
+ pad_prefix = pad["name"].lower()
+%>\
+% if not get_dio_sig(pinmux, pad):
+ pad_attr_t manual_attr_${pad_prefix};
+% endif
+% endfor
+
+% if target["pinout"]["remove_pads"]:
+ /////////////////////////
+ // Stubbed pad tie-off //
+ /////////////////////////
+
+ // Only signals going to non-custom pads need to be tied off.
+ logic [${len(pinout["pads"])-1}:0] unused_sig;
+% for pad in pinout["pads"]:
+ % if pad["connection"] == 'muxed':
+ % if pad["name"] in target["pinout"]["remove_pads"]:
+ assign mio_in[${pad["idx"]}] = 1'b0;
+ assign unused_sig[${loop.index}] = mio_out[${pad["idx"]}] ^ mio_oe[${pad["idx"]}];
+ % endif
+ % else:
+ % if pad["name"] in target["pinout"]["remove_pads"]:
+<%
+ ## Only need to tie off if this is not a custom pad.
+ sig = get_dio_sig(pinmux, pad)
+ if sig is not None:
+ sig_index = lib.get_io_enum_literal(sig, 'dio')
+%>\
+ % if sig is not None:
+ assign dio_in[${lib.get_io_enum_literal(sig, 'dio')}] = 1'b0;
+ assign unused_sig[${loop.index}] = dio_out[${sig_index}] ^ dio_oe[${sig_index}];
+ % endif
+ % endif
+ % endif
+% endfor
+%endif
+
+ //////////////////////
+ // Padring Instance //
+ //////////////////////
+
+% if target["name"] == "asic":
+ // AST signals needed in padring
+ ast_pkg::ast_clks_t ast_base_clks;
+ logic scan_rst_n;
+ lc_ctrl_pkg::lc_tx_t scanmode;
+% endif
+
+ padring #(
+ // Padring specific counts may differ from pinmux config due
+ // to custom, stubbed or added pads.
+ .NDioPads(${len(dedicated_pads)}),
+ .NMioPads(${len(muxed_pads)}),
+% if target["name"] == "asic":
+ // TODO: need to add ScanRole parameters
+ .PhysicalPads(1),
+ .NIoBanks(IoBankCount),
+ .DioPadBank ({
+% for pad in list(reversed(dedicated_pads)):
+ ${lib.Name(['io', 'bank', pad["bank"]]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+ }),
+ .MioPadBank ({
+% for pad in list(reversed(muxed_pads)):
+ ${lib.Name(['io', 'bank', pad["bank"]]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+ }),
+% endif
+\
+\
+ .DioPadType ({
+% for pad in list(reversed(dedicated_pads)):
+ ${pad["type"]}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+ }),
+ .MioPadType ({
+% for pad in list(reversed(muxed_pads)):
+ ${pad["type"]}${" " if loop.last else ","} // ${pad['name']}
+% endfor
+ })
+ ) u_padring (
+ // This is only used for scan and DFT purposes
+% if target["name"] == "asic":
+ .clk_scan_i ( ast_base_clks.clk_sys ),
+ .scanmode_i ( scanmode ),
+% else:
+ .clk_scan_i ( 1'b0 ),
+ .scanmode_i ( lc_ctrl_pkg::Off ),
+ % endif
+ // TODO: wire this up to AST. Hint: the top_<name>_pkg contains
+ // generated parameters that can be used to index pads by name.
+ .dio_in_raw_o ( ),
+ .mio_in_raw_o ( ),
+ // Chip IOs
+ .dio_pad_io ({
+% for pad in list(reversed(dedicated_pads)):
+ ${pad["name"]}${"" if loop.last else ","}
+% endfor
+ }),
+
+ .mio_pad_io ({
+% for pad in list(reversed(muxed_pads)):
+ ${pad["name"]}${"" if loop.last else ","}
+% endfor
+ }),
+
+ // Core-facing
+% for port in ["in_o", "out_i", "oe_i", "attr_i"]:
+ .dio_${port} ({
+ % for pad in list(reversed(dedicated_pads)):
+ <%
+ sig = get_dio_sig(pinmux, pad)
+ %>\
+ % if sig is None:
+ manual_${port[:-2]}_${pad["name"].lower()}${"" if loop.last else ","}
+ % else:
+ dio_${port[:-2]}[${lib.get_io_enum_literal(sig, 'dio')}]${"" if loop.last else ","}
+ % endif
+ % endfor
+ }),
+% endfor
+
+% for port in ["in_o", "out_i", "oe_i", "attr_i"]:
+ .mio_${port} ({
+ % for pad in list(reversed(muxed_pads)):
+ mio_${port[:-2]}[${pad["idx"]}]${"" if loop.last else ","}
+ % endfor
+ })${"" if loop.last else ","}
+% endfor
+ );
+
+
+###################################################################
+## USB for CW305 ##
+###################################################################
+% if target["name"] == "cw305":
+ // Connect the DP pad
+ assign dio_in[DioUsbdevDp] = manual_in_usb_p;
+ assign manual_out_usb_p = dio_out[DioUsbdevDp];
+ assign manual_oe_usb_p = dio_oe[DioUsbdevDp];
+ assign manual_attr_usb_p = dio_attr[DioUsbdevDp];
+
+ // Connect the DN pad
+ assign dio_in[DioUsbdevDn] = manual_in_usb_n;
+ assign manual_out_usb_n = dio_out[DioUsbdevDn];
+ assign manual_oe_usb_n = dio_oe[DioUsbdevDn];
+ assign manual_attr_usb_n = dio_attr[DioUsbdevDn];
+
+ // Connect sense pad
+ assign dio_in[DioUsbdevSense] = manual_in_io_usb_sense0;
+ assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense];
+ assign manual_oe_io_usb_sense0 = dio_oe[DioUsbdevSense];
+ assign manual_attr_io_sense0 = dio_attr[DioUsbdevSense];
+
+ // Connect DN pullup
+ assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0;
+ assign manual_out_io_usb_dnpullup0 = dio_out[DioUsbdevDnPullup];
+ assign manual_oe_io_usb_dnpullup0 = dio_oe[DioUsbdevDnPullup];
+ assign manual_attr_io_dnpullup0 = dio_attr[DioUsbdevDnPullup];
+
+ // Connect DP pullup
+ assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0;
+ assign manual_out_io_usb_dppullup0 = dio_out[DioUsbdevDpPullup];
+ assign manual_oe_io_usb_dppullup0 = dio_oe[DioUsbdevDpPullup];
+ assign manual_attr_io_dppullup0 = dio_attr[DioUsbdevDpPullup];
+
+ // Tie-off unused signals
+ assign dio_in[DioUsbdevSe0] = 1'b0;
+ assign dio_in[DioUsbdevTxModeSe] = 1'b0;
+ assign dio_in[DioUsbdevSuspend] = 1'b0;
+
+ logic unused_usb_sigs;
+ assign unused_usb_sigs = ^{
+ // SE0
+ dio_out[DioUsbdevSe0],
+ dio_oe[DioUsbdevSe0],
+ dio_attr[DioUsbdevSe0],
+ // TX Mode
+ dio_out[DioUsbdevTxModeSe],
+ dio_oe[DioUsbdevTxModeSe],
+ dio_attr[DioUsbdevTxModeSe],
+ // Suspend
+ dio_out[DioUsbdevSuspend],
+ dio_oe[DioUsbdevSuspend],
+ dio_attr[DioUsbdevSuspend],
+ // D is used as an input only
+ dio_out[DioUsbdevD],
+ dio_oe[DioUsbdevD],
+ dio_attr[DioUsbdevD]
+ };
+
+% endif
+
+###################################################################
+## USB for Nexysvideo ##
+###################################################################
+% if target["name"] == "nexysvideo":
+
+ /////////////////////
+ // USB Overlay Mux //
+ /////////////////////
+
+ // TODO: generalize this USB mux code and align with other tops.
+
+ // Software can enable the pinflip feature inside usbdev.
+ // The example hello_usbdev does this based on GPIO0 (a switch on the board)
+ //
+ // Here, we use the state of the DN pullup to effectively undo the
+ // swapping such that the PCB always sees the unflipped D+/D-. We
+ // could do the same inside the .xdc file but then two FPGA
+ // bitstreams would be needed for testing.
+ //
+ // dio_in/out/oe map is: PADS <- _padring <- JTAG mux -> _umux -> USB mux -> _core
+
+ // Split out for differential PHY testing
+
+ // Outputs always drive and just copy the value
+ // Let them go to the normal place too because it won't do any harm
+ // and it simplifies the changes needed
+
+ // The output enable for IO_USB_DNPULLUP0 is used to decide whether we need to undo the swapping.
+ logic undo_swap;
+ assign undo_swap = dio_oe[DioUsbdevDnPullup];
+
+ // GPIO[2] = Switch 2 on board is used to select using the UPHY
+ // Keep GPIO[1] for selecting differential in sw
+ logic use_uphy;
+ assign use_uphy = mio_in[MioPadIoa2];
+
+ // DioUsbdevDn
+ assign manual_attr_usb_n = '0;
+ assign manual_attr_io_uphy_dn_tx = '0;
+
+ assign manual_out_io_uphy_dn_tx = manual_out_usb_n;
+ assign manual_out_usb_n = undo_swap ? dio_out[DioUsbdevDp] :
+ dio_out[DioUsbdevDn];
+
+ assign manual_oe_io_uphy_dn_tx = manual_oe_usb_n;
+ assign manual_oe_usb_n = undo_swap ? dio_oe[DioUsbdevDp] :
+ dio_oe[DioUsbdevDn];
+
+ assign dio_in[DioUsbdevDn] = use_uphy ?
+ (undo_swap ? manual_in_io_uphy_dp_rx :
+ manual_in_io_uphy_dn_rx) :
+ (undo_swap ? manual_in_usb_p :
+ manual_in_usb_n);
+ // DioUsbdevDp
+ assign manual_attr_usb_p = '0;
+ assign manual_attr_io_uphy_dp_tx = '0;
+
+ assign manual_out_io_uphy_dp_tx = manual_out_usb_p;
+ assign manual_out_usb_p = undo_swap ? dio_out[DioUsbdevDn] :
+ dio_out[DioUsbdevDp];
+
+ assign manual_oe_io_uphy_dp_tx = manual_oe_usb_p;
+ assign manual_oe_usb_p = undo_swap ? dio_oe[DioUsbdevDn] :
+ dio_oe[DioUsbdevDp];
+ assign dio_in[DioUsbdevDp] = use_uphy ?
+ (undo_swap ? manual_in_io_uphy_dn_rx :
+ manual_in_io_uphy_dp_rx) :
+ (undo_swap ? manual_in_usb_n :
+ manual_in_usb_p);
+ // DioUsbdevD
+ // This is not connected at the moment
+ logic unused_out_usb_d;
+ assign unused_out_usb_d = dio_out[DioUsbdevD] ^
+ dio_oe[DioUsbdevD];
+ assign dio_in[DioUsbdevD] = use_uphy ?
+ (undo_swap ? ~manual_in_io_uphy_d_rx :
+ manual_in_io_uphy_d_rx) :
+ // This is not connected at the moment
+ (undo_swap ? 1'b1 : 1'b0);
+ assign manual_out_io_uphy_d_rx = 1'b0;
+ assign manual_oe_io_uphy_d_rx = 1'b0;
+
+ // DioUsbdevDnPullup
+ assign manual_attr_io_usb_dnpullup0 = '0;
+ assign manual_out_io_usb_dnpullup0 = undo_swap ? dio_out[DioUsbdevDpPullup] :
+ dio_out[DioUsbdevDnPullup];
+ assign manual_oe_io_usb_dnpullup0 = undo_swap ? dio_oe[DioUsbdevDpPullup] :
+ dio_oe[DioUsbdevDnPullup];
+ assign dio_in[DioUsbdevDnPullup] = manual_in_io_usb_dnpullup0;
+
+ // DioUsbdevDpPullup
+ assign manual_attr_io_usb_dppullup0 = '0;
+ assign manual_out_io_usb_dppullup0 = undo_swap ? dio_out[DioUsbdevDnPullup] :
+ dio_out[DioUsbdevDpPullup];
+ assign manual_oe_io_usb_dppullup0 = undo_swap ? dio_oe[DioUsbdevDnPullup] :
+ dio_oe[DioUsbdevDpPullup];
+ assign dio_in[DioUsbdevDpPullup] = manual_in_io_usb_dppullup0;
+
+ // DioUsbdevSense
+ assign manual_out_io_usb_sense0 = dio_out[DioUsbdevSense];
+ assign manual_oe_io_usb_sense0 = dio_oe[DioUsbdevSense];
+ assign dio_in[DioUsbdevSense] = use_uphy ? manual_in_io_uphy_sense :
+ manual_in_io_usb_sense0;
+ assign manual_out_io_uphy_sense = 1'b0;
+ assign manual_oe_io_uphy_sense = 1'b0;
+
+ // Additional outputs for uphy
+ assign manual_oe_io_uphy_dppullup = 1'b1;
+ assign manual_out_io_uphy_dppullup = manual_out_io_usb_dppullup0 &
+ manual_oe_io_usb_dppullup0;
+
+ logic unused_in_io_uphy_dppullup;
+ assign unused_in_io_uphy_dppullup = manual_in_io_uphy_dppullup;
+
+ assign manual_oe_io_uphy_oe_n = 1'b1;
+ assign manual_out_io_uphy_oe_n = ~manual_oe_usb_p;
+
+ logic unused_in_io_uphy_oe_n;
+ assign unused_in_io_uphy_oe_n = manual_in_io_uphy_oe_n;
+
+% endif
+
+###################################################################
+## ASIC ##
+###################################################################
+% if target["name"] == "asic":
+
+ //////////////////////////////////
+ // Manual Pad / Signal Tie-offs //
+ //////////////////////////////////
+
+ assign manual_out_por_n = 1'b0;
+ assign manual_oe_por_n = 1'b0;
+
+ assign manual_out_flash_test_mode0 = 1'b0;
+ assign manual_oe_flash_test_mode0 = 1'b0;
+ assign manual_out_flash_test_mode1 = 1'b0;
+ assign manual_oe_flash_test_mode1 = 1'b0;
+ assign manual_out_flash_test_mode2 = 1'b0;
+ assign manual_oe_flash_test_mode2 = 1'b0;
+ assign manual_out_flash_test_mode3 = 1'b0;
+ assign manual_oe_flash_test_mode3 = 1'b0;
+
+ assign manual_out_cc1 = 1'b0;
+ assign manual_oe_cc1 = 1'b0;
+ assign manual_out_cc2 = 1'b0;
+ assign manual_oe_cc2 = 1'b0;
+
+ assign manual_out_flash_test_volt = 1'b0;
+ assign manual_oe_flash_test_volt = 1'b0;
+
+ // These pad attributes currently tied off permanently (these are all input-only pads).
+ assign manual_attr_por_n = '0;
+ assign manual_attr_cc1 = '0;
+ assign manual_attr_cc2 = '0;
+ assign manual_attr_flash_test_mode0 = '0;
+ assign manual_attr_flash_test_mode1 = '0;
+ assign manual_attr_flash_test_mode2 = '0;
+ assign manual_attr_flash_test_mode3 = '0;
+ assign manual_attr_flash_test_volt = '0;
+
+ logic unused_manual_sigs;
+ assign unused_manual_sigs = ^{
+ manual_in_cc2,
+ manual_in_cc1,
+ manual_in_flash_test_mode3,
+ manual_in_flash_test_mode2,
+ manual_in_flash_test_mode1,
+ manual_in_flash_test_mode0,
+ manual_in_flash_test_volt
+ };
+
+ ///////////////////////////////
+ // Differential USB Receiver //
+ ///////////////////////////////
+
+ // TODO: generalize this USB mux code and align with other tops.
+
+ // Connect the DP pad
+ assign dio_in[DioUsbdevDp] = manual_in_usb_p;
+ assign manual_out_usb_p = dio_out[DioUsbdevDp];
+ assign manual_oe_usb_p = dio_oe[DioUsbdevDp];
+ assign manual_attr_usb_p = dio_attr[DioUsbdevDp];
+
+ // Connect the DN pad
+ assign dio_in[DioUsbdevDn] = manual_in_usb_n;
+ assign manual_out_usb_n = dio_out[DioUsbdevDn];
+ assign manual_oe_usb_n = dio_oe[DioUsbdevDn];
+ assign manual_attr_usb_n = dio_attr[DioUsbdevDn];
+
+ // Pullups
+ logic usb_pullup_p_en, usb_pullup_n_en;
+ assign usb_pullup_p_en = dio_out[DioUsbdevDpPullup] & dio_oe[DioUsbdevDpPullup];
+ assign usb_pullup_n_en = dio_out[DioUsbdevDnPullup] & dio_oe[DioUsbdevDnPullup];
+
+ // TODO(#5925): connect this to AST?
+ logic usbdev_aon_usb_rx_enable;
+ logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
+ assign usbdev_aon_usb_rx_enable = 1'b0;
+
+ prim_usb_diff_rx #(
+ .CalibW(ast_pkg::UsbCalibWidth)
+ ) u_prim_usb_diff_rx (
+ .input_pi ( USB_P ),
+ .input_ni ( USB_N ),
+ .input_en_i ( usbdev_aon_usb_rx_enable ),
+ .core_pok_i ( ast_base_pwr.main_pok ),
+ .pullup_p_en_i ( usb_pullup_p_en ),
+ .pullup_n_en_i ( usb_pullup_n_en ),
+ .calibration_i ( usb_io_pu_cal ),
+ .input_o ( dio_in[DioUsbdevD] )
+ );
+
+ // Tie-off unused signals
+ assign dio_in[DioUsbdevSense] = 1'b0;
+ assign dio_in[DioUsbdevSe0] = 1'b0;
+ assign dio_in[DioUsbdevTxModeSe] = 1'b0;
+ assign dio_in[DioUsbdevSuspend] = 1'b0;
+
+ logic unused_usb_sigs;
+ assign unused_usb_sigs = ^{
+ // Sense
+ dio_out[DioUsbdevSense],
+ dio_oe[DioUsbdevSense],
+ dio_attr[DioUsbdevSense],
+ // SE0
+ dio_out[DioUsbdevSe0],
+ dio_oe[DioUsbdevSe0],
+ dio_attr[DioUsbdevSe0],
+ // TX Mode
+ dio_out[DioUsbdevTxModeSe],
+ dio_oe[DioUsbdevTxModeSe],
+ dio_attr[DioUsbdevTxModeSe],
+ // Suspend
+ dio_out[DioUsbdevSuspend],
+ dio_oe[DioUsbdevSuspend],
+ dio_attr[DioUsbdevSuspend],
+ // D is used as an input only
+ dio_out[DioUsbdevD],
+ dio_oe[DioUsbdevD],
+ dio_attr[DioUsbdevD]
+ };
+
+ //////////////////////
+ // AST //
+ //////////////////////
+ // TLUL interface
+ tlul_pkg::tl_h2d_t base_ast_bus;
+ tlul_pkg::tl_d2h_t ast_base_bus;
+
+ // assorted ast status
+ ast_pkg::ast_status_t ast_status;
+
+ // ast clocks and resets
+ logic aon_pok;
+
+ // pwrmgr interface
+ pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+
+ // synchronization clocks / rests
+ clkmgr_pkg::clkmgr_ast_out_t clks_ast;
+ rstmgr_pkg::rstmgr_ast_out_t rsts_ast;
+
+ // otp power sequence
+ otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
+ otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
+
+ logic usb_ref_pulse;
+ logic usb_ref_val;
+
+ // adc
+ // The adc package definition should eventually be moved to the adc module
+ ast_pkg::adc_ast_req_t adc_i;
+ ast_pkg::adc_ast_rsp_t adc_o;
+
+ // entropy source interface
+ // The entropy source pacakge definition should eventually be moved to es
+ entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
+ entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
+ logic es_rng_fips;
+
+ // entropy distribution network
+ edn_pkg::edn_req_t ast_edn_edn_req;
+ edn_pkg::edn_rsp_t ast_edn_edn_rsp;
+
+ // alerts interface
+ ast_pkg::ast_alert_rsp_t ast_alert_rsp;
+ ast_pkg::ast_alert_req_t ast_alert_req;
+
+ // Flash connections
+ lc_ctrl_pkg::lc_tx_t flash_bist_enable;
+ logic flash_power_down_h;
+ logic flash_power_ready_h;
+
+ // Life cycle clock bypass req/ack
+ lc_ctrl_pkg::lc_tx_t ast_clk_byp_req;
+ lc_ctrl_pkg::lc_tx_t ast_clk_byp_ack;
+
+ // DFT connections
+ logic scan_en;
+ lc_ctrl_pkg::lc_tx_t dft_en;
+ pinmux_pkg::dft_strap_test_req_t dft_strap_test;
+
+ // Debug connections
+ logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
+ logic [ast_pkg::Pad2AstInWidth-1:0] pinmux2ast;
+
+ // Jitter enable
+ logic jen;
+
+ // Alert connections
+ import sensor_ctrl_reg_pkg::AsSel;
+ import sensor_ctrl_reg_pkg::CgSel;
+ import sensor_ctrl_reg_pkg::GdSel;
+ import sensor_ctrl_reg_pkg::TsHiSel;
+ import sensor_ctrl_reg_pkg::TsLoSel;
+ import sensor_ctrl_reg_pkg::LsSel;
+ import sensor_ctrl_reg_pkg::OtSel;
+
+ // reset domain connections
+ import rstmgr_pkg::PowerDomains;
+ import rstmgr_pkg::DomainAonSel;
+ import rstmgr_pkg::Domain0Sel;
+
+ // adc connections
+ ast_pkg::adc_ast_req_t adc_req;
+ ast_pkg::adc_ast_rsp_t adc_rsp;
+
+ // TODO: need to mux the external clock.
+ logic ext_clk;
+ assign ext_clk = 1'b0;
+
+ // Memory configuration connections
+ ast_pkg::spm_rm_t ast_ram_1p_cfg;
+ ast_pkg::spm_rm_t ast_rf_cfg;
+ ast_pkg::spm_rm_t ast_rom_cfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
+ ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
+
+ prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
+ prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
+ prim_rom_pkg::rom_cfg_t rom_cfg;
+
+ // conversion from ast structure to memory centric structures
+ assign ram_1p_cfg = '{
+ ram_cfg: '{
+ cfg_en: ast_ram_1p_cfg.marg_en,
+ cfg: ast_ram_1p_cfg.marg
+ },
+ rf_cfg: '{
+ cfg_en: ast_rf_cfg.marg_en,
+ cfg: ast_rf_cfg.marg
+ }
+ };
+
+ assign ram_2p_cfg = '{
+ a_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_a,
+ cfg: ast_ram_2p_fcfg.marg_a
+ },
+ a_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_a,
+ cfg: ast_ram_2p_lcfg.marg_a
+ },
+ b_ram_fcfg: '{
+ cfg_en: ast_ram_2p_fcfg.marg_en_b,
+ cfg: ast_ram_2p_fcfg.marg_b
+ },
+ b_ram_lcfg: '{
+ cfg_en: ast_ram_2p_lcfg.marg_en_b,
+ cfg: ast_ram_2p_lcfg.marg_b
+ }
+ };
+
+ assign rom_cfg = '{
+ cfg_en: ast_rom_cfg.marg_en,
+ cfg: ast_rom_cfg.marg
+ };
+
+
+ // AST does not use all clocks / resets forwarded to it
+ logic unused_slow_clk_en;
+ logic unused_usb_clk_aon;
+ logic unused_usb_clk_io_div4;
+ assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
+ assign unused_usb_clk_aon = clks_ast.clk_ast_usbdev_aon_peri;
+ assign unused_usb_clk_io_div4 = clks_ast.clk_ast_usbdev_io_div4_peri;
+
+ logic unused_usb_usb_rst;
+ logic [PowerDomains-1:0] unused_usb_sys_io_div4_rst;
+ logic [PowerDomains-1:0] unused_usb_sys_aon_rst;
+ logic unused_ast_sys_io_div4_rst;
+ logic unused_sensor_ctrl_sys_io_div4_rst;
+ logic unused_adc_ctrl_sys_io_div4_rst;
+ logic unused_entropy_sys_rst;
+ logic unused_edn_sys_rst;
+ assign unused_usb_usb_rst = rsts_ast.rst_ast_usbdev_usb_n[DomainAonSel];
+ assign unused_usb_sys_io_div4_rst = rsts_ast.rst_ast_usbdev_sys_io_div4_n;
+ assign unused_usb_sys_aon_rst = rsts_ast.rst_ast_usbdev_sys_aon_n;
+ assign unused_ast_sys_io_div4_rst =
+ rsts_ast.rst_ast_ast_sys_io_div4_n[Domain0Sel];
+ assign unused_sensor_ctrl_sys_io_div4_rst =
+ rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[Domain0Sel];
+ assign unused_adc_ctrl_sys_io_div4_rst =
+ rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[Domain0Sel];
+ assign unused_entropy_sys_rst = rsts_ast.rst_ast_entropy_src_sys_n[DomainAonSel];
+ assign unused_edn_sys_rst = rsts_ast.rst_ast_edn0_sys_n[DomainAonSel];
+
+
+ ast #(
+ .EntropyStreams(top_pkg::ENTROPY_STREAM),
+ .AdcChannels(top_pkg::ADC_CHANNELS),
+ .AdcDataWidth(top_pkg::ADC_DATAW),
+ .UsbCalibWidth(ast_pkg::UsbCalibWidth),
+ .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
+ .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
+ ) u_ast (
+ // tlul
+ .tl_i ( base_ast_bus ),
+ .tl_o ( ast_base_bus ),
+ // buffered clocks & resets
+ // Reset domain connection is manual at the moment
+ .clk_ast_adc_i ( clks_ast.clk_ast_adc_ctrl_aon_io_div4_peri ),
+ .rst_ast_adc_ni ( rsts_ast.rst_ast_adc_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_alert_i ( clks_ast.clk_ast_sensor_ctrl_aon_io_div4_secure ),
+ .rst_ast_alert_ni ( rsts_ast.rst_ast_sensor_ctrl_aon_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_es_i ( clks_ast.clk_ast_edn0_main_secure ),
+ .rst_ast_es_ni ( rsts_ast.rst_ast_edn0_sys_n[Domain0Sel] ),
+ .clk_ast_rng_i ( clks_ast.clk_ast_entropy_src_main_secure ),
+ .rst_ast_rng_ni ( rsts_ast.rst_ast_entropy_src_sys_n[Domain0Sel] ),
+ .clk_ast_tlul_i ( clks_ast.clk_ast_ast_io_div4_secure ),
+ .rst_ast_tlul_ni ( rsts_ast.rst_ast_ast_sys_io_div4_n[DomainAonSel] ),
+ .clk_ast_usb_i ( clks_ast.clk_ast_usbdev_usb_peri ),
+ .rst_ast_usb_ni ( rsts_ast.rst_ast_usbdev_usb_n[Domain0Sel] ),
+ .clk_ast_ext_i ( ext_clk ),
+ .por_ni ( manual_in_por_n ),
+ // pok test for FPGA
+ .vcc_supp_i ( 1'b1 ),
+ .vcaon_supp_i ( 1'b1 ),
+ .vcmain_supp_i ( 1'b1 ),
+ .vioa_supp_i ( 1'b1 ),
+ .viob_supp_i ( 1'b1 ),
+ // pok
+ .vcaon_pok_o ( aon_pok ),
+ .vcmain_pok_o ( ast_base_pwr.main_pok ),
+ .vioa_pok_o ( ast_status.io_pok[0] ),
+ .viob_pok_o ( ast_status.io_pok[1] ),
+ // main regulator
+ .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
+ .main_pd_ni ( base_ast_pwr.main_pd_n ),
+ // pdm control (flash)/otp
+ .flash_power_down_h_o ( flash_power_down_h ),
+ .flash_power_ready_h_o ( flash_power_ready_h ),
+ .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
+ // system source clock
+ .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
+ // need to add function in clkmgr
+ .clk_src_sys_jen_i ( jen ),
+ .clk_src_sys_o ( ast_base_clks.clk_sys ),
+ .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
+ // aon source clock
+ .clk_src_aon_o ( ast_base_clks.clk_aon ),
+ .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
+ // io source clock
+ .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
+ .clk_src_io_o ( ast_base_clks.clk_io ),
+ .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
+ // usb source clock
+ .usb_ref_pulse_i ( usb_ref_pulse ),
+ .usb_ref_val_i ( usb_ref_val ),
+ .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
+ .clk_src_usb_o ( ast_base_clks.clk_usb ),
+ .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
+ // USB IO Pull-up Calibration Setting
+ .usb_io_pu_cal_o ( usb_io_pu_cal ),
+ // adc
+ .adc_a0_ai ( CC1 ),
+ .adc_a1_ai ( CC2 ),
+ .adc_pd_i ( adc_req.pd ),
+ .adc_chnsel_i ( adc_req.channel_sel ),
+ .adc_d_o ( adc_rsp.data ),
+ .adc_d_val_o ( adc_rsp.data_valid ),
+ // rng
+ .rng_en_i ( es_rng_req.rng_enable ),
+ .rng_fips_i ( es_rng_fips ),
+ .rng_val_o ( es_rng_rsp.rng_valid ),
+ .rng_b_o ( es_rng_rsp.rng_b ),
+ // entropy
+ .entropy_rsp_i ( ast_edn_edn_rsp ),
+ .entropy_req_o ( ast_edn_edn_req ),
+ // alerts
+ .as_alert_trig_i ( ast_alert_rsp.alerts_trig[AsSel] ),
+ .as_alert_ack_i ( ast_alert_rsp.alerts_ack[AsSel] ),
+ .as_alert_o ( ast_alert_req.alerts[AsSel] ),
+ .cg_alert_trig_i ( ast_alert_rsp.alerts_trig[CgSel] ),
+ .cg_alert_ack_i ( ast_alert_rsp.alerts_ack[CgSel] ),
+ .cg_alert_o ( ast_alert_req.alerts[CgSel] ),
+ .gd_alert_trig_i ( ast_alert_rsp.alerts_trig[GdSel] ),
+ .gd_alert_ack_i ( ast_alert_rsp.alerts_ack[GdSel] ),
+ .gd_alert_o ( ast_alert_req.alerts[GdSel] ),
+ .ts_alert_hi_trig_i ( ast_alert_rsp.alerts_trig[TsHiSel] ),
+ .ts_alert_hi_ack_i ( ast_alert_rsp.alerts_ack[TsHiSel] ),
+ .ts_alert_hi_o ( ast_alert_req.alerts[TsHiSel] ),
+ .ts_alert_lo_trig_i ( ast_alert_rsp.alerts_trig[TsLoSel] ),
+ .ts_alert_lo_ack_i ( ast_alert_rsp.alerts_ack[TsLoSel] ),
+ .ts_alert_lo_o ( ast_alert_req.alerts[TsLoSel] ),
+ .ls_alert_trig_i ( ast_alert_rsp.alerts_trig[LsSel] ),
+ .ls_alert_ack_i ( ast_alert_rsp.alerts_ack[LsSel] ),
+ .ls_alert_o ( ast_alert_req.alerts[LsSel] ),
+ .ot_alert_trig_i ( ast_alert_rsp.alerts_trig[OtSel] ),
+ .ot_alert_ack_i ( ast_alert_rsp.alerts_ack[OtSel] ),
+ .ot_alert_o ( ast_alert_req.alerts[OtSel] ),
+ // dft
+ .dft_strap_test_i ( dft_strap_test ),
+ .lc_dft_en_i ( dft_en ),
+ // pinmux related
+ .padmux2ast_i ( pinmux2ast ),
+ .ast2padmux_o ( ast2pinmux ),
+ // Direct short to PAD
+ .pad2ast_t0_ai ( IOA4 ),
+ .pad2ast_t1_ai ( IOA5 ),
+ .ast2pad_t0_ao ( IOA2 ),
+ .ast2pad_t1_ao ( IOA3 ),
+ .lc_clk_byp_req_i ( ast_clk_byp_req ),
+ .lc_clk_byp_ack_o ( ast_clk_byp_ack ),
+ .flash_bist_en_o ( flash_bist_enable ),
+ // Memory configuration connections
+ .dpram_rmf_o ( ast_ram_2p_fcfg ),
+ .dpram_rml_o ( ast_ram_2p_lcfg ),
+ .spram_rm_o ( ast_ram_1p_cfg ),
+ .sprgf_rm_o ( ast_rf_cfg ),
+ .sprom_rm_o ( ast_rom_cfg ),
+ // scan
+ .dft_scan_md_o ( scanmode ),
+ .scan_shift_en_o ( scan_en ),
+ .scan_reset_no ( scan_rst_n )
+ );
+
+ //////////////////////
+ // Top-level design //
+ //////////////////////
+
+ top_${top["name"]} #(
+ .AesMasking(1'b1),
+ .AesSBoxImpl(aes_pkg::SBoxImplDom),
+ .SecAesStartTriggerDelay(0),
+ .SecAesAllowForcingMasks(1'b0),
+ .KmacEnMasking(1), // DOM AND + Masking scheme
+ .KmacReuseShare(0),
+ .SramCtrlRetAonInstrExec(0),
+ .SramCtrlMainInstrExec(1),
+ .PinmuxAonTargetCfg(PinmuxTargetCfg)
+ ) top_${top["name"]} (
+ .rst_ni ( aon_pok ),
+ // ast connections
+ .clk_main_i ( ast_base_clks.clk_sys ),
+ .clk_io_i ( ast_base_clks.clk_io ),
+ .clk_usb_i ( ast_base_clks.clk_usb ),
+ .clk_aon_i ( ast_base_clks.clk_aon ),
+ .clks_ast_o ( clks_ast ),
+ .clk_main_jitter_en_o ( jen ),
+ .rsts_ast_o ( rsts_ast ),
+ .pwrmgr_ast_req_o ( base_ast_pwr ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
+ .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
+ .sensor_ctrl_ast_status_i ( ast_status ),
+ .usbdev_usb_ref_val_o ( usb_ref_pulse ),
+ .usbdev_usb_ref_pulse_o ( usb_ref_val ),
+ .ast_tl_req_o ( base_ast_bus ),
+ .ast_tl_rsp_i ( ast_base_bus ),
+ .adc_req_o ( adc_req ),
+ .adc_rsp_i ( adc_rsp ),
+ .ast_edn_req_i ( ast_edn_edn_req ),
+ .ast_edn_rsp_o ( ast_edn_edn_rsp ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
+ .flash_bist_enable_i ( flash_bist_enable ),
+ .flash_power_down_h_i ( flash_power_down_h ),
+ .flash_power_ready_h_i ( flash_power_ready_h ),
+ .es_rng_req_o ( es_rng_req ),
+ .es_rng_rsp_i ( es_rng_rsp ),
+ .es_rng_fips_o ( es_rng_fips ),
+ .ast_clk_byp_req_o ( ast_clk_byp_req ),
+ .ast_clk_byp_ack_i ( ast_clk_byp_ack ),
+ .pinmux2ast_o ( pinmux2ast ),
+ .ast2pinmux_i ( ast2pinmux ),
+
+ // Flash test mode voltages
+ .flash_test_mode_a_io ( {FLASH_TEST_MODE3,
+ FLASH_TEST_MODE2,
+ FLASH_TEST_MODE1,
+ FLASH_TEST_MODE0} ),
+ .flash_test_voltage_h_io ( FLASH_TEST_VOLT ),
+
+ // Multiplexed I/O
+ .mio_in_i ( mio_in ),
+ .mio_out_o ( mio_out ),
+ .mio_oe_o ( mio_oe ),
+
+ // Dedicated I/O
+ .dio_in_i ( dio_in ),
+ .dio_out_o ( dio_out ),
+ .dio_oe_o ( dio_oe ),
+
+ // Pad attributes
+ .mio_attr_o ( mio_attr ),
+ .dio_attr_o ( dio_attr ),
+
+ // Memory attributes
+ .ram_1p_cfg_i ( ram_1p_cfg ),
+ .ram_2p_cfg_i ( ram_2p_cfg ),
+ .rom_cfg_i ( rom_cfg ),
+
+ // DFT signals
+ .ast_lc_dft_en_o ( dft_en ),
+ .dft_strap_test_o ( dft_strap_test ),
+ .scan_rst_ni ( scan_rst_n ),
+ .scan_en_i ( scan_en ),
+ .scanmode_i ( scanmode )
+ );
+% endif
+
+###################################################################
+## FPGA shared ##
+###################################################################
+% if target["name"] in ["cw305", "nexysvideo"]:
+ //////////////////
+ // PLL for FPGA //
+ //////////////////
+
+ assign manual_out_io_clk = 1'b0;
+ assign manual_oe_io_clk = 1'b0;
+ assign manual_out_por_n = 1'b0;
+ assign manual_oe_por_n = 1'b0;
+ assign manual_out_io_jsrst_n = 1'b0;
+ assign manual_oe_io_jsrst_n = 1'b0;
+
+ logic clk_main, clk_usb_48mhz, clk_aon, rst_n;
+ clkgen_xil7series # (
+ .AddClkBuf(0)
+ ) clkgen (
+ .clk_i(manual_in_io_clk),
+ .rst_ni(manual_in_por_n),
+ .jtag_srst_ni(manual_in_io_jsrst_n),
+ .clk_main_o(clk_main),
+ .clk_48MHz_o(clk_usb_48mhz),
+ .clk_aon_o(clk_aon),
+ .rst_no(rst_n)
+ );
+
+ //////////////////////
+ // Top-level design //
+ //////////////////////
+ pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
+ ast_pkg::ast_alert_req_t ast_base_alerts;
+ ast_pkg::ast_status_t ast_base_status;
+
+ assign ast_base_pwr.slow_clk_val = 1'b1;
+ assign ast_base_pwr.core_clk_val = 1'b1;
+ assign ast_base_pwr.io_clk_val = 1'b1;
+ assign ast_base_pwr.usb_clk_val = 1'b1;
+ assign ast_base_pwr.main_pok = 1'b1;
+
+ ast_pkg::ast_dif_t silent_alert = '{
+ p: 1'b0,
+ n: 1'b1
+ };
+
+ assign ast_base_alerts.alerts = {ast_pkg::NumAlerts{silent_alert}};
+ assign ast_base_status.io_pok = {ast_pkg::NumIoRails{1'b1}};
+
+ // the rst_ni pin only goes to AST
+ // the rest of the logic generates reset based on the 'pok' signal.
+ // for verilator purposes, make these two the same.
+ lc_ctrl_pkg::lc_tx_t lc_clk_bypass;
+
+% if target["name"] == "cw305":
+ // This is used for outputting the capture trigger
+ logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_pre;
+% endif
+
+// TODO: align this with ASIC version to minimize the duplication.
+// Also need to add AST simulation and FPGA emulation models for things like entropy source -
+// otherwise Verilator / FPGA will hang.
+ top_${top["name"]} #(
+% if target["name"] == "cw305":
+ .AesMasking(1'b1),
+ .AesSBoxImpl(aes_pkg::SBoxImplDom),
+ .SecAesStartTriggerDelay(40),
+ .SecAesAllowForcingMasks(1'b1),
+ .SecAesSkipPRNGReseeding(1'b1),
+ .IbexICache(0),
+ .BootRomInitFile(BootRomInitFile),
+% else:
+ .AesMasking(1'b0),
+ .AesSBoxImpl(aes_pkg::SBoxImplLut),
+ .SecAesStartTriggerDelay(0),
+ .SecAesAllowForcingMasks(1'b0),
+ .SecAesSkipPRNGReseeding(1'b0),
+ .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
+ .OtbnRegFile(otbn_pkg::RegFileFPGA),
+ .OtpCtrlMemInitFile(OtpCtrlMemInitFile),
+ .RomCtrlBootRomInitFile(BootRomInitFile),
+% endif
+ .IbexRegFile(ibex_pkg::RegFileFPGA),
+ .IbexPipeLine(1),
+ .SramCtrlRetAonInstrExec(0),
+ .SramCtrlMainInstrExec(1),
+ .PinmuxAonTargetCfg(PinmuxTargetCfg)
+ ) top_${top["name"]} (
+ .rst_ni ( rst_n ),
+ .clk_main_i ( clk_main ),
+ .clk_io_i ( clk_main ),
+ .clk_usb_i ( clk_usb_48mhz ),
+ .clk_aon_i ( clk_aon ),
+ .clks_ast_o ( ),
+ .clk_main_jitter_en_o ( ),
+ .rsts_ast_o ( ),
+ .pwrmgr_ast_req_o ( ),
+ .pwrmgr_ast_rsp_i ( ast_base_pwr ),
+ .sensor_ctrl_ast_alert_req_i ( ast_base_alerts ),
+ .sensor_ctrl_ast_alert_rsp_o ( ),
+ .sensor_ctrl_ast_status_i ( ast_base_status ),
+ .usbdev_usb_ref_val_o ( ),
+ .usbdev_usb_ref_pulse_o ( ),
+ .ast_edn_req_i ( '0 ),
+ .ast_edn_rsp_o ( ),
+ .flash_bist_enable_i ( lc_ctrl_pkg::Off ),
+ .flash_power_down_h_i ( 1'b0 ),
+ .flash_power_ready_h_i ( 1'b1 ),
+ .ast_clk_byp_req_o ( lc_clk_bypass ),
+ .ast_clk_byp_ack_i ( lc_clk_bypass ),
+
+% if target["name"] != "cw305":
+ .ast_tl_req_o ( ),
+ .ast_tl_rsp_i ( '0 ),
+ .otp_ctrl_otp_ast_pwr_seq_o ( ),
+ .otp_ctrl_otp_ast_pwr_seq_h_i ( '0 ),
+ .es_rng_req_o ( ),
+ .es_rng_rsp_i ( '0 ),
+ .es_rng_fips_o ( ),
+ .pinmux2ast_o ( ),
+ .ast2pinmux_i ( '0 ),
+% endif
+
+ // Multiplexed I/O
+ .mio_in_i ( mio_in ),
+% if target["name"] == "cw305":
+ .mio_out_o ( mio_out_pre ),
+% else:
+ .mio_out_o ( mio_out ),
+% endif
+ .mio_oe_o ( mio_oe ),
+
+ // Dedicated I/O
+ .dio_in_i ( dio_in ),
+ .dio_out_o ( dio_out ),
+ .dio_oe_o ( dio_oe ),
+
+ // Pad attributes
+ .mio_attr_o ( mio_attr ),
+ .dio_attr_o ( dio_attr ),
+
+ // Memory attributes
+ .ram_1p_cfg_i ( '0 ),
+ .ram_2p_cfg_i ( '0 ),
+ .rom_cfg_i ( '0 ),
+
+ // DFT signals
+ .scan_rst_ni ( 1'b1 ),
+ .scan_en_i ( 1'b0 ),
+ .scanmode_i ( lc_ctrl_pkg::Off )
+ );
+% endif
+
+
+###################################################################
+## CW305 capture trigger ##
+###################################################################
+% if target["name"] == "cw305":
+
+ //////////////////////////////////////
+ // Generate precise capture trigger //
+ //////////////////////////////////////
+
+ // TODO: make this a "manual" IO specific to the CW305 target
+ // such that we can decouple this from the MIO signals.
+ localparam int MioIdxTrigger = 15;
+
+ // To obtain a more precise capture trigger for side-channel analysis, we only forward the
+ // software-controlled capture trigger when the AES module is actually busy (performing
+ // either encryption/decryption or clearing internal registers).
+ // GPIO15 is used as capture trigger (mapped to IOB9 at the moment in pinmux.c).
+ always_comb begin : p_trigger
+ mio_out = mio_out_pre;
+ mio_out[MioIdxTrigger] = mio_out_pre[MioIdxTrigger] &
+ ~top_englishbreakfast.clkmgr_aon_idle[clkmgr_pkg::Aes];
+ end
+
+ //////////////////////
+ // ChipWhisperer IO //
+ //////////////////////
+
+ logic unused_inputs;
+ assign unused_inputs = manual_in_tio_clkout ^ manual_in_io_utx_debug;
+
+ // Clock ouput to capture board.
+ assign manual_out_tio_clkout = manual_in_io_clk;
+ assign manual_oe_tio_clkout = 1'b1;
+
+ // UART Tx for debugging. The UART itself is connected to the capture board.
+ assign manual_out_io_utx_debug = top_${top["name"]}.cio_uart0_tx_d2p;
+ assign manual_oe_io_utx_debug = 1'b1;
+
+% endif
+
+// TODO: change the naming to chip_
+endmodule : top_${top["name"]}_${target["name"]}
diff --git a/util/topgen/templates/toplevel.h.tpl b/util/topgen/templates/toplevel.h.tpl
index ad7f0bf..24ba410 100644
--- a/util/topgen/templates/toplevel.h.tpl
+++ b/util/topgen/templates/toplevel.h.tpl
@@ -134,10 +134,12 @@
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
-// PERIPH_INSEL ranges from 0 to NUM_MIO + 2 -1}
+// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
// 0 and 1 are tied to value 0 and 1
-#define NUM_MIO ${top["pinmux"]["num_mio"]}
-#define NUM_DIO ${sum([x["width"] if "width" in x else 1 for x in top["pinmux"]["dio"]])}
+#define NUM_MIO_PADS ${top["pinmux"]["io_counts"]["muxed"]["pads"]}
+#define NUM_DIO_PADS ${top["pinmux"]["io_counts"]["dedicated"]["inouts"] + \
+ top["pinmux"]["io_counts"]["dedicated"]["inputs"] + \
+ top["pinmux"]["io_counts"]["dedicated"]["outputs"] }
#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
diff --git a/util/topgen/templates/toplevel.sv.tpl b/util/topgen/templates/toplevel.sv.tpl
index 5786302..b76fc92 100644
--- a/util/topgen/templates/toplevel.sv.tpl
+++ b/util/topgen/templates/toplevel.sv.tpl
@@ -5,23 +5,24 @@
<%
import re
import topgen.lib as lib
-from topgen.c import Name
-num_mio_inputs = sum([x["width"] for x in top["pinmux"]["inputs"]])
-num_mio_outputs = sum([x["width"] for x in top["pinmux"]["outputs"]])
-num_mio = top["pinmux"]["num_mio"]
+num_mio_inputs = top['pinmux']['io_counts']['muxed']['inouts'] + \
+ top['pinmux']['io_counts']['muxed']['inputs']
+num_mio_outputs = top['pinmux']['io_counts']['muxed']['inouts'] + \
+ top['pinmux']['io_counts']['muxed']['outputs']
+num_mio_pads = top['pinmux']['io_counts']['muxed']['pads']
-num_dio_inputs = sum([x["width"] if x["type"] == "input" else 0 for x in top["pinmux"]["dio"]])
-num_dio_outputs = sum([x["width"] if x["type"] == "output" else 0 for x in top["pinmux"]["dio"]])
-num_dio_inouts = sum([x["width"] if x["type"] == "inout" else 0 for x in top["pinmux"]["dio"]])
-num_dio = sum([x["width"] if "width" in x else 1 for x in top["pinmux"]["dio"]])
+num_dio_inputs = top['pinmux']['io_counts']['dedicated']['inouts'] + \
+ top['pinmux']['io_counts']['dedicated']['inputs']
+num_dio_outputs = top['pinmux']['io_counts']['dedicated']['inouts'] + \
+ top['pinmux']['io_counts']['dedicated']['outputs']
+num_dio_total = top['pinmux']['io_counts']['dedicated']['inouts'] + \
+ top['pinmux']['io_counts']['dedicated']['inputs'] + \
+ top['pinmux']['io_counts']['dedicated']['outputs']
num_im = sum([x["width"] if "width" in x else 1 for x in top["inter_signal"]["external"]])
-max_miolength = max([len(x["name"]) for x in top["pinmux"]["inputs"] + top["pinmux"]["outputs"]])
-max_diolength = max([len(x["name"]) for x in top["pinmux"]["dio"]])
-
-max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["inputs"] + top["pinmux"]["outputs"]])
+max_sigwidth = max([x["width"] if "width" in x else 1 for x in top["pinmux"]["ios"]])
max_sigwidth = len("{}".format(max_sigwidth))
clks_attr = top['clocks']
@@ -62,25 +63,23 @@
// Reset, clocks defined as part of intermodule
input rst_ni,
-% if num_mio != 0:
+% if num_mio_pads != 0:
// Multiplexed I/O
- input ${lib.bitarray(num_mio, max_sigwidth)} mio_in_i,
- output logic ${lib.bitarray(num_mio, max_sigwidth)} mio_out_o,
- output logic ${lib.bitarray(num_mio, max_sigwidth)} mio_oe_o,
+ input ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_in_i,
+ output logic ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_out_o,
+ output logic ${lib.bitarray(num_mio_pads, max_sigwidth)} mio_oe_o,
% endif
-% if num_dio != 0:
+% if num_dio_total != 0:
// Dedicated I/O
- input ${lib.bitarray(num_dio, max_sigwidth)} dio_in_i,
- output logic ${lib.bitarray(num_dio, max_sigwidth)} dio_out_o,
- output logic ${lib.bitarray(num_dio, max_sigwidth)} dio_oe_o,
+ input ${lib.bitarray(num_dio_total, max_sigwidth)} dio_in_i,
+ output logic ${lib.bitarray(num_dio_total, max_sigwidth)} dio_out_o,
+ output logic ${lib.bitarray(num_dio_total, max_sigwidth)} dio_oe_o,
% endif
% if "pinmux" in top:
// pad attributes to padring
- output logic[pinmux_reg_pkg::NMioPads-1:0]
- [pinmux_reg_pkg::AttrDw-1:0] mio_attr_o,
- output logic[pinmux_reg_pkg::NDioPads-1:0]
- [pinmux_reg_pkg::AttrDw-1:0] dio_attr_o,
+ output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o,
+ output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o,
% endif
% if num_im != 0:
@@ -115,16 +114,17 @@
import tlul_pkg::*;
import top_pkg::*;
import tl_main_pkg::*;
+ import top_${top["name"]}_pkg::*;
// Compile-time random constants
import top_${top["name"]}_rnd_cnst_pkg::*;
// Signals
logic [${num_mio_inputs - 1}:0] mio_p2d;
logic [${num_mio_outputs - 1}:0] mio_d2p;
- logic [${num_mio_outputs - 1}:0] mio_d2p_en;
- logic [${num_dio - 1}:0] dio_p2d;
- logic [${num_dio - 1}:0] dio_d2p;
- logic [${num_dio - 1}:0] dio_d2p_en;
+ logic [${num_mio_outputs - 1}:0] mio_en_d2p;
+ logic [${num_dio_total - 1}:0] dio_p2d;
+ logic [${num_dio_total - 1}:0] dio_d2p;
+ logic [${num_dio_total - 1}:0] dio_en_d2p;
% for m in top["module"]:
% if not lib.is_inst(m):
<% continue %>
@@ -398,7 +398,7 @@
<%
mem_name = m["name"].split("_")
-mem_name = Name(mem_name[1:])
+mem_name = lib.Name(mem_name[1:])
%>\
prim_ram_1p_scr #(
.Width(${full_data_width}),
@@ -667,7 +667,7 @@
% if m["type"] == "pinmux":
.periph_to_mio_i (mio_d2p ),
- .periph_to_mio_oe_i (mio_d2p_en ),
+ .periph_to_mio_oe_i (mio_en_d2p ),
.mio_to_periph_o (mio_p2d ),
.mio_attr_o,
@@ -676,7 +676,7 @@
.mio_in_i,
.periph_to_dio_i (dio_d2p ),
- .periph_to_dio_oe_i (dio_d2p_en ),
+ .periph_to_dio_oe_i (dio_en_d2p ),
.dio_to_periph_o (dio_p2d ),
.dio_attr_o,
@@ -743,90 +743,68 @@
% if "pinmux" in top:
// Pinmux connections
- % if num_mio_outputs != 0:
- assign mio_d2p = {
- % for sig in list(reversed(top["pinmux"]["outputs"])):
- cio_${sig["name"]}_d2p${"" if loop.last else ","}
- % endfor
- };
- assign mio_d2p_en = {
- % for sig in list(reversed(top["pinmux"]["outputs"])):
- cio_${sig["name"]}_en_d2p${"" if loop.last else ","}
- % endfor
- };
- % endif
- % if num_mio_inputs != 0:
- assign {
- % for sig in list(reversed(top["pinmux"]["inputs"])):
- cio_${sig["name"]}_p2d${"" if loop.last else ","}
- % endfor
- } = mio_p2d;
- % endif
-% endif
-
-% if num_dio != 0:
- // Dedicated IO connections
- // Input-only DIOs have no d2p signals
- assign dio_d2p = {<% vector_idx = num_dio - 1 %>
- % for sig in top["pinmux"]["dio"]:
- % if sig["type"] in ["output", "inout"]:
- % if sig["width"] > 1:
- % for i in range(sig["width"]-1,-1,-1):
- cio_${sig["name"]}_d2p[${i}]${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
- % endfor
- % else:
- cio_${sig["name"]}_d2p${"" if vector_idx == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
- % endif
- % else:
- % if sig["width"] > 1:
- ${sig["width"]}'b0${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx} - DIO${vector_idx-sig["width"] + 1}: cio_${sig["name"]}<% vector_idx -= sig["width"] %>
- % else:
- ${sig["width"]}'b0${"" if vector_idx == 0 else ","} // DIO${vector_idx}: cio_${sig["name"]}<% vector_idx -= 1 %>
- % endif
+ // All muxed inputs
+ % for sig in top["pinmux"]["ios"]:
+ % if sig["connection"] == "muxed" and sig["type"] in ["inout", "input"]:
+<% literal = lib.get_io_enum_literal(sig, 'mio_in') %>\
+ assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""} = mio_p2d[${literal}];
% endif
% endfor
- };
- assign dio_d2p_en = {<% vector_idx = num_dio - 1 %>
- % for sig in top["pinmux"]["dio"]:
- % if sig["type"] in ["output", "inout"]:
- % if sig["width"] > 1:
- % for i in range(sig["width"]-1,-1,-1):
- cio_${sig["name"]}_en_d2p[${i}]${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
- % endfor
- % else:
- cio_${sig["name"]}_en_d2p${"" if vector_idx == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
- % endif
- % else:
- % if sig["width"] > 1:
- ${sig["width"]}'b0${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx} - DIO${vector_idx-sig["width"] + 1}: cio_${sig["name"]}<% vector_idx -= sig["width"] %>
- % else:
- ${sig["width"]}'b0${"" if vector_idx == 0 else ","} // DIO${vector_idx}: cio_${sig["name"]}<% vector_idx -= 1 %>
- % endif
+ // All muxed outputs
+ % for sig in top["pinmux"]["ios"]:
+ % if sig["connection"] == "muxed" and sig["type"] in ["inout", "output"]:
+<% literal = lib.get_io_enum_literal(sig, 'mio_out') %>\
+ assign mio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""};
% endif
% endfor
- };
- // Output-only DIOs have no p2d signal<% vector_idx = num_dio - 1 %>
- % for sig in top["pinmux"]["dio"]:
- % if sig["type"] in ["input", "inout"]:
- % if sig["width"] > 1:
- % for i in range(sig["width"]-1,-1,-1):
- assign cio_${sig["name"]}_p2d[${i}]${" " * (max_diolength - len(str(i)) - 2 - len(sig["name"]))} = dio_p2d[${vector_idx}]; // DIO${vector_idx}<% vector_idx -= 1 %>
- % endfor
- % else:
- assign cio_${sig["name"]}_p2d${" " * (max_diolength - len(sig["name"]))} = dio_p2d[${vector_idx}]; // DIO${vector_idx}<% vector_idx -= 1 %>
- % endif
- % else:
- % if sig["width"] > 1:
- % for i in range(sig["width"]-1,-1,-1):
- // DIO${vector_idx}: cio_${sig["name"]}[${i}] // DIO${vector_idx}<% vector_idx -= 1 %>
- % endfor
- % else:
- // DIO${vector_idx}: cio_${sig["name"]} // DIO${vector_idx}<% vector_idx -= 1 %>
- % endif
+ // All muxed output enables
+ % for sig in top["pinmux"]["ios"]:
+ % if sig["connection"] == "muxed" and sig["type"] in ["inout", "output"]:
+<% literal = lib.get_io_enum_literal(sig, 'mio_out') %>\
+ assign mio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""};
% endif
% endfor
+
+ // All dedicated inputs
+<% idx = 0 %>\
+ logic [${num_dio_total-1}:0] unused_dio_p2d;
+ % for sig in top["pinmux"]["ios"]:
+<% literal = lib.get_io_enum_literal(sig, 'dio') %>\
+ % if sig["connection"] != "muxed" and sig["type"] in ["inout"]:
+ assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""} = dio_p2d[${literal}];
+ % elif sig["connection"] != "muxed" and sig["type"] in ["input"]:
+ assign cio_${sig["name"]}_p2d${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""} = dio_p2d[${literal}];
+ % elif sig["connection"] != "muxed" and sig["type"] in ["output"]:
+ assign unused_dio_p2d[${idx}] = dio_p2d[${literal}];<% idx += 1 %>
+ % endif
+ % endfor
+
+ // All dedicated outputs
+ % for sig in top["pinmux"]["ios"]:
+<% literal = lib.get_io_enum_literal(sig, 'dio') %>\
+ % if sig["connection"] != "muxed" and sig["type"] in ["inout"]:
+ assign dio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""};
+ % elif sig["connection"] != "muxed" and sig["type"] in ["input"]:
+ assign dio_d2p[${literal}] = 1'b0;
+ % elif sig["connection"] != "muxed" and sig["type"] in ["output"]:
+ assign dio_d2p[${literal}] = cio_${sig["name"]}_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""};
+ % endif
+ % endfor
+
+ // All dedicated output enables
+ % for sig in top["pinmux"]["ios"]:
+<% literal = lib.get_io_enum_literal(sig, 'dio') %>\
+ % if sig["connection"] != "muxed" and sig["type"] in ["inout"]:
+ assign dio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""};
+ % elif sig["connection"] != "muxed" and sig["type"] in ["input"]:
+ assign dio_en_d2p[${literal}] = 1'b0;
+ % elif sig["connection"] != "muxed" and sig["type"] in ["output"]:
+ assign dio_en_d2p[${literal}] = cio_${sig["name"]}_en_d2p${"[" + str(sig["idx"]) +"]" if sig["idx"] !=-1 else ""};
+ % endif
+ % endfor
+
% endif
// make sure scanmode_i is never X (including during reset)
diff --git a/util/topgen/templates/toplevel_pkg.sv.tpl b/util/topgen/templates/toplevel_pkg.sv.tpl
index a4346e3..ffd60ed 100644
--- a/util/topgen/templates/toplevel_pkg.sv.tpl
+++ b/util/topgen/templates/toplevel_pkg.sv.tpl
@@ -4,30 +4,8 @@
${gencmd}
<%
import topgen.lib as lib
-
-
-def camelcase(str):
- """Turns a string from 'snake_case' to 'CamelCase'."""
- return "".join([part.capitalize() for part in str.split("_")])
-
-
-def get_dio_pin_enum_literal(sig, start_idx):
- """Returns the DIO pin enum literal with value assignment"""
- if "width" in sig and sig["width"] > 1:
- return_str = ""
- for i in range(int(sig["width"])):
- if i > 0:
- return_str += "\n "
- return_str += camelcase("top_{}_dio_pin_{}_{} = {},".format(
- top["name"], sig["name"], i, start_idx + i))
- return return_str
- return camelcase("top_{}_dio_pin_{} = {},".format(
- top["name"], sig["name"], start_idx))
-
-top_name = top["name"]
-
%>\
-package top_${top_name}_pkg;
+package top_${top["name"]}_pkg;
% for (inst_name, if_name), region in helper.devices():
<%
if_desc = inst_name if if_name is None else '{} device on {}'.format(if_name, inst_name)
@@ -35,12 +13,12 @@
hex_size_bytes = "32'h{:X}".format(region.size_bytes)
%>\
/**
- * Peripheral base address for ${if_desc} in top ${top_name}.
+ * Peripheral base address for ${if_desc} in top ${top["name"]}.
*/
parameter int unsigned ${region.base_addr_name().as_c_define()} = ${hex_base_addr};
/**
- * Peripheral size in bytes for ${if_desc} in top ${top_name}.
+ * Peripheral size in bytes for ${if_desc} in top ${top["name"]}.
*/
parameter int unsigned ${region.size_bytes_name().as_c_define()} = ${hex_size_bytes};
@@ -51,25 +29,82 @@
hex_size_bytes = "32'h{:x}".format(region.size_bytes)
%>\
/**
- * Memory base address for ${name} in top ${top_name}.
+ * Memory base address for ${name} in top ${top["name"]}.
*/
parameter int unsigned ${region.base_addr_name().as_c_define()} = ${hex_base_addr};
/**
- * Memory size for ${name} in top ${top_name}.
+ * Memory size for ${name} in top ${top["name"]}.
*/
parameter int unsigned ${region.size_bytes_name().as_c_define()} = ${hex_size_bytes};
% endfor
- // Enumeration for DIO pins.
+
+ // Enumeration of IO power domains.
+ // Only used in ASIC target.
typedef enum {
- <% pin_cnt = 0 %>\
- % for sig in reversed(top["pinmux"]["dio"]):
- ${get_dio_pin_enum_literal(sig, pin_cnt)}
- <% pin_cnt += int(sig["width"]) if "width" in sig else 1 %>\
- % endfor
- ${camelcase("top_{}_dio_pin_count".format(top_name))} = ${pin_cnt}
- } top_${top_name}_dio_pin_e;
+% for bank in top["pinout"]["banks"]:
+ ${lib.Name(['io', 'bank', bank]).as_camel_case()} = ${loop.index},
+% endfor
+ IoBankCount = ${len(top["pinout"]["banks"])}
+ } pwr_dom_e;
+
+ // Enumeration for MIO signals on the top-level.
+ typedef enum {
+% for sig in top["pinmux"]["ios"]:
+ % if sig['type'] in ['inout', 'input'] and sig['connection'] == 'muxed':
+ ${lib.get_io_enum_literal(sig, 'mio_in')} = ${sig['glob_idx']},
+ % endif
+% endfor
+<% total = top["pinmux"]['io_counts']['muxed']['inouts'] + \
+ top["pinmux"]['io_counts']['muxed']['inputs'] %>\
+ ${lib.Name.from_snake_case("mio_in_count").as_camel_case()} = ${total}
+ } mio_in_e;
+
+ typedef enum {
+% for sig in top["pinmux"]["ios"]:
+ % if sig['type'] in ['inout', 'output'] and sig['connection'] == 'muxed':
+ ${lib.get_io_enum_literal(sig, 'mio_out')} = ${sig['glob_idx']},
+ % endif
+% endfor
+<% total = top["pinmux"]['io_counts']['muxed']['inouts'] + \
+ top["pinmux"]['io_counts']['muxed']['outputs'] %>\
+ ${lib.Name.from_snake_case("mio_out_count").as_camel_case()} = ${total}
+ } mio_out_e;
+
+ // Enumeration for DIO signals, used on both the top and chip-levels.
+ typedef enum {
+% for sig in top["pinmux"]["ios"]:
+ % if sig['connection'] != 'muxed':
+ ${lib.get_io_enum_literal(sig, 'dio')} = ${sig['glob_idx']},
+ % endif
+% endfor
+<% total = top["pinmux"]['io_counts']['dedicated']['inouts'] + \
+ top["pinmux"]['io_counts']['dedicated']['inputs'] + \
+ top["pinmux"]['io_counts']['dedicated']['outputs'] %>\
+ ${lib.Name.from_snake_case("dio_count").as_camel_case()} = ${total}
+ } dio_e;
+
+ // Raw MIO/DIO input array indices on chip-level.
+ // TODO: Does not account for target specific stubbed/added pads.
+ // Need to make a target-specific package for those.
+ typedef enum {
+% for pad in top["pinout"]["pads"]:
+ % if pad["connection"] == "muxed":
+ ${lib.Name.from_snake_case("mio_pad_" + pad["name"]).as_camel_case()} = ${pad["idx"]},
+ % endif
+% endfor
+ ${lib.Name.from_snake_case("mio_pad_count").as_camel_case()}
+ } mio_pad_e;
+
+ typedef enum {
+% for pad in top["pinout"]["pads"]:
+ % if pad["connection"] != "muxed":
+ ${lib.Name.from_snake_case("dio_pad_" + pad["name"]).as_camel_case()} = ${pad["idx"]},
+ % endif
+% endfor
+ ${lib.Name.from_snake_case("dio_pad_count").as_camel_case()}
+ } dio_pad_e;
// TODO: Enumeration for PLIC Interrupt source peripheral.
// TODO: Enumeration for PLIC Interrupt Ids.
diff --git a/util/topgen/validate.py b/util/topgen/validate.py
index 94b4234..b259f3c 100644
--- a/util/topgen/validate.py
+++ b/util/topgen/validate.py
@@ -1,9 +1,11 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
+import re
import logging as log
from collections import OrderedDict
from enum import Enum
+from typing import Dict, List
from reggen.validate import check_keys
from reggen.ip_block import IpBlock
@@ -40,15 +42,15 @@
'clocks': ['g', 'group of clock properties'],
'resets': ['l', 'list of resets'],
'module': ['l', 'list of modules to instantiate'],
- 'memory': [
- 'l', 'list of memories. At least one memory is needed to run \
- the software'
- ],
- 'debug_mem_base_addr':
- ['d', 'Base address of RV_DM. Planned to move to \
-module'],
+ 'memory': ['l', 'list of memories. At least one memory '
+ 'is needed to run the software'],
+ 'debug_mem_base_addr': ['d', 'Base address of RV_DM. '
+ 'Planned to move to module'],
'xbar': ['l', 'List of the xbar used in the top'],
'rnd_cnst_seed': ['int', "Seed for random netlist constant computation"],
+ 'pinout': ['g', 'Pinout configuration'],
+ 'targets': ['l', ' Target configurations'],
+ 'pinmux': ['g', 'pinmux configuration'],
}
top_optional = {
@@ -65,11 +67,6 @@
'interrupt': ['lnw', 'interrupts (generated)'],
'interrupt_module': ['l', 'list of the modules that connects to rv_plic'],
'num_cores': ['pn', "number of computing units"],
- 'padctrl': [
- 'g',
- 'PADS instantiation, if doesn\'t exist, tool creates direct output'
- ],
- 'pinmux': ['g', 'pinmux definition if doesn\'t exist, tool uses defaults'],
'power': ['g', 'power domains supported by the design'],
'port': ['g', 'assign special attributes to specific ports']
}
@@ -78,26 +75,98 @@
pinmux_required = {}
pinmux_optional = {
- 'num_mio': [
- 'd', 'Number of Multiplexed IOs'
- ' If padctrl is used, this value will be replaced with #pads'
- ' - #DIO'
+ 'num_wkup_detect': [
+ 'd', 'Number of wakeup detectors'
],
- 'dio_modules': ['l', 'List of Dedicated IOs.'],
- 'mio_modules': ['l', 'List of Multiplexed IPs/IOs'],
- 'nc_modules': ['l', 'List of NotConnected IOs'],
+ 'wkup_cnt_width': [
+ 'd', 'Number of bits in wakeup detector counters'
+ ],
+ 'signals': ['l', 'List of Dedicated IOs.'],
}
pinmux_added = {
- 'inputs': ['l', 'Full list of SoC inputs, `module_name.sig_name`'],
- 'outputs': ['l', 'Full list of SoC outputs, `module_name.sig_name`'],
+ 'ios': ['l', 'Full list of IO'],
}
-padctrl_required = {}
-padctrl_optional = {
- 'pads': ['l', 'List of pads'],
- 'attr_default': ['l', 'List of the attribute']
+pinmux_sig_required = {
+ 'instance': ['s', 'Module instance name'],
+ 'connection': ['s', 'Specification of connection type, '
+ 'can be direct, manual or muxed'],
}
-padctrl_added = {}
+pinmux_sig_optional = {
+ 'port': ['s', 'Port name of module'],
+ 'pad': ['s', 'Pad name for direct connections'],
+ 'desc': ['s', 'Signal description']
+}
+pinmux_sig_added = {}
+
+pinout_required = {
+ 'banks': ['l', 'List of IO power banks'],
+ 'pads': ['l', 'List of pads']
+}
+pinout_optional = {
+}
+pinout_added = {}
+
+pad_required = {
+ 'name': ['l', 'Pad name'],
+ 'type': ['s', 'Pad type'],
+ 'bank': ['s', 'IO power bank for the pad'],
+ 'connection': ['s', 'Specification of connection type, '
+ 'can be direct, manual or muxed'],
+}
+pad_optional = {
+ 'desc': ['s', 'Pad description'],
+}
+pad_added = {}
+
+target_required = {
+ 'name': ['s', 'Name of target'],
+ 'pinout': ['g', 'Target-specific pinout configuration'],
+ 'pinmux': ['g', 'Target-specific pinmux configuration']
+}
+target_optional = {
+}
+target_added = {}
+
+target_pinmux_required = {
+ 'special_signals': ['l', 'List of special signals and the pad they are mapped to.'],
+}
+target_pinmux_optional = {}
+target_pinmux_added = {}
+
+target_pinout_required = {
+ 'remove_pads': ['l', 'List of pad names to remove and stub out'],
+ 'add_pads': ['l', 'List of manual pads to add'],
+}
+target_pinout_optional = {}
+target_pinout_added = {}
+
+straps_required = {
+ 'tap0': ['s', 'Name of tap0 pad'],
+ 'tap1': ['s', 'Name of tap1 pad'],
+ 'dft0': ['s', 'Name of dft0 pad'],
+ 'dft1': ['s', 'Name of dft1 pad'],
+}
+straps_optional = {}
+straps_added = {}
+
+straps_required = {
+ 'tap0': ['s', 'Name of tap0 pad'],
+ 'tap1': ['s', 'Name of tap1 pad'],
+ 'dft0': ['s', 'Name of dft0 pad'],
+ 'dft1': ['s', 'Name of dft1 pad'],
+}
+straps_optional = {}
+straps_added = {}
+
+special_sig_required = {
+ 'name': ['s', 'DIO name'],
+ 'pad': ['s', 'Pad name'],
+}
+special_sig_optional = {
+ 'desc': ['s', 'Description of signal connection'],
+}
+special_sig_added = {}
clock_srcs_required = {
'name': ['s', 'name of clock group'],
@@ -149,6 +218,23 @@
eflash_added = {}
+# Supported PAD types.
+# Needs to coincide with enum definition in prim_pad_wrapper_pkg.sv
+class PadType(Enum):
+ INPUT_STD = 'InputStd'
+ BIDIR_STD = 'BidirStd'
+ BIDIR_TOL = 'BidirTol'
+ BIDIR_OD = 'BidirOd'
+
+
+def is_valid_pad_type(obj):
+ try:
+ PadType(obj)
+ except ValueError:
+ return False
+ return True
+
+
class TargetType(Enum):
MODULE = "module"
XBAR = "xbar"
@@ -189,10 +275,11 @@
return (n != 0) and (n & (n - 1) == 0)
def check_values(self):
- pow2_check = self.is_pow2(self.banks) and self.is_pow2(self.pages_per_bank) and \
- self.is_pow2(self.program_resolution)
- limit_check = (self.banks <= Flash.max_banks) \
- and (self.pages_per_bank <= Flash.max_pages_per_bank)
+ pow2_check = (self.is_pow2(self.banks) and
+ self.is_pow2(self.pages_per_bank) and
+ self.is_pow2(self.program_resolution))
+ limit_check = ((self.banks <= Flash.max_banks) and
+ (self.pages_per_bank <= Flash.max_pages_per_bank))
return pow2_check and limit_check
@@ -255,14 +342,203 @@
return error, idxs
-def check_padctrl(top, prefix):
- error = check_keys(top["padctrl"], padctrl_required, padctrl_optional,
- padctrl_added, prefix + " PadControl")
+def check_pad(top: Dict,
+ pad: Dict,
+ known_pad_names: Dict,
+ valid_connections: List[str],
+ prefix: str) -> int:
+ error = 0
+ error += check_keys(pad, pad_required, pad_optional,
+ pad_added, prefix)
+
+ # check name uniqueness
+ if pad['name'] in known_pad_names:
+ log.warning('Pad name {} is not unique'.format(pad['name']))
+ error += 1
+ known_pad_names[pad['name']] = 1
+
+ if not is_valid_pad_type(pad['type']):
+ log.warning('Unkown pad type {}'.format(pad['type']))
+ error += 1
+
+ if pad['bank'] not in top['pinout']['banks']:
+ log.warning('Unkown io power bank {}'.format(pad['bank']))
+ error += 1
+
+ if pad['connection'] not in valid_connections:
+ log.warning('Connection type {} of pad {} is invalid'
+ .format(pad['connection'], pad['name']))
+ error += 1
+
return error
-def check_pinmux(top, prefix):
- return 0
+def check_pinout(top: Dict, prefix: str) -> int:
+ error = check_keys(top['pinout'], pinout_required, pinout_optional,
+ pinout_added, prefix + ' Pinout')
+
+ known_names = {}
+ for pad in top['pinout']['pads']:
+ error += check_keys(pad, pad_required, pad_optional,
+ pad_added, prefix + ' Pinout')
+
+ error += check_pad(top, pad, known_names,
+ ['direct', 'manual', 'muxed'],
+ prefix + ' Pad')
+
+ return error
+
+
+def check_pinmux(top: Dict, prefix: str) -> int:
+ error = check_keys(top['pinmux'], pinmux_required, pinmux_optional,
+ pinmux_added, prefix + ' Pinmux')
+
+ # This is used for the direct connection accounting below,
+ # where we tick off already connected direct pads.
+ known_direct_pads = {}
+ for pad in top['pinout']['pads']:
+ if pad['connection'] == 'direct':
+ known_direct_pads[pad['name']] = 1
+
+ # Note: the actual signal crosscheck is deferred until the merge stage,
+ # since we have no idea at this point which IOs comportable IPs expose.
+ for sig in top['pinmux']['signals']:
+ error += check_keys(sig, pinmux_sig_required, pinmux_sig_optional,
+ pinmux_sig_added, prefix + ' Pinmux signal')
+
+ if sig['connection'] not in ['direct', 'manual', 'muxed']:
+ log.warning('Invalid connection type {}'.format(sig['connection']))
+ error += 1
+
+ # The pad needs to refer to a valid pad name in the pinout that is of
+ # connection type "direct". We tick off all direct pads that have been
+ # referenced in order to make sure there are no double connections
+ # and unconnected direct pads.
+ padname = sig.setdefault('pad', '')
+ if padname != '':
+ if padname in known_direct_pads:
+ if known_direct_pads[padname] == 1:
+ known_direct_pads[padname] = 0
+ else:
+ log.warning('Warning, direct pad {} is already connected'
+ .format(padname))
+ error += 1
+ else:
+ log.warning('Unknown direct pad {}'.format(padname))
+ error += 1
+
+ # Check port naming scheme.
+ port = sig.setdefault('port', '')
+ pattern = r'^[a-zA-Z0-9_]*(\[[0-9]*\]){0,1}'
+ matches = re.match(pattern, port)
+ if matches is None:
+ log.warning('Port name {} has wrong format'
+ .format(port))
+ error += 1
+
+ # Check that only direct connections have pad keys
+ if sig['connection'] == 'direct':
+ if padname == '':
+ log.warning('Instance {} port {} connection is of direct type '
+ 'and therefore must have an associated pad name.'
+ .format(sig['instance'],
+ sig['port']))
+ error += 1
+ if port == '':
+ log.warning('Instance {} port {} connection is of direct type '
+ 'and therefore must have an associated port name.'
+ .format(sig['instance'],
+ sig['port']))
+ error += 1
+ else:
+ if padname != '':
+ log.warning('Muxed/manual connection of instance {} port {} '
+ 'must not have an associated pad'
+ .format(sig['instance'],
+ sig['port']))
+ error += 1
+
+ # At this point, all direct pads should have been ticked off.
+ for key, val in known_direct_pads.items():
+ if val == 1:
+ log.warning('Direct pad {} has not been connected'
+ .format(key))
+ error += 1
+
+ return error
+
+
+def check_implementation_targets(top: Dict, prefix: str) -> int:
+ error = 0
+ known_names = {}
+ for target in top['targets']:
+ error += check_keys(target, target_required, target_optional,
+ target_added, prefix + ' Targets')
+
+ # check name uniqueness
+ if target['name'] in known_names:
+ log.warning('Target name {} is not unique'.format(target['name']))
+ error += 1
+ known_names[target['name']] = 1
+
+ error += check_keys(target['pinmux'], target_pinmux_required, target_pinmux_optional,
+ target_pinmux_added, prefix + ' Target pinmux')
+
+ error += check_keys(target['pinout'], target_pinout_required, target_pinout_optional,
+ target_pinout_added, prefix + ' Target pinout')
+
+ # Check special pad signals
+ known_entry_names = {}
+ for entry in target['pinmux']['special_signals']:
+ error += check_keys(entry, special_sig_required, special_sig_optional,
+ special_sig_added, prefix + ' Special signal')
+
+ # check name uniqueness
+ if entry['name'] in known_entry_names:
+ log.warning('Special pad name {} is not unique'.format(entry['name']))
+ error += 1
+ known_entry_names[entry['name']] = 1
+
+ # The pad key needs to refer to a valid pad name.
+ is_muxed = False
+ for pad in top['pinout']['pads']:
+ if entry['pad'] == pad['name']:
+ is_muxed = pad['connection'] == 'muxed'
+ break
+ else:
+ log.warning('Unknown pad {}'.format(entry['pad']))
+ error += 1
+
+ if not is_muxed:
+ # If this is not a muxed pad, we need to make sure this refers to
+ # DIO that is NOT a manual pad.
+ for sig in top['pinmux']['signals']:
+ if entry['pad'] == sig['pad']:
+ break
+ else:
+ log.warning('Special pad {} cannot refer to a manual pad'.format(entry['pad']))
+ error += 1
+
+ # Check pads to remove and stub out
+ for entry in target['pinout']['remove_pads']:
+ # The pad key needs to refer to a valid pad name.
+ for pad in top['pinout']['pads']:
+ if entry == pad['name']:
+ break
+ else:
+ log.warning('Unknown pad {}'.format(entry))
+ error += 1
+
+ # Check pads to add
+ known_pad_names = {}
+ for pad in top['pinout']['pads']:
+ known_pad_names.update({pad['name']: 1})
+
+ for pad in target['pinout']['add_pads']:
+ error += check_pad(top, pad, known_pad_names, ['manual'],
+ prefix + ' Additional Pad')
+
+ return error
# check for inconsistent clock group definitions
@@ -558,21 +834,11 @@
# RV_PLIC check
- # PINMUX & PADS check
- if "padctrl" not in top:
- log.warning("padsctrl field doesn't exist in top. Skipping pads \
- generation. Top input/output are directly connected from \
- peripherals.")
- # Pads configuration check
- else:
- error += check_padctrl(top, component)
-
- if "pinmux" not in top:
- log.warning("Top {} has no 'pinmux' field. Please consider specifying \
- pinmux and pads configuration")
- top["pinmux"] = OrderedDict()
- # checking pinmux after pads as dio connects to PAD
-
+ # Pinout, pinmux and target checks
+ # Note that these checks must happen in this order, as
+ # the pinmux and target configs depend on the pinout.
+ error += check_pinout(top, component)
error += check_pinmux(top, component)
+ error += check_implementation_targets(top, component)
return top, error
