[AST] Update prim_mubi4_sync parameter
Signed-off-by: Jacob Levy <jacob.levy@opentitan.org>
diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core
index 524794e..12b0440 100644
--- a/hw/top_earlgrey/ip/ast/ast.core
+++ b/hw/top_earlgrey/ip/ast/ast.core
@@ -28,28 +28,29 @@
- rtl/ast_pkg.sv
- rtl/ast_bhv_pkg.sv
- rtl/ast.sv
+ - rtl/ast_reg_top.sv
- rtl/adc.sv
- rtl/adc_ana.sv
- - rtl/aon_clk.sv
- - rtl/aon_osc.sv
- - rtl/ast_dft.sv
- - rtl/ast_reg_top.sv
- - rtl/ast_entropy.sv
- - rtl/dev_entropy.sv
- - rtl/ast_alert.sv
- rtl/vcc_pgd.sv
- rtl/vio_pgd.sv
- rtl/vcaon_pgd.sv
- rtl/vcmain_pgd.sv
- - rtl/gfr_clk_mux2.sv
+ - rtl/ast_alert.sv
+ - rtl/aon_clk.sv
+ - rtl/aon_osc.sv
- rtl/io_clk.sv
- rtl/io_osc.sv
- - rtl/rglts_pdm_3p3v.sv
- - rtl/rng.sv
- rtl/sys_clk.sv
- rtl/sys_osc.sv
- rtl/usb_clk.sv
- rtl/usb_osc.sv
+ - rtl/gfr_clk_mux2.sv
+ - rtl/ast_clks_byp.sv
+ - rtl/rglts_pdm_3p3v.sv
+ - rtl/ast_entropy.sv
+ - rtl/dev_entropy.sv
+ - rtl/rng.sv
+ - rtl/ast_dft.sv
file_type: systemVerilogSource
files_verilator_waiver:
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index 3602c39..b12b4dc 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -277,7 +277,7 @@
// Regulators & PDM Logic (VCC)
///////////////////////////////////////
-logic clk_aon;
+logic clk_aon, deep_sleep;
rglts_pdm_3p3v u_rglts_pdm_3p3v (
.vcc_pok_h_i ( vcc_pok_h ),
@@ -290,6 +290,7 @@
.scan_mode_i ( scan_mode ),
.vcaon_pok_h_o ( vcaon_pok_h_int ),
.main_pwr_dly_o ( main_pwr_dly_o ),
+ .deep_sleep_h_o ( deep_sleep ),
.otp_power_seq_h_o ( otp_power_seq_h_o[1:0] ),
.flash_power_down_h_o ( flash_power_down_h_o ),
.flash_power_ready_h_o ( flash_power_ready_h_o )
@@ -348,7 +349,7 @@
assign clk_usb_ext = clk_osc_byp_i.usb;
`endif
assign rst_usb_clk_n = vcmain_pok_por;
-assign clk_usb_pd_n = vcmain_pok;
+assign clk_usb_pd_n = !deep_sleep;
usb_clk u_usb_clk (
.vcore_pok_h_i ( vcaon_pok_h ),
@@ -446,6 +447,39 @@
///////////////////////////////////////
+// AST Clocks Bypass
+///////////////////////////////////////
+ast_clks_byp u_ast_clks_byp (
+ .clk_i ( clk_ast_tlul_i ),
+ .rst_ni ( rst_ast_tlul_ni ),
+ .vcaon_pok_i ( vcaon_pok ),
+ .deep_sleep_i ( deep_sleep ),
+ .clk_osc_sys_i ( clk_osc_sys ),
+ .clk_osc_sys_val_i ( clk_osc_sys_val ),
+ .clk_osc_io_i ( clk_osc_io ),
+ .clk_osc_io_val_i ( clk_osc_io_val ),
+ .clk_osc_usb_i ( clk_osc_usb ),
+ .clk_osc_usb_val_i ( clk_osc_usb_val ),
+ .clk_osc_aon_i ( clk_osc_aon ),
+ .clk_osc_aon_val_i ( clk_osc_aon_val ),
+ .clk_ast_ext_i ( clk_ast_ext_i ),
+ .io_clk_byp_req_i ( io_clk_byp_req_i ),
+ .all_clk_byp_req_i ( all_clk_byp_req_i ),
+ .ext_freq_is_96m_i ( ext_freq_is_96m_i ),
+ .io_clk_byp_ack_o ( io_clk_byp_ack_o ),
+ .all_clk_byp_ack_o ( all_clk_byp_ack_o ),
+ .clk_src_sys_o ( clk_src_sys_o ),
+ .clk_src_sys_val_o ( clk_src_sys_val_o ),
+ .clk_src_io_o ( clk_src_io_o ),
+ .clk_src_io_val_o ( clk_src_io_val_o ),
+ .clk_src_usb_o ( clk_src_usb_o ),
+ .clk_src_usb_val_o ( clk_src_usb_val_o ),
+ .clk_src_aon_o ( clk_src_aon_o ),
+ .clk_src_aon_val_o ( clk_src_aon_val_o )
+);
+
+
+///////////////////////////////////////
// ADC (Always ON)
///////////////////////////////////////
adc #(
@@ -744,33 +778,7 @@
///////////////////////////////////////
// DFT (Main | Always ON)
///////////////////////////////////////
-
ast_dft u_ast_dft (
- .clk_i ( clk_ast_tlul_i ),
- .rst_ni ( rst_ast_tlul_ni ),
- .vcaon_pok_i ( vcaon_pok ),
- .clk_osc_sys_i ( clk_osc_sys ),
- .clk_osc_sys_val_i ( clk_osc_sys_val ),
- .clk_osc_io_i ( clk_osc_io ),
- .clk_osc_io_val_i ( clk_osc_io_val ),
- .clk_osc_usb_i ( clk_osc_usb ),
- .clk_osc_usb_val_i ( clk_osc_usb_val ),
- .clk_osc_aon_i ( clk_osc_aon ),
- .clk_osc_aon_val_i ( clk_osc_aon_val ),
- .all_clk_byp_req_i ( all_clk_byp_req_i ),
- .io_clk_byp_req_i ( io_clk_byp_req_i ),
- .ext_freq_is_96m_i ( ext_freq_is_96m_i ),
- .clk_ast_ext_i ( clk_ast_ext_i ),
- .clk_src_sys_o ( clk_src_sys_o ),
- .clk_src_sys_val_o ( clk_src_sys_val_o ),
- .clk_src_io_o ( clk_src_io_o ),
- .clk_src_io_val_o ( clk_src_io_val_o ),
- .clk_src_usb_o ( clk_src_usb_o ),
- .clk_src_usb_val_o ( clk_src_usb_val_o ),
- .clk_src_aon_o ( clk_src_aon_o ),
- .clk_src_aon_val_o ( clk_src_aon_val_o ),
- .io_clk_byp_ack_o ( io_clk_byp_ack_o ),
- .all_clk_byp_ack_o ( all_clk_byp_ack_o ),
.dpram_rmf_o ( dpram_rmf_o ),
.dpram_rml_o ( dpram_rml_o ),
.spram_rm_o ( spram_rm_o ),
@@ -778,6 +786,7 @@
.sprom_rm_o ( sprom_rm_o )
);
+
////////////////////////////////////////
// DFT Misc Logic
////////////////////////////////////////
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv b/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv
new file mode 100644
index 0000000..bd1b853
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_clks_byp.sv
@@ -0,0 +1,305 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: ast_clks_byp
+// *Module Description: AST Clocks Bypass
+//############################################################################
+
+`include "prim_assert.sv"
+
+module ast_clks_byp (
+ input clk_i, // TLUL Clock
+ input rst_ni, // TLUL Reset
+ input vcaon_pok_i, // VCAON POK
+ input deep_sleep_i, // Deep Sleep (main regulator & switch are off)
+ input clk_osc_sys_i, // SYS Oscillator Clock
+ input clk_osc_sys_val_i, // SYS Oscillator Clock Valid
+ input clk_osc_io_i, // IO Oscillator Clock
+ input clk_osc_io_val_i, // IO Oscillator Clock Valid
+ input clk_osc_usb_i, // USB Oscillator Clock
+ input clk_osc_usb_val_i, // USB Oscillator Clock Valid
+ input clk_osc_aon_i, // AON Oscillator Clock
+ input clk_osc_aon_val_i, // AON Oscillator Clock Valid
+ input clk_ast_ext_i, // External Clock
+ input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // External IO clock mux for OTP bootstrap
+ input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override
+ input ext_freq_is_96m_i, // External Clock Frequecy is 96MHz (else 48MHz)
+ output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clock
+ output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clock
+ output logic clk_src_sys_o, // SYS Source Clock
+ output logic clk_src_sys_val_o, // SYS Source Clock Valid
+ output logic clk_src_io_o, // IO Source Clock
+ output logic clk_src_io_val_o, // IO Source Clock Valid
+ output logic clk_src_usb_o, // USB Source Clock
+ output logic clk_src_usb_val_o, // USB Source Clock Valid
+ output logic clk_src_aon_o, // AON Source Clock
+ output logic clk_src_aon_val_o // AON Source Clock Valid
+);
+
+logic ext_clk, rst_aon_n;
+
+logic scan_mode_i;
+
+assign scan_mode_i = 1'b0;
+assign ext_clk = clk_ast_ext_i;
+assign rst_aon_n = vcaon_pok_i;
+
+
+////////////////////////////////////////
+// Source Clocks Selection
+////////////////////////////////////////
+
+
+
+// SW Bypass select logic
+////////////////////////////////////////
+
+// Sync to local TLUL clcok
+prim_mubi_pkg::mubi4_t io_clk_byp_req, all_clk_byp_req;
+logic sw_ext_freq_is_96m;
+
+prim_mubi4_sync #(
+ .StabilityCheck ( 1 ),
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_io_clk_byp_req (
+ .clk_i,
+ .rst_ni,
+ .mubi_i ( io_clk_byp_req_i ),
+ .mubi_o ( io_clk_byp_req )
+);
+
+prim_mubi4_sync #(
+ .StabilityCheck ( 1 ),
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_all_clk_byp_req (
+ .clk_i,
+ .rst_ni,
+ .mubi_i ( all_clk_byp_req_i ),
+ .mubi_o ( all_clk_byp_req )
+);
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_sw_ext_freq_sync (
+ .clk_i ( ext_clk ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( ext_freq_is_96m_i ),
+ .q_o ( sw_ext_freq_is_96m )
+);
+
+// Decode logic
+prim_mubi_pkg::mubi4_t io_clk_byp_sel_req;
+logic all_clk_byp, sys_clk_byp, io_clk_byp, usb_clk_byp, aon_clk_byp;
+
+assign io_clk_byp_sel_req = prim_mubi_pkg::mubi4_test_true_strict( all_clk_byp_req ) ?
+ prim_mubi_pkg::MuBi4True : io_clk_byp_req;
+
+prim_mubi4_dec u_all_byp_sel ( .mubi_i ( all_clk_byp_req ), .mubi_dec_o ( all_clk_byp ) );
+prim_mubi4_dec u_sys_byp_sel ( .mubi_i ( all_clk_byp_req ), .mubi_dec_o ( sys_clk_byp ) );
+prim_mubi4_dec u_io_byp_sel ( .mubi_i ( io_clk_byp_sel_req ), .mubi_dec_o ( io_clk_byp ) );
+prim_mubi4_dec u_usb_byp_sel ( .mubi_i ( all_clk_byp_req ), .mubi_dec_o ( usb_clk_byp ) );
+prim_mubi4_dec u_aon_byp_sel ( .mubi_i ( all_clk_byp_req ), .mubi_dec_o ( aon_clk_byp ) );
+
+// De-Glitch selects (decode "noise")
+logic sw_all_clk_byp, sw_sys_clk_byp, sw_io_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp;
+
+always_ff @ ( posedge clk_i, negedge rst_ni ) begin
+ if ( !rst_ni ) begin
+ sw_all_clk_byp <= 1'b0;
+ sw_sys_clk_byp <= 1'b0;
+ sw_io_clk_byp <= 1'b0;
+ sw_usb_clk_byp <= 1'b0;
+ sw_aon_clk_byp <= 1'b0;
+ end else begin
+ sw_all_clk_byp <= all_clk_byp;
+ sw_sys_clk_byp <= sys_clk_byp;
+ sw_io_clk_byp <= io_clk_byp;
+ sw_usb_clk_byp <= usb_clk_byp;
+ sw_aon_clk_byp <= aon_clk_byp;
+ end
+end
+
+logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel, ext_freq_is_96m;
+
+assign sys_clk_byp_sel = sw_sys_clk_byp;
+assign io_clk_byp_sel = sw_io_clk_byp;
+assign usb_clk_byp_sel = sw_usb_clk_byp;
+assign aon_clk_byp_sel = sw_aon_clk_byp;
+assign ext_freq_is_96m = sw_ext_freq_is_96m;
+
+
+// External USB & AON clocks genaration
+////////////////////////////////////////
+logic ext_clk_usb, clk_usb_ext;
+
+prim_clock_div #(
+ .Divisor( 2 )
+) u_clk_ext_div2_div (
+ .clk_i ( ext_clk ),
+ .rst_ni ( rst_aon_n ),
+ .step_down_req_i( !ext_freq_is_96m ),
+ .step_down_ack_o ( ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( ext_clk_usb )
+);
+
+assign clk_usb_ext = ext_clk_usb;
+
+logic clk_usb_ext_d240, clk_ext_aon;
+
+prim_clock_div #(
+ .Divisor( 240 )
+) u_clk_usb_div240_div (
+ .clk_i ( clk_usb_ext ),
+ .rst_ni ( rst_aon_n ),
+ .step_down_req_i( 1'b0 ),
+ .step_down_ack_o ( ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_usb_ext_d240 )
+);
+
+assign clk_ext_aon = clk_usb_ext_d240;
+
+
+// Deep Slepp Gators
+////////////////////////////////////////
+logic deep_sleep_n;
+
+prim_flop_2sync #(
+ .Width ( 1 ),
+ .ResetValue ( 1'b0 )
+) u_deep_sleep_sync (
+ .clk_i ( ext_clk ),
+ .rst_ni ( rst_aon_n ),
+ .d_i ( !deep_sleep_i ),
+ .q_o ( deep_sleep_n )
+);
+
+// SYS & IO
+logic clk_ext_sys, clk_ext_io;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_ext_sys_ckgt (
+ .clk_i ( ext_clk ),
+ .en_i ( deep_sleep_n ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_sys )
+);
+
+assign clk_ext_io = clk_ext_sys;
+
+// USB SYS
+logic clk_ext_usb;
+
+prim_clock_gating #(
+ .NoFpgaGate ( 1'b1)
+) u_clk_ext_usb_ckgt (
+ .clk_i ( clk_usb_ext ),
+ .en_i ( deep_sleep_n ),
+ .test_en_i ( scan_mode_i ),
+ .clk_o ( clk_ext_usb )
+);
+
+logic sys_clk_osc_en, io_clk_osc_en, usb_clk_osc_en, aon_clk_osc_en;
+logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en;
+
+logic rst_clk_osc_n, rst_clk_ext_n;
+assign rst_clk_osc_n = vcaon_pok_i;
+assign rst_clk_ext_n = vcaon_pok_i;
+
+// SYS Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_sys_sel (
+ .clk_osc_i ( clk_osc_sys_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_n ),
+ .clk_ext_i ( clk_ext_sys ),
+ .rst_clk_ext_ni ( rst_clk_ext_n ),
+ .ext_sel_i ( sys_clk_byp_sel ),
+ .clk_osc_en_o ( sys_clk_osc_en ),
+ .clk_ext_en_o ( sys_clk_byp_en ),
+ .clk_o ( clk_src_sys_o )
+);
+
+// IO Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_io_sel (
+ .clk_osc_i ( clk_osc_io_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_n ),
+ .clk_ext_i ( clk_ext_io ),
+ .rst_clk_ext_ni ( rst_clk_ext_n ),
+ .ext_sel_i ( io_clk_byp_sel ),
+ .clk_osc_en_o ( io_clk_osc_en ),
+ .clk_ext_en_o ( io_clk_byp_en ),
+ .clk_o ( clk_src_io_o )
+);
+
+// USB Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_usb_sel (
+ .clk_osc_i ( clk_osc_usb_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_n ),
+ .clk_ext_i ( clk_ext_usb ),
+ .rst_clk_ext_ni ( rst_clk_ext_n ),
+ .ext_sel_i ( usb_clk_byp_sel ),
+ .clk_osc_en_o ( usb_clk_osc_en ),
+ .clk_ext_en_o ( usb_clk_byp_en ),
+ .clk_o ( clk_src_usb_o )
+);
+
+// AON Clock Bypass Mux
+////////////////////////////////////////
+gfr_clk_mux2 u_clk_src_aon_sel (
+ .clk_osc_i ( clk_osc_aon_i ),
+ .rst_clk_osc_ni ( rst_clk_osc_n ),
+ .clk_ext_i ( clk_ext_aon ),
+ .rst_clk_ext_ni ( rst_clk_ext_n ),
+ .ext_sel_i ( aon_clk_byp_sel ),
+ .clk_osc_en_o ( aon_clk_osc_en ),
+ .clk_ext_en_o ( aon_clk_byp_en ),
+ .clk_o ( clk_src_aon_o )
+);
+
+assign clk_src_sys_val_o = sys_clk_byp_sel ? sys_clk_byp_en : sys_clk_osc_en && clk_osc_sys_val_i;
+assign clk_src_io_val_o = io_clk_byp_sel ? io_clk_byp_en : io_clk_osc_en && clk_osc_io_val_i;
+assign clk_src_usb_val_o = usb_clk_byp_sel ? usb_clk_byp_en : usb_clk_osc_en && clk_osc_usb_val_i;
+assign clk_src_aon_val_o = aon_clk_byp_sel ? aon_clk_byp_en : aon_clk_osc_en && clk_osc_aon_val_i;
+
+logic all_clks_byp_en;
+prim_mubi_pkg::mubi4_t all_clk_byp_ack;
+
+assign all_clks_byp_en = sw_all_clk_byp && sys_clk_byp_en && io_clk_byp_en &&
+ usb_clk_byp_en && aon_clk_byp_en;
+
+assign all_clk_byp_ack = all_clks_byp_en ? prim_mubi_pkg::MuBi4True :
+ prim_mubi_pkg::MuBi4False;
+
+prim_mubi4_sender #(
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_all_clk_byp_ack (
+ .clk_i,
+ .rst_ni,
+ .mubi_i ( all_clk_byp_ack ),
+ .mubi_o ( all_clk_byp_ack_o )
+);
+
+logic only_io_clk_byp_en;
+prim_mubi_pkg::mubi4_t io_clk_byp_ack;
+
+assign only_io_clk_byp_en = !sw_all_clk_byp && sw_io_clk_byp && io_clk_byp_en;
+
+assign io_clk_byp_ack = only_io_clk_byp_en ? prim_mubi_pkg::MuBi4True :
+ prim_mubi_pkg::MuBi4False;
+
+prim_mubi4_sender #(
+ .ResetValue ( prim_mubi_pkg::MuBi4False )
+) u_io_clk_byp_ack (
+ .clk_i,
+ .rst_ni,
+ .mubi_i ( io_clk_byp_ack ),
+ .mubi_o ( io_clk_byp_ack_o )
+);
+
+endmodule : ast_clks_byp
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv b/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv
index 3aa9281..76aa8e3 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv
@@ -9,31 +9,6 @@
`include "prim_assert.sv"
module ast_dft (
- input clk_i, // TLUL Clock
- input rst_ni, // TLUL Reset
- input vcaon_pok_i, // AON POK
- input clk_osc_sys_i, // SYS Oscillator Clock
- input clk_osc_sys_val_i, // SYS Oscillator Clock Valid
- input clk_osc_io_i, // IO Oscillator Clock
- input clk_osc_io_val_i, // IO Oscillator Clock Valid
- input clk_osc_usb_i, // USB Oscillator Clock
- input clk_osc_usb_val_i, // USB Oscillator Clock Valid
- input clk_osc_aon_i, // AON Oscillator Clock
- input clk_osc_aon_val_i, // AON Oscillator Clock Valid
- input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // External IO clock mux for OTP bootstrap
- input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override
- input ext_freq_is_96m_i, // External Clock Frequecy is 96MHz (else 48MHz)
- input clk_ast_ext_i, // External Clock
- output logic clk_src_sys_o, // SYS Source Clock
- output logic clk_src_sys_val_o, // SYS Source Clock Valid
- output logic clk_src_io_o, // IO Source Clock
- output logic clk_src_io_val_o, // IO Source Clock Valid
- output logic clk_src_usb_o, // USB Source Clock
- output logic clk_src_usb_val_o, // USB Source Clock Valid
- output logic clk_src_aon_o, // AON Source Clock
- output logic clk_src_aon_val_o, // AON Source Clock Valid
- output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clock
- output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clock
// memories read-write margins
output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast
output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow
@@ -42,244 +17,6 @@
output ast_pkg::spm_rm_t sprom_rm_o // Single Port ROM Read-write Margin
);
-logic ext_clk, rst_aon_n;
-
-logic scan_mode_i;
-assign scan_mode_i = 1'b0;
-
-assign ext_clk = clk_ast_ext_i;
-assign rst_aon_n = vcaon_pok_i;
-
-
-////////////////////////////////////////
-// Source Clocks Selection
-////////////////////////////////////////
-
-
-
-// SW Bypass select logic
-////////////////////////////////////////
-prim_mubi_pkg::mubi4_t io_clk_byp_req;
-
-assign io_clk_byp_req = prim_mubi_pkg::mubi4_test_true_strict( all_clk_byp_req_i ) ?
- prim_mubi_pkg::MuBi4True : io_clk_byp_req_i;
-
-logic all_clk_byp, sys_clk_byp, io_clk_byp, usb_clk_byp, aon_clk_byp;
-
-prim_mubi4_dec u_all_byp_sel ( .mubi_i ( all_clk_byp_req_i ), .mubi_dec_o ( all_clk_byp ) );
-prim_mubi4_dec u_sys_byp_sel ( .mubi_i ( all_clk_byp_req_i ), .mubi_dec_o ( sys_clk_byp ) );
-prim_mubi4_dec u_io_byp_sel ( .mubi_i ( io_clk_byp_req ), .mubi_dec_o ( io_clk_byp ) );
-prim_mubi4_dec u_usb_byp_sel ( .mubi_i ( all_clk_byp_req_i ), .mubi_dec_o ( usb_clk_byp ) );
-prim_mubi4_dec u_aon_byp_sel ( .mubi_i ( all_clk_byp_req_i ), .mubi_dec_o ( aon_clk_byp ) );
-
-// Sync to De-Glitch selects
-logic sw_all_clk_byp, sw_sys_clk_byp, sw_io_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp;
-
-prim_flop_2sync #(
- .Width ( 1 ),
- .ResetValue ( 1'b0 )
-) u_sw_all_clk_byp (
- .clk_i,
- .rst_ni,
- .d_i ( all_clk_byp ),
- .q_o ( sw_all_clk_byp )
-);
-
-prim_flop_2sync #(
- .Width ( 1 ),
- .ResetValue ( 1'b0 )
-) u_sw_sys_clk_byp (
- .clk_i,
- .rst_ni,
- .d_i ( sys_clk_byp ),
- .q_o ( sw_sys_clk_byp )
-);
-
-prim_flop_2sync #(
- .Width ( 1 ),
- .ResetValue ( 1'b0 )
-) u_sw_io_clk_byp (
- .clk_i,
- .rst_ni,
- .d_i ( io_clk_byp ),
- .q_o ( sw_io_clk_byp )
-);
-
-prim_flop_2sync #(
- .Width ( 1 ),
- .ResetValue ( 1'b0 )
-) u_sw_usb_clk_byp (
- .clk_i,
- .rst_ni,
- .d_i ( usb_clk_byp ),
- .q_o ( sw_usb_clk_byp )
-);
-
-prim_flop_2sync #(
- .Width ( 1 ),
- .ResetValue ( 1'b0 )
-) u_sw_aon_clk_byp (
- .clk_i,
- .rst_ni,
- .d_i ( aon_clk_byp ),
- .q_o ( sw_aon_clk_byp )
-);
-
-logic sw_ext_freq_is_96m;
-
-prim_flop_2sync #(
- .Width ( 1 ),
- .ResetValue ( 1'b0 )
-) u_ (
- .clk_i ( ext_clk ),
- .rst_ni ( rst_aon_n ),
- .d_i ( ext_freq_is_96m_i ),
- .q_o ( sw_ext_freq_is_96m )
-);
-
-logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel, ext_freq_is_96m;
-
-assign sys_clk_byp_sel = sw_sys_clk_byp;
-assign io_clk_byp_sel = sw_io_clk_byp;
-assign usb_clk_byp_sel = sw_usb_clk_byp;
-assign aon_clk_byp_sel = sw_aon_clk_byp;
-assign ext_freq_is_96m = sw_ext_freq_is_96m;
-
-
-// External USB & AON clocks genaration
-////////////////////////////////////////
-logic clk_usb_ext_d2, clk_usb_ext;
-
-prim_clock_div #(
- .Divisor( 2 )
-) u_clk_ext_div2_div (
- .clk_i ( ext_clk ),
- .rst_ni ( rst_aon_n ),
- .step_down_req_i( ext_freq_is_96m ),
- .step_down_ack_o ( ),
- .test_en_i ( scan_mode_i ),
- .clk_o ( clk_usb_ext_d2 )
-);
-
-assign clk_usb_ext = clk_usb_ext_d2;
-
-logic clk_usb_ext_d240, clk_aon_ext;
-
-prim_clock_div #(
- .Divisor( 240 )
-) u_clk_usb_div240_div (
- .clk_i ( clk_usb_ext ),
- .rst_ni ( rst_aon_n ),
- .step_down_req_i( 1'b1 ),
- .step_down_ack_o ( ),
- .test_en_i ( scan_mode_i ),
- .clk_o ( clk_usb_ext_d240 )
-);
-
-assign clk_aon_ext = clk_usb_ext_d240;
-
-logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en;
-
-logic rst_clk_osc_n, rst_clk_ext_n;
-assign rst_clk_osc_n = vcaon_pok_i;
-assign rst_clk_ext_n = vcaon_pok_i;
-
-// SYS Clock Bypass Mux
-////////////////////////////////////////
-gfr_clk_mux2 u_clk_src_sys_sel (
- .clk_osc_i ( clk_osc_sys_i ),
- .rst_clk_osc_ni ( rst_clk_osc_n ),
- .clk_ext_i ( ext_clk ),
- .rst_clk_ext_ni ( rst_clk_ext_n ),
- .ext_sel_i ( sys_clk_byp_sel ),
- .clk_osc_en_o ( ),
- .clk_ext_en_o ( sys_clk_byp_en ),
- .clk_o ( clk_src_sys_o )
-);
-
-// IO Clock Bypass Mux
-////////////////////////////////////////
-gfr_clk_mux2 u_clk_src_io_sel (
- .clk_osc_i ( clk_osc_io_i ),
- .rst_clk_osc_ni ( rst_clk_osc_n ),
- .clk_ext_i ( ext_clk ),
- .rst_clk_ext_ni ( rst_clk_ext_n ),
- .ext_sel_i ( io_clk_byp_sel ),
- .clk_osc_en_o ( ),
- .clk_ext_en_o ( io_clk_byp_en ),
- .clk_o ( clk_src_io_o )
-);
-
-// USB Clock Bypass Mux
-////////////////////////////////////////
-gfr_clk_mux2 u_clk_src_usb_sel (
- .clk_osc_i ( clk_osc_usb_i ),
- .rst_clk_osc_ni ( rst_clk_osc_n ),
- .clk_ext_i ( clk_usb_ext ),
- .rst_clk_ext_ni ( rst_clk_ext_n ),
- .ext_sel_i ( usb_clk_byp_sel ),
- .clk_osc_en_o ( ),
- .clk_ext_en_o ( usb_clk_byp_en ),
- .clk_o ( clk_src_usb_o )
-);
-
-// AON Clock Bypass Mux
-////////////////////////////////////////
-gfr_clk_mux2 u_clk_src_aon_sel (
- .clk_osc_i ( clk_osc_aon_i ),
- .rst_clk_osc_ni ( rst_clk_osc_n ),
- .clk_ext_i ( clk_aon_ext ),
- .rst_clk_ext_ni ( rst_clk_ext_n ),
- .ext_sel_i ( aon_clk_byp_sel ),
- .clk_osc_en_o ( ),
- .clk_ext_en_o ( aon_clk_byp_en ),
- .clk_o ( clk_src_aon_o )
-);
-
-assign clk_src_sys_val_o = sys_clk_byp_sel ? sys_clk_byp_en : clk_osc_sys_val_i;
-assign clk_src_io_val_o = io_clk_byp_sel ? io_clk_byp_en : clk_osc_io_val_i;
-assign clk_src_usb_val_o = usb_clk_byp_sel ? usb_clk_byp_en : clk_osc_usb_val_i;
-assign clk_src_aon_val_o = aon_clk_byp_sel ? aon_clk_byp_en : clk_osc_aon_val_i;
-
-logic all_clks_byp_en, only_io_clk_byp_en;
-
-assign all_clks_byp_en = sw_all_clk_byp && sys_clk_byp_en && io_clk_byp_en &&
- usb_clk_byp_en && aon_clk_byp_en;
-
-assign only_io_clk_byp_en = !sw_all_clk_byp && sw_io_clk_byp && io_clk_byp_en;
-
-
-prim_mubi_pkg::mubi4_t all_clk_byp_ack;
-
-assign all_clk_byp_ack = all_clks_byp_en ? prim_mubi_pkg::MuBi4True :
- prim_mubi_pkg::MuBi4False;
-
-prim_mubi4_sync #(
- .ResetValue ( prim_mubi_pkg::MuBi4False )
-) u_all_clk_byp_ack (
- .clk_i,
- .rst_ni,
- .mubi_i ( all_clk_byp_ack ),
- .mubi_o ( all_clk_byp_ack_o )
-);
-
-prim_mubi_pkg::mubi4_t io_clk_byp_ack;
-
-assign io_clk_byp_ack = only_io_clk_byp_en ? prim_mubi_pkg::MuBi4True :
- prim_mubi_pkg::MuBi4False;
-
-prim_mubi4_sync #(
- .ResetValue ( prim_mubi_pkg::MuBi4False )
-) u_io_clk_byp_ack (
- .clk_i,
- .rst_ni,
- .mubi_i ( io_clk_byp_ack ),
- .mubi_o ( io_clk_byp_ack_o )
-);
-
-
-
-
////////////////////////////////////////
// Memories Read-write Margins
////////////////////////////////////////
@@ -289,13 +26,4 @@
assign sprgf_rm_o = 5'h00;
assign sprom_rm_o = 5'h00;
-
-///////////////////////
-// Unused Signals
-///////////////////////
-logic unused_sigs;
-assign unused_sigs = ^{ clk_i, // Used in ASIC implementation
- rst_ni // Used in ASIC implementation
- };
-
endmodule : ast_dft
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
index 4a3fcd3..ddb6e61 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
@@ -11,127 +11,127 @@
package ast_pkg;
- // Alerts
- parameter int unsigned NumAlerts = 13;
- parameter int unsigned NumIoRails = 2;
- parameter int unsigned AsSel = 0;
- parameter int unsigned CgSel = 1;
- parameter int unsigned GdSel = 2;
- parameter int unsigned TsHiSel = 3;
- parameter int unsigned TsLoSel = 4;
- parameter int unsigned FlaSel = 5;
- parameter int unsigned OtpSel = 6;
- parameter int unsigned Ot0Sel = 7;
- parameter int unsigned Ot1Sel = 8;
- parameter int unsigned Ot2Sel = 9;
- parameter int unsigned Ot3Sel = 10;
- parameter int unsigned Ot4Sel = 11;
- parameter int unsigned Ot5Sel = 12;
- //
- parameter int unsigned EntropyStreams = 4;
- parameter int unsigned AdcChannels = 2;
- parameter int unsigned AdcDataWidth = 10;
- parameter int unsigned UsbCalibWidth = 20;
- parameter int unsigned Ast2PadOutWidth = 9;
- parameter int unsigned Pad2AstInWidth = 7;
+// Alerts
+parameter int unsigned NumAlerts = 13;
+parameter int unsigned NumIoRails = 2;
+parameter int unsigned AsSel = 0;
+parameter int unsigned CgSel = 1;
+parameter int unsigned GdSel = 2;
+parameter int unsigned TsHiSel = 3;
+parameter int unsigned TsLoSel = 4;
+parameter int unsigned FlaSel = 5;
+parameter int unsigned OtpSel = 6;
+parameter int unsigned Ot0Sel = 7;
+parameter int unsigned Ot1Sel = 8;
+parameter int unsigned Ot2Sel = 9;
+parameter int unsigned Ot3Sel = 10;
+parameter int unsigned Ot4Sel = 11;
+parameter int unsigned Ot5Sel = 12;
+//
+parameter int unsigned EntropyStreams = 4;
+parameter int unsigned AdcChannels = 2;
+parameter int unsigned AdcDataWidth = 10;
+parameter int unsigned UsbCalibWidth = 20;
+parameter int unsigned Ast2PadOutWidth = 9;
+parameter int unsigned Pad2AstInWidth = 7;
- // These LFSR parameters have been generated with
- // $ ./util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
- parameter int LfsrWidth = 64;
- typedef logic [LfsrWidth-1:0] lfsr_seed_t;
- typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
- parameter lfsr_seed_t RndCnstLfsrSeedDefault = 64'h22d326255bd24320;
- parameter lfsr_perm_t RndCnstLfsrPermDefault = {
- 128'h16108c9f9008aa37e5118d1ec1df64a7,
- 256'h24f3f1b73537f42d38383ee8f897286df81d49ab54b6bbbb666cbd1a16c41252
- };
+// These LFSR parameters have been generated with
+// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 691876113 --prefix ""
+parameter int LfsrWidth = 64;
+typedef logic [LfsrWidth-1:0] lfsr_seed_t;
+typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t;
+parameter lfsr_seed_t RndCnstLfsrSeedDefault = 64'h22d326255bd24320;
+parameter lfsr_perm_t RndCnstLfsrPermDefault = {
+ 128'h16108c9f9008aa37e5118d1ec1df64a7,
+ 256'h24f3f1b73537f42d38383ee8f897286df81d49ab54b6bbbb666cbd1a16c41252
+};
- // Memories Read-Write Margin Interface
- typedef struct packed {
- logic marg_en_a;
- logic [4-1:0] marg_a;
- logic marg_en_b;
- logic [4-1:0] marg_b;
- } dpm_rm_t;
+// Memories Read-Write Margin Interface
+typedef struct packed {
+ logic marg_en_a;
+ logic [4-1:0] marg_a;
+ logic marg_en_b;
+ logic [4-1:0] marg_b;
+} dpm_rm_t;
- typedef struct packed {
- logic marg_en;
- logic [4-1:0] marg;
- } spm_rm_t;
+typedef struct packed {
+ logic marg_en;
+ logic [4-1:0] marg;
+} spm_rm_t;
- // ADC Interface
- typedef struct packed {
- logic [AdcChannels-1:0] channel_sel;
- logic pd;
- } adc_ast_req_t;
+// ADC Interface
+typedef struct packed {
+ logic [AdcChannels-1:0] channel_sel;
+ logic pd;
+} adc_ast_req_t;
- typedef struct packed {
- logic [AdcDataWidth-1:0] data;
- logic data_valid;
- } adc_ast_rsp_t;
+typedef struct packed {
+ logic [AdcDataWidth-1:0] data;
+ logic data_valid;
+} adc_ast_rsp_t;
- // Analog Signal
+// Analog Signal
`ifdef ANALOGSIM
- typedef real awire_t;
+typedef real awire_t;
`else
- typedef logic awire_t;
+typedef logic awire_t;
`endif
- // Clock & Resets Interface
- typedef struct packed {
- logic clk_sys;
- logic clk_io;
- logic clk_usb;
- logic clk_aon;
- } ast_clks_t;
+// Clock & Resets Interface
+typedef struct packed {
+ logic clk_sys;
+ logic clk_io;
+ logic clk_usb;
+ logic clk_aon;
+} ast_clks_t;
- typedef struct packed {
- logic aon_pok;
- } ast_rst_t;
+typedef struct packed {
+ logic aon_pok;
+} ast_rst_t;
- parameter ast_rst_t AST_RST_DEFAULT = '{
- aon_pok: 1'b1
- };
+parameter ast_rst_t AST_RST_DEFAULT = '{
+ aon_pok: 1'b1
+};
- typedef struct packed {
- logic [NumIoRails-1:0] io_pok;
- } ast_status_t;
+typedef struct packed {
+ logic [NumIoRails-1:0] io_pok;
+} ast_status_t;
- typedef struct packed {
- logic aon_pok;
- logic vcc_pok;
- logic main_pok;
- logic [NumIoRails-1:0] io_pok;
- } ast_pwst_t;
+typedef struct packed {
+ logic aon_pok;
+ logic vcc_pok;
+ logic main_pok;
+ logic [NumIoRails-1:0] io_pok;
+} ast_pwst_t;
- // Alerts Interface
- typedef struct packed {
- logic p;
- logic n;
- } ast_dif_t;
+// Alerts Interface
+typedef struct packed {
+ logic p;
+ logic n;
+} ast_dif_t;
- typedef struct packed {
- ast_dif_t [NumAlerts-1:0] alerts;
- } ast_alert_req_t;
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts;
+} ast_alert_req_t;
- typedef struct packed {
- ast_dif_t [NumAlerts-1:0] alerts_ack;
- ast_dif_t [NumAlerts-1:0] alerts_trig;
- } ast_alert_rsp_t;
+typedef struct packed {
+ ast_dif_t [NumAlerts-1:0] alerts_ack;
+ ast_dif_t [NumAlerts-1:0] alerts_trig;
+} ast_alert_rsp_t;
- // Ack mode enumerations
- typedef enum logic {
- ImmAck = 0,
- SwAck = 1
- } ast_ack_mode_e;
+// Ack mode enumerations
+typedef enum logic {
+ ImmAck = 0,
+ SwAck = 1
+} ast_ack_mode_e;
- // Clocks Oschillator Bypass
- typedef struct packed {
- logic usb;
- logic sys;
- logic io;
- logic aon;
- } clks_osc_byp_t;
+// Clocks Oschillator Bypass
+typedef struct packed {
+ logic usb;
+ logic sys;
+ logic io;
+ logic aon;
+} clks_osc_byp_t;
endpackage // of ast_pkg
`endif // of __AST_PKG_SV
diff --git a/hw/top_earlgrey/ip/ast/rtl/gfr_clk_mux2.sv b/hw/top_earlgrey/ip/ast/rtl/gfr_clk_mux2.sv
index 3afd0fc..66ee89c 100644
--- a/hw/top_earlgrey/ip/ast/rtl/gfr_clk_mux2.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/gfr_clk_mux2.sv
@@ -59,7 +59,6 @@
////////////////////////////////////////
logic clk_ext_sel, clk_ext_aoff;
-
always_ff @( posedge clk_ext_i, negedge rst_clk_ext_ni ) begin
if ( !rst_clk_ext_ni ) begin
clk_ext_sel <= 1'b0;
@@ -91,7 +90,7 @@
prim_clock_gating #(
.NoFpgaGate ( 1'b1)
) u_clk_osc_ckgt (
- .clk_i ( clk_osc_i && rst_clk_osc_ni ),
+ .clk_i ( clk_osc_i ),
.en_i ( clk_osc_en_o ),
.test_en_i ( 1'b0 ),
.clk_o ( clk_osc )
@@ -100,7 +99,7 @@
prim_clock_gating #(
.NoFpgaGate ( 1'b1)
) u_clk_byp_ckgt (
- .clk_i ( clk_ext_i && rst_clk_ext_ni ),
+ .clk_i ( clk_ext_i ),
.en_i ( clk_ext_en_o ),
.test_en_i ( 1'b0 ),
.clk_o ( clk_ext )
diff --git a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
index d4b5843..ca993d6 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
@@ -22,6 +22,7 @@
input scan_mode_i, // Scan Mode
output logic vcaon_pok_h_o, // VCAON (1.1v) Exist @3.3v
output logic main_pwr_dly_o, // For modeling only.
+ output logic deep_sleep_h_o, // Deep Sleep (main regulator & switch are off) @3.3v
output logic flash_power_down_h_o, //
output logic flash_power_ready_h_o, //
output logic [1:0] otp_power_seq_h_o // MMR0,24 masked by PDM, out (VCC)
@@ -104,6 +105,12 @@
///////////////////////////////////////
+// Deep Sleep Indication
+///////////////////////////////////////
+assign deep_sleep_h_o = !(main_pd_h_ni && vcmain_pok_o_h_i);
+
+
+///////////////////////////////////////
// Flash
///////////////////////////////////////
assign flash_power_down_h_o = scan_mode_i || !(main_pd_h_ni && vcmain_pok_o_h_i);
