[spi_device] Let readsram sends Sram Req

To make mailbox crossing logic simpler, let SRAM request from readsram
go out to DPSRAM even the operation is not permitted (readbuffer while
in PassThrough)

In order to block the SRAM request, the logic needs:

1. readcmd to hold fifo pop while not in mailbox as FIFO is empty
2. strb in readsram should be reset prior to move to StActive. When the
   address crosses the mailbox (readbuf -> mailbox), the strb is always
   0. strb in the current version latches `current_address_i` when first
   SRAM request sends out to DPSRAM and is incremented at every byte
   being pushed to FIFO.
3. `addr_in_mailbox` should be latched then be used to block the FIFO
   pop. at the last byte of the readbuf, the addr_in_mailbox is already
   high as it sees `addr_d` to check the mailbox region.

So, to make logic simpler, I decided to let request out and sends the
Readbuf data while not in mailbox (in Passthrough mode). The logic will
be blocked by `mailbox_assumed_o` signal at the spi_device top.

To do this, `mailbox_assumed_o` is also revised to set at every byte
while in the mailbox, and to clear if not in the mailbox region.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
2 files changed
tree: 66fffd00b08d31ca62d9e7f42d21c6879980d387
  1. .github/
  2. ci/
  3. doc/
  4. hw/
  5. rules/
  6. site/
  7. sw/
  8. test/
  9. third_party/
  10. util/
  11. .bazelignore
  12. .bazelrc
  13. .bazelversion
  14. .clang-format
  15. .dockerignore
  16. .flake8
  17. .gitignore
  18. .style.yapf
  19. .svlint.toml
  20. .svls.toml
  21. _index.md
  22. apt-requirements.txt
  23. azure-pipelines.yml
  24. bazelisk.sh
  25. BUILD.bazel
  26. check_tool_requirements.core
  27. CLA
  28. COMMITTERS
  29. CONTRIBUTING.md
  30. LICENSE
  31. meson-config.txt
  32. meson.build
  33. meson_init.sh
  34. meson_options.txt
  35. python-requirements.txt
  36. README.md
  37. tool_requirements.py
  38. topgen-reg-only.core
  39. topgen.core
  40. WORKSPACE
  41. yum-requirements.txt
README.md

OpenTitan

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About the project

OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.

About this repository

This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.

Documentation

The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.

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Have a look at [CONTRIBUTING]({{< relref “CONTRIBUTING.md” >}}) and our documentation on project organization and processes for guidelines on how to contribute code to this repository.

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