[prim] Update fifo behavior during reset

Address #4260

Signed-off-by: Timothy Chen <timothytim@google.com>

[prim] Minor fifo updates

Signed-off-by: Timothy Chen <timothytim@google.com>

[prim] minor update

Signed-off-by: Timothy Chen <timothytim@google.com>

[flash_ctrl] fixes to flash for prim_fifo updates

Signed-off-by: Timothy Chen <timothytim@google.com>

[flash_ctrl] Auto generate files

Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index 61fb8fd..692bcca 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -96,6 +96,7 @@
   logic [BusWidth-1:0]  rd_fifo_wdata;
   logic [BusWidth-1:0]  rd_fifo_rdata;
   logic [FifoDepthW-1:0] rd_fifo_depth;
+  logic                 rd_fifo_full;
 
   // Program Control Connections
   logic prog_flash_req;
@@ -526,6 +527,7 @@
     .wvalid_i(rd_fifo_wen),
     .wready_o(rd_fifo_wready),
     .wdata_i (rd_fifo_wdata),
+    .full_o  (rd_fifo_full),
     .depth_o (rd_fifo_depth),
     .rvalid_o(rd_fifo_rvalid),
     .rready_i(rd_fifo_rready),
@@ -718,7 +720,7 @@
   assign hw2reg.op_status.done.de    = sw_ctrl_done;
   assign hw2reg.op_status.err.d      = 1'b1;
   assign hw2reg.op_status.err.de     = sw_ctrl_err;
-  assign hw2reg.status.rd_full.d     = ~rd_fifo_wready;
+  assign hw2reg.status.rd_full.d     = rd_fifo_full;
   assign hw2reg.status.rd_full.de    = sw_sel;
   assign hw2reg.status.rd_empty.d    = ~rd_fifo_rvalid;
   assign hw2reg.status.rd_empty.de   = sw_sel;
@@ -784,7 +786,7 @@
 
   assign intr_src = { ~prog_fifo_rvalid,
                       reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
-                      ~rd_fifo_wready,
+                      rd_fifo_full,
                       reg2hw.fifo_lvl.rd.q == rd_fifo_depth
                     };
 
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 2f16346..10a3970 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -96,6 +96,7 @@
   logic [BusWidth-1:0]  rd_fifo_wdata;
   logic [BusWidth-1:0]  rd_fifo_rdata;
   logic [FifoDepthW-1:0] rd_fifo_depth;
+  logic                 rd_fifo_full;
 
   // Program Control Connections
   logic prog_flash_req;
@@ -526,6 +527,7 @@
     .wvalid_i(rd_fifo_wen),
     .wready_o(rd_fifo_wready),
     .wdata_i (rd_fifo_wdata),
+    .full_o  (rd_fifo_full),
     .depth_o (rd_fifo_depth),
     .rvalid_o(rd_fifo_rvalid),
     .rready_i(rd_fifo_rready),
@@ -719,7 +721,7 @@
   assign hw2reg.op_status.done.de    = sw_ctrl_done;
   assign hw2reg.op_status.err.d      = 1'b1;
   assign hw2reg.op_status.err.de     = sw_ctrl_err;
-  assign hw2reg.status.rd_full.d     = ~rd_fifo_wready;
+  assign hw2reg.status.rd_full.d     = rd_fifo_full;
   assign hw2reg.status.rd_full.de    = sw_sel;
   assign hw2reg.status.rd_empty.d    = ~rd_fifo_rvalid;
   assign hw2reg.status.rd_empty.de   = sw_sel;
@@ -785,7 +787,7 @@
 
   assign intr_src = { ~prog_fifo_rvalid,
                       reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
-                      ~rd_fifo_wready,
+                      rd_fifo_full,
                       reg2hw.fifo_lvl.rd.q == rd_fifo_depth
                     };
 
diff --git a/hw/ip/prim/rtl/prim_fifo_sync.sv b/hw/ip/prim/rtl/prim_fifo_sync.sv
index af559ac..77b8230 100644
--- a/hw/ip/prim/rtl/prim_fifo_sync.sv
+++ b/hw/ip/prim/rtl/prim_fifo_sync.sv
@@ -27,9 +27,11 @@
   input                   rready_i,
   output  [Width-1:0]     rdata_o,
   // occupancy
+  output                  full_o,
   output  [DepthW-1:0]    depth_o
 );
 
+
   // FIFO is in complete passthrough mode
   if (Depth == 0) begin : gen_passthru_fifo
     `ASSERT_INIT(paramCheckPass, Pass == 1)
@@ -42,6 +44,7 @@
 
     // host facing
     assign wready_o = rready_i;
+    assign full_o = rready_i;
 
     // this avoids lint warnings
     logic unused_clr;
@@ -56,6 +59,16 @@
     logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr;
     logic                 fifo_incr_wptr, fifo_incr_rptr, fifo_empty;
 
+    // module under reset flag
+    logic under_rst;
+    always_ff @(posedge clk_i or negedge rst_ni) begin
+      if (!rst_ni) begin
+        under_rst <= 1'b1;
+      end else if (under_rst) begin
+        under_rst <= ~under_rst;
+      end
+    end
+
     // create the write and read pointers
     logic  full, empty;
     logic  wptr_msb;
@@ -71,11 +84,15 @@
                      (wptr_msb == rptr_msb) ? DepthW'(wptr_value) - DepthW'(rptr_value) :
                      (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_value)) ;
 
-    assign fifo_incr_wptr = wvalid_i & wready_o;
-    assign fifo_incr_rptr = rvalid_o & rready_i;
+    assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
+    assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
 
-    assign wready_o = ~full;
-    assign rvalid_o = ~empty;
+    // full and not ready for write are two different concepts.
+    // The latter can be '0' when under reset, while the former is an indication that no more
+    // entries can be written.
+    assign wready_o = ~full & ~under_rst;
+    assign full_o   = full;
+    assign rvalid_o = ~empty & ~under_rst;
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 666c4be..564d255 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -102,6 +102,7 @@
   logic [BusWidth-1:0]  rd_fifo_wdata;
   logic [BusWidth-1:0]  rd_fifo_rdata;
   logic [FifoDepthW-1:0] rd_fifo_depth;
+  logic                 rd_fifo_full;
 
   // Program Control Connections
   logic prog_flash_req;
@@ -532,6 +533,7 @@
     .wvalid_i(rd_fifo_wen),
     .wready_o(rd_fifo_wready),
     .wdata_i (rd_fifo_wdata),
+    .full_o  (rd_fifo_full),
     .depth_o (rd_fifo_depth),
     .rvalid_o(rd_fifo_rvalid),
     .rready_i(rd_fifo_rready),
@@ -725,7 +727,7 @@
   assign hw2reg.op_status.done.de    = sw_ctrl_done;
   assign hw2reg.op_status.err.d      = 1'b1;
   assign hw2reg.op_status.err.de     = sw_ctrl_err;
-  assign hw2reg.status.rd_full.d     = ~rd_fifo_wready;
+  assign hw2reg.status.rd_full.d     = rd_fifo_full;
   assign hw2reg.status.rd_full.de    = sw_sel;
   assign hw2reg.status.rd_empty.d    = ~rd_fifo_rvalid;
   assign hw2reg.status.rd_empty.de   = sw_sel;
@@ -791,7 +793,7 @@
 
   assign intr_src = { ~prog_fifo_rvalid,
                       reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
-                      ~rd_fifo_wready,
+                      rd_fifo_full,
                       reg2hw.fifo_lvl.rd.q == rd_fifo_depth
                     };