commit | 718b2a01aaa5507d590c05fa1fd6576ecc131443 | [log] [tgz] |
---|---|---|
author | Guillermo Maturana <maturana@google.com> | Wed Oct 13 11:44:47 2021 -0700 |
committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Tue Oct 26 12:27:24 2021 -0700 |
tree | e958c4cdf96292177a3e755d5ffdbb41a6c158c9 | |
parent | a5bc6b3f3c45969247aa7dc5ba5ded0715994186 [diff] |
[dv/asic] Create main power glitch test Add interface that drives some AST inputs tied to 1, including vcmain_supp_i and vcaon_supp_i. Create C code to handle two resets, the second being due to the power glitch generated by the DV code in response to the `core_sleeping` rising because of a wait_for_interrupt instruction. Signed-off-by: Guillermo Maturana <maturana@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.
Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).