[clkmgr] Allow multiple hint clocks in a block
There are several parts to this patch, which all have to be done at
once (because the design is broken if you just do some of them).
1. Rename the hints in hint_names_e to include the clock name as
well as the endpoint. This is needed because the "otbn" endpoint
has two different clocks with hints, which need different enum
entries.
2. Also, move the code that chooses these hint names to a method on
the TypedClocks class, so that other code can use it too and be
guaranteed to get the same results.
3. Use this code to determine the iteration order when connecting up
idle signals in merge.py. This (finally!) lets us remove the hack
that we were using to ensure each block only contributed one idle
signal.
4. Add a new "idle_otp_o" signal to OTBN. Wire it up properly and
add placeholder documentation stubs.
5. Teach the clkmgr DV code about the new clock. This is slightly
more work than "just add another entry to the list" because the
new output clock has io_div4 as a source clock, rather than main,
which was used for all the others. (Guillermo helped with the
changes here).
Co-authored-by: Guillermo Maturana <maturana@google.com>
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/util/topgen.py b/util/topgen.py
index 00e2f17..be90d55 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -405,13 +405,8 @@
clocks = top['clocks']
assert isinstance(clocks, Clocks)
- by_type = clocks.typed_clocks()
-
- # The names of endpoints that use one or more sw hint clocks (clkmgr has an
- # "idle" feedback signal from each), in ascending order.
- hint_blocks = sorted(set(ep_name
- for sig in by_type.hint_clks.values()
- for ep_name, ep_port in sig.endpoints))
+ typed_clocks = clocks.typed_clocks()
+ hint_names = typed_clocks.hint_names()
for idx, tpl in enumerate(tpls):
out = ""
@@ -419,13 +414,14 @@
tpl = Template(fin.read())
try:
out = tpl.render(cfg=top,
- rg_srcs=by_type.rg_srcs,
- ft_clks=by_type.ft_clks,
- rg_clks=by_type.rg_clks,
- sw_clks=by_type.sw_clks,
- hint_clks=by_type.hint_clks,
+ rg_srcs=typed_clocks.rg_srcs,
+ ft_clks=typed_clocks.ft_clks,
+ rg_clks=typed_clocks.rg_clks,
+ sw_clks=typed_clocks.sw_clks,
+ hint_clks=typed_clocks.hint_clks,
+ all_clks=typed_clocks.all_clocks(),
export_clks=top['exported_clks'],
- hint_blocks=hint_blocks)
+ hint_names=hint_names)
except: # noqa: E722
log.error(exceptions.text_error_template().render())
