Update riscv_compliance to riscv/riscv-compliance@5a978cf Update code from upstream repository https://github.com/riscv/riscv- compliance.git to revision 5a978cfd444d5e640150d46703deda99057b2bbb Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch index 5b55077..7c5015b 100644 --- a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch +++ b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
@@ -1,4 +1,4 @@ -From 12ff08f286e3045323375877017286afc54dcf39 Mon Sep 17 00:00:00 2001 +From e8b82ff045fca264917a7c5539bfcbe8ed22b7a0 Mon Sep 17 00:00:00 2001 From: Greg Chadwick <gac@lowrisc.org> Date: Wed, 15 Apr 2020 15:45:31 +0100 Subject: [PATCH 1/3] Add configurable trap alignment and entry point to p @@ -95,5 +95,5 @@ # increment return address csrr x30, mepc -- -2.26.2 +2.28.0
diff --git a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch index ecd567c..5095736 100644 --- a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch +++ b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
@@ -1,19 +1,19 @@ -From 3cafdf492bf9e29e9349ca44ae448b5d2359cd06 Mon Sep 17 00:00:00 2001 +From 4d25ba90b659be25aaa441e7dfad6eed9c7f4af3 Mon Sep 17 00:00:00 2001 From: Greg Chadwick <gac@lowrisc.org> Date: Wed, 15 Apr 2020 15:44:54 +0100 Subject: [PATCH 2/3] Add OpenTitan target --- Makefile | 6 +- - riscv-target/opentitan/README.md | 160 ++++++++++++++++++ + riscv-target/opentitan/README.md | 152 ++++++++++++++++++ riscv-target/opentitan/compliance_io.h | 22 +++ riscv-target/opentitan/compliance_test.h | 35 ++++ - .../opentitan/device/rv32imc/Makefile.include | 79 +++++++++ + .../opentitan/device/rv32imc/Makefile.include | 75 +++++++++ .../opentitan/device/rv32imc/isa.yaml | 49 ++++++ - riscv-target/opentitan/device/rv32imc/main.c | 39 +++++ + riscv-target/opentitan/device/rv32imc/main.c | 32 ++++ .../opentitan/device/rv32imc/platform.yaml | 10 ++ .../opentitan/device/rv32imc/run_rvc_test.S | 85 ++++++++++ - 9 files changed, 484 insertions(+), 1 deletion(-) + 9 files changed, 465 insertions(+), 1 deletion(-) create mode 100644 riscv-target/opentitan/README.md create mode 100644 riscv-target/opentitan/compliance_io.h create mode 100644 riscv-target/opentitan/compliance_test.h @@ -24,7 +24,7 @@ create mode 100644 riscv-target/opentitan/device/rv32imc/run_rvc_test.S diff --git a/Makefile b/Makefile -index 25557c1..27433ed 100644 +index 25557c1..a6fd315 100644 --- a/Makefile +++ b/Makefile @@ -50,6 +50,11 @@ else @@ -32,7 +32,7 @@ JOBS ?= -j8 --max-load=4 endif + ifeq ($(RISCV_TARGET),opentitan) -+ ifeq ($(OT_TARGET),verilator) ++ ifeq ($(OT_TARGET),sim_verilator) + JOBS ?= -j4 + endif + endif @@ -46,10 +46,10 @@ - diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md new file mode 100644 -index 0000000..71baa3c +index 0000000..353a9b3 --- /dev/null +++ b/riscv-target/opentitan/README.md -@@ -0,0 +1,160 @@ +@@ -0,0 +1,152 @@ + +# Overview +The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator. @@ -62,25 +62,19 @@ +```console +$ export RISCV_TARGET=opentitan +$ export RISCV_DEVICE=rv32imc -+$ export OT_TARGET=verilator ++$ export OT_TARGET=sim_verilator +``` + -+To run on FPGA, set the variables below. The `FPGA_UART` variable must be set -+to wherever a valid device is connected. ++To run on FPGA, set the variables below. The `OT_FPGA_UART` variable must be ++set to wherever a valid device is connected. + +```console +$ export RISCV_TARGET=opentitan +$ export RISCV_DEVICE=rv32imc -+$ export OT_TARGET=fpga ++$ export OT_TARGET=fpga_nexysvideo +$ export OT_FPGA_UART=/dev/tty* +``` + -+In addition the UART device must be appropriately configured. -+ -+```console -+$ stty -F $OT_FPGA_UART 230400 raw -+``` -+ +By default, the test assumes there exists a valid Verilator build at +`${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`. +If your Verilator build is at a different location, please set that as well when @@ -91,10 +85,9 @@ +``` + +When running against FPGA, the test assumes the FPGA is already programmed and -+ready to go with spiflash available at -+`${REPO_TOP}/build-bin/sw/host/spiflash/spiflash_export` To quickly get started -+with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start -+guide](https://docs.opentitan.org/doc/ug/quickstart/). ++ready to go with spiflash available at `$BIN_DIR/sw/host/spiflash/spiflash`. ++To quickly get started with a verilator binary or FPGA bitfile, please see the ++[OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/). + +Finally the support software must be built, including the boot_rom when using +the verilator target. @@ -184,7 +177,7 @@ +``` + +## Parallel runs -+When running against the `verilator` target parallel make jobs are used (via ++When running against the `sim_verilator` target parallel make jobs are used (via +passing `-j4` to make internally). Parallel runs can be disabled by passing +`PARALLEL=0` to the `make` command or the `-j` used can be altered with the +`JOBS` argument. @@ -209,132 +202,127 @@ +* I-MISALIGN_JMP-01 +* I-MISALIGN_LDST-01 +* I-FENCE.I-01 -+ diff --git a/riscv-target/opentitan/compliance_io.h b/riscv-target/opentitan/compliance_io.h new file mode 100644 -index 0000000..2774158 +index 0000000..d5d88d4 --- /dev/null +++ b/riscv-target/opentitan/compliance_io.h @@ -0,0 +1,22 @@ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+// RISC-V Compliance IO Test Header File -+ -+ -+#ifndef _COMPLIANCE_IO_H -+#define _COMPLIANCE_IO_H -+ -+//----------------------------------------------------------------------- -+// RV IO Macros (Non functional) -+//----------------------------------------------------------------------- -+ -+#define RVTEST_IO_INIT -+#define RVTEST_IO_WRITE_STR(_SP, _STR) -+#define RVTEST_IO_CHECK() -+#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) -+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) -+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) -+ -+#endif // _COMPLIANCE_IO_H ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// RISC-V Compliance IO Test Header File ++ ++ ++#ifndef _COMPLIANCE_IO_H ++#define _COMPLIANCE_IO_H ++ ++//----------------------------------------------------------------------- ++// RV IO Macros (Non functional) ++//----------------------------------------------------------------------- ++ ++#define RVTEST_IO_INIT ++#define RVTEST_IO_WRITE_STR(_SP, _STR) ++#define RVTEST_IO_CHECK() ++#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) ++#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) ++#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) ++ ++#endif // _COMPLIANCE_IO_H diff --git a/riscv-target/opentitan/compliance_test.h b/riscv-target/opentitan/compliance_test.h new file mode 100644 -index 0000000..978d578 +index 0000000..6a889cf --- /dev/null +++ b/riscv-target/opentitan/compliance_test.h @@ -0,0 +1,35 @@ -+// Copyright lowRISC contributors. -+// Licensed under the Apache License, Version 2.0, see LICENSE for details. -+// SPDX-License-Identifier: Apache-2.0 -+ -+// RISC-V Compliance Test Header File -+ -+#ifndef _COMPLIANCE_TEST_H -+#define _COMPLIANCE_TEST_H -+ -+#include "riscv_test.h" -+ -+//----------------------------------------------------------------------- -+// RV Compliance Macros -+//----------------------------------------------------------------------- -+#define RV_COMPLIANCE_HALT \ -+ j end_rvc_test; \ -+ -+#define RV_COMPLIANCE_RV32M \ -+ RVTEST_RV32M \ -+ -+ -+#define RV_COMPLIANCE_CODE_BEGIN \ -+ RVTEST_CODE_BEGIN \ -+ -+#define RV_COMPLIANCE_CODE_END \ -+ RVTEST_CODE_END \ -+ -+#define RV_COMPLIANCE_DATA_BEGIN \ -+ .section .data; \ -+ RVTEST_DATA_BEGIN \ -+ -+#define RV_COMPLIANCE_DATA_END \ -+ RVTEST_DATA_END \ -+ -+#endif ++// Copyright lowRISC contributors. ++// Licensed under the Apache License, Version 2.0, see LICENSE for details. ++// SPDX-License-Identifier: Apache-2.0 ++ ++// RISC-V Compliance Test Header File ++ ++#ifndef _COMPLIANCE_TEST_H ++#define _COMPLIANCE_TEST_H ++ ++#include "riscv_test.h" ++ ++//----------------------------------------------------------------------- ++// RV Compliance Macros ++//----------------------------------------------------------------------- ++#define RV_COMPLIANCE_HALT \ ++ j end_rvc_test; \ ++ ++#define RV_COMPLIANCE_RV32M \ ++ RVTEST_RV32M \ ++ ++ ++#define RV_COMPLIANCE_CODE_BEGIN \ ++ RVTEST_CODE_BEGIN \ ++ ++#define RV_COMPLIANCE_CODE_END \ ++ RVTEST_CODE_END \ ++ ++#define RV_COMPLIANCE_DATA_BEGIN \ ++ .section .data; \ ++ RVTEST_DATA_BEGIN \ ++ ++#define RV_COMPLIANCE_DATA_END \ ++ RVTEST_DATA_END \ ++ ++#endif diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include new file mode 100644 -index 0000000..dba8732 +index 0000000..a44e0c3 --- /dev/null +++ b/riscv-target/opentitan/device/rv32imc/Makefile.include -@@ -0,0 +1,79 @@ +@@ -0,0 +1,75 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +OPENTITAN = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc -+OT_SW = $(ROOTDIR)/../../device -+OT_ROOT = $(OT_SW)/../../ ++OT_ROOT ?= $(ROOTDIR)/../../../ ++OT_SW = $(OT_ROOT)/sw/device +OT_BIN ?= $(OT_ROOT)/build-bin -+OT_BUILD = $(OT_ROOT)/build-out +OT_TOOLS ?= /tools/riscv/bin +OT_FPGA_UART ?= -+OT_TARGET ?= fpga ++OT_TARGET ?= fpga_nexysvideo +LDSCRIPT = $(OT_ROOT)/sw/device/exts/common/flash_link.ld +DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DRVTEST_ENTRY=_rvc_start -DTRAPALIGN=8 +TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator + -+ifeq ($(OT_TARGET),fpga) -+ CARG = -+ MAKEARG = -+ PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_BIN)/sw/host/spiflash/spiflash \ -+ --test_bin $(<).bin -+ OT_SW_TARGET = fpga_nexysvideo -+else -+ CARG = -DSIMULATION=1 -+ MAKEARG = SIM=1 -+ # Verilator can be run in parallel mode so alter log output to prepend with -+ # test name, also increase uart_timeout as with parallel runs on CI individual -+ # test execution can take greater than 60 seconds. -+ PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(<) \ -+ --rom_bin $(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf \ -+ --log-cli-format "$(notdir $(basename $(<))): %(message)s" --log-cli-level DEBUG \ -+ --uart_timeout 240 -+ OT_SW_TARGET = sim_verilator -+endif -+ -+COMPLIANCE_LIB_EXPORT = sw/device/riscv_compliance_support/riscv_compliance_support_export_$(OT_SW_TARGET) -+COMPLIANCE_LIB = ot_riscv_compliance_support_$(OT_SW_TARGET) ++COMPLIANCE_LIB_EXPORT = sw/device/riscv_compliance_support/riscv_compliance_support_export_$(OT_TARGET) ++COMPLIANCE_LIB = ot_riscv_compliance_support_$(OT_TARGET) + +# The run target recipe does the following things: +# Invoke pytest to run the test +# Parse the resulting log for the output signatures +# Convert all signatures to lower case since the reference is in all lower case -+RUN_TARGET=\ -+ pytest -s -v $(OT_ROOT)/test/systemtest/functional_$(OT_TARGET)_test.py \ -+ $(PYTEST_OPT) \ -+ --log $(<).uart.log; \ -+ grep -o 'SIG: [a-zA-Z0-9_]*' $(<).uart.log | sed 's/SIG: //' \ -+ > $(*).signature.temp.output; \ -+ tr '[:upper:]' '[:lower:]' < $(*).signature.temp.output > $(*).signature.output; -+ ++ifeq ($(OT_TARGET),sim_verilator) ++ MAKEARG = SIM=1 ++ CARG = -DSIMULATION=1 ++ RUN_TARGET = \ ++ $(TARGET_SIM) \ ++ --meminit="rom,$(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf" \ ++ --meminit="flash,$(<)" \ ++ +UARTDPI_LOG_uart0="$(*).uart.log" > $@ 2>&1 \ ++ && sed -e 's/^/[UART $(shell basename $(*))] /' "$(*).uart.log" $(REDIR) \ ++ && grep -o 'SIG: [a-zA-Z0-9_]*' "$(*).uart.log" \ ++ | sed 's/SIG: //' > $(*).signature.output ++else ifeq ($(OT_TARGET),fpga_nexysvideo) ++ MAKEARG = ++ CARG = ++ RUN_TARGET = \ ++ ( test -e "$(OT_FPGA_UART)" || ( echo "UART device '$(OT_FPGA_UART)' not available. Set OT_FPGA_UART." >&2 && exit 1 ) ) \ ++ && echo "Writing '$(<).bin' to device." \ ++ && $(OT_BIN)/sw/host/spiflash/spiflash --input="$(<).bin" \ ++ && stty -F "$(OT_FPGA_UART)" speed 230400 cs8 -cstopb -parenb \ ++ && grep -o 'SIG: [a-zA-Z0-9_]*' "$(OT_FPGA_UART)" \ ++ | sed 's/SIG: //' > $(*).signature.output ++else ++ $(error Unsupported target $(OT_TARGET)) ++endif + +RISCV_PREFIX ?= ${OT_TOOLS}/riscv32-unknown-elf- +RISCV_GCC ?= ${OT_TOOLS}/riscv32-unknown-elf-gcc @@ -421,10 +409,10 @@ + implemented: true diff --git a/riscv-target/opentitan/device/rv32imc/main.c b/riscv-target/opentitan/device/rv32imc/main.c new file mode 100644 -index 0000000..4691578 +index 0000000..ad5ca31 --- /dev/null +++ b/riscv-target/opentitan/device/rv32imc/main.c -@@ -0,0 +1,39 @@ +@@ -0,0 +1,32 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 @@ -435,6 +423,7 @@ + +#include "sw/device/lib/uart.h" +#include "sw/device/lib/arch/device.h" ++#include "sw/device/lib/base/print.h" +#include "sw/device/lib/common.h" + +extern void run_rvc_test(void); @@ -454,14 +443,6 @@ + base_printf("SIG: %08x\r\n", REG32(begin_signature + i)); + } + -+ base_printf("PASS!\r\n"); -+ -+ // The "End" string here is a workaround to pytest console parsing. -+ // Without additional characters, the "\n" from above is not always -+ // detected, and this causes pytest to register the test as a false failure. -+ // This needs to be debugged further to see if it's a setup or hw issue. -+ base_printf("End"); -+ + return 0; +} diff --git a/riscv-target/opentitan/device/rv32imc/platform.yaml b/riscv-target/opentitan/device/rv32imc/platform.yaml @@ -572,5 +553,5 @@ + // jump to the handler from the OT library + j crt_interrupt_vector -- -2.26.2 +2.28.0
diff --git a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch index d9439cb..69ef293 100644 --- a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch +++ b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
@@ -1,4 +1,4 @@ -From 869ad7202f4551ae75440b8e34d8aa37f4b3f4cf Mon Sep 17 00:00:00 2001 +From 7ada51301b9ef34982d8a05bdcc63d98e162243a Mon Sep 17 00:00:00 2001 From: Greg Chadwick <gac@lowrisc.org> Date: Wed, 15 Apr 2020 18:39:08 +0100 Subject: [PATCH 3/3] Remove tests that do not pass on OpenTitan @@ -33,5 +33,5 @@ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) -- -2.26.2 +2.28.0