| commit | 708c202d1cc1fd5844dfd4a0787858c88987d72c | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Tue Apr 06 09:20:37 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Wed Apr 07 13:12:01 2021 +0100 |
| tree | 5355ae33c9df4c4f8aa9ca524a02c0f1ab423ba5 | |
| parent | f6e68c271698feb6fe3d0f63dca3ef34c95eb45a [diff] |
[otp_ctrl,lint] Write a range select explicitly, not using >> The right shift in otp_ctrl_part_buf.sv was being used to convert an (N+1)-bit long byte address (that we happen to know is even) to an N-bit long halfword address. The right shift, combined with Verilog's truncation rules, mean that it functioned as a range select to grab just the bottom N bits. Verilator complains about such things (it treats the assignment of N+1 bits to an N-bit variable as a width mismatch). Here, it's easy to sort out: just write the range select explicitly. We have an equivalent situation in otp_ctrl_part_unbuf.sv (although this was inlining the right shift into the branches of a conditional expression). Make this match too. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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