Updated sysrst_ctrl_testplan
Signed-off-by: Madhuri Patel <madhuri.patel@ensilica.com>
diff --git a/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.hjson b/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.hjson
index 9aab787..871bcc1 100644
--- a/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.hjson
+++ b/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.hjson
@@ -5,35 +5,209 @@
name: "sysrst_ctrl"
// TODO: remove the common testplans if not applicable
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
- "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
+ "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson"]
testpoints: [
{
name: smoke
desc: '''
- Smoke test accessing a major datapath within the sysrst_ctrl.
+ Verify end to end data transfer in normal operation mode.
- **Stimulus**:
- - TBD
-
- **Checks**:
- - TBD
+ * Write a random data to the input keys.
+ * Read the data at the output pins and compare it with the input data.
'''
milestone: V1
tests: ["sysrst_ctrl_smoke"]
}
+
{
- name: feature1
- desc: '''Add more test entries here like above.'''
+ name: input_output_inverted
+ desc: '''
+ Verify end to end data transfer with inverted input and inverted output.
+
+ * Write a random data to the input keys.
+ * Configure KEY_INVERT_CTL register to invert the input.
+ * Read the data at the output pins and compare it with the input data.
+ * Configure KEY_INVERT_CTL register to invert the output.
+ * Check if the output is inverted form of input pins.
+ '''
milestone: V1
- tests: []
+ tests: ["sysrst_ctrl_in_out_inverted"]
+ }
+
+ {
+ name: combo_detect_ec_rst
+ desc: '''
+ Verify the combo detection with ec_rst action.
+
+ * Trigger the input keys by configuring COM_SEL_CTL_0 register.
+ * Set the combo duration via the COM_DET_CTL_0 register.
+ * Select the action to be taken by configuring COM_OUT_CTL_0 register.
+ * Set the pulse width via EC_RST_CTL register only to raise ec_rst action.
+ * Read the COMBO_INTR_STATUS register to check if the interrupt is raised and
+ clear the interrupt.
+ * NOTE: This is a directed test with no random values for V1 milestone,
+ further this test will be randomized.
+ '''
+ milestone: V1
+ tests: ["sysrst_ctrl_combo_detect_ec_rst"]
+ }
+
+ {
+ name: combo_detect
+ desc: '''
+ Verify the combo detection with random action.
+
+ * Trigger the input keys by configuring COM_SEL_CTL_0 register.
+ * Set the random combo duration via the COM_DET_CTL_0 register.
+ * Randomly select the action to be taken by configuring COM_OUT_CTL_0 register.
+ * Set the pulse width via EC_RST_CTL register.
+ * Read the COMBO_INTR_STATUS register to check if the interrupt is raised and clear the
+ interrupt.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_combo_detect"]
+ }
+
+ {
+ name: auto_block_key_outputs
+ desc: '''
+ Verify the auto block key output feature.
+
+ * Trigger the input keys combo.
+ * Set the debounce timer value in AUTO_BLOCK_DEBOUNCE_CTL register.
+ * Select the output override value by configuring AUTO_BLOCK_OUT_CTL register.
+ * Check whether the input keys stays low for the selected debounce time.
+ * Read the AUTO_BLOCK_OUT_CTL register to check if the output key is overridden.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_auto_blk_key_output"]
+ }
+
+ {
+ name: keyboard_input_triggered_interrupt
+ desc: '''
+ Verify the keyboard and input triggered interrupt feature by detecting the edge
+ transitions on input pins.
+
+ * Set the input signals and edge transition by configuring KEY_INTR_CTL register.
+ * Set the debounce timer value via KEY_INTR_DEBOUNCE_CTL register.
+ * Read the KEY_INTR_STATUS register to check if the interrupt caused and
+ clear the interrupt.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_edge_detect"]
+ }
+
+ {
+ name: pin_output_keyboard_inversion_control
+ desc: '''
+ Verify the keyboard inversion feature by override logic.
+
+ * Select the output signals to override via PIN_OUT_CTL register.
+ * Allow the output signals to override the value via PIN_ALLOWED_CTL register.
+ * Set the override value to the output signal via PIN_OUT_VALUE register.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_override_test"]
+ }
+
+ {
+ name: pin_input_value_accessibility
+ desc: '''
+ Verify the pin input value accessibilty.
+
+ * Trigger the key[0,1,2], ac_present_in, pwrb_in, ec_rst_in_l input pins with random values.
+ * Read the PIN_IN_VALUE register and check if the read value is same as input value.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_pin_access_test"]
+ }
+
+ {
+ name: ec_power_on_reset
+ desc: '''
+ Verify the EC and power on reset.
+
+ * Enable the override value by writing to PIN_ALLOWED_CTL.EC_RST_L_1
+ and PIN_OUT_CTL.EC_RST_L register.
+ * Make sure ec_rst_out_l is asserted even after opentitan reset is released.
+ * Set PIN_OUT_CTL.EC_RST_L to 0 to release the ec_rst_out_l reset.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_ec_pwr_on_rst"]
+ }
+
+ {
+ name: flash_write_protect_output
+ desc: '''
+ Verify the flash write protect.
+
+ * Make sure flash_wp_out_l signal is asserted low by reading PIN_OUT_CTL.flash_wp_l.
+ * Enable the override function by setting PIN_OUT_CTL.FLASH_WP_L to value 1.
+ * Check if flash_wp_out_l is released.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_flash_wr_prot_out"]
+ }
+
+ {
+ name: ultra_low_power_test
+ desc: '''
+ Verify the ultra low power feature.
+
+ * Configure ULP_AC_DEBOUNCE_CTL, ULP_LID_DEBOUNCE_CTL and
+ ULP_PWRB_DEBOUNCE_CTL register to set the debounce timer value.
+ * Disable the bus clock to check detection logic works in sleep mode.
+ * Trigger the ac_present_i, lid_open_in, ec_rst_l_i input keys.
+ * Turn on the bus clock to read the status register.
+ * Read the WKUP_STATUS register to check if the event has occured.
+ * Read the ULP_STATUS register and check if the ultra low power wakeup event is detected.
+ '''
+ milestone: V2
+ tests: ["sysrst_ctrl_ultra_low_pwr"]
}
]
covergroups: [
{
- name: sysrst_ctrl_feature_cg
- desc: '''Describe the functionality covered by this covergroup.'''
+ name: sysrst_ctrl_ec_rst_pulse_width_cg
+ desc: '''
+ Cover the ec_rst_out_l pulse width range from 10-200ms.
+ '''
+ }
+ {
+ name: sysrst_ctrl_key_intr_cg
+ desc: '''
+ Cover the FSM for input key pressed and released.
+ '''
+ }
+ {
+ name: sysrst_ctrl_timerfsm_cg
+ desc: '''
+ Cover the timer based FSM model for different debounce time.
+ '''
+ }
+ {
+ name: sysrst_ctrl_ulpfsm_cg
+ desc: '''
+ Cover the ultra low power fsm model.
+ '''
+ }
+ {
+ name: sysrst_ctrl_combo_detect_action_cg
+ desc: '''
+ Cover all the combo detect actions.
+ '''
+ }
+ {
+ name: sysrst_ctrl_override_values_cg
+ desc: '''
+ Cover the pin override value transition from 0 -> 1 and 1 -> 0.
+ Reference: PIN_OUT_VALUE register.
+ '''
}
]
}
