[otbn] Rename from "error code" to "error bit" in ISS
No functional change, but the name now matches the design a bit
better.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/otbn/dv/otbnsim/sim/alert.py b/hw/ip/otbn/dv/otbnsim/sim/alert.py
index a32ff48..d7b5287 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/alert.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/alert.py
@@ -4,32 +4,32 @@
from typing import Optional
-# A copy of the list of error codes. This also appears in the documentation and
-# otbn_pkg.sv: we should probably be generating them from the hjson every time.
-ERR_CODE_NO_ERROR = 0
-ERR_CODE_BAD_DATA_ADDR = 1 << 0
-ERR_CODE_BAD_INSN_ADDR = 1 << 1
-ERR_CODE_CALL_STACK = 1 << 2
-ERR_CODE_ILLEGAL_INSN = 1 << 3
-ERR_CODE_LOOP = 1 << 4
-ERR_CODE_FATAL_IMEM = 1 << 5
-ERR_CODE_FATAL_DMEM = 1 << 6
-ERR_CODE_FATAL_REG = 1 << 7
+# A copy of the list of bits in the ERR_BITS register. This also appears in the
+# documentation and otbn_pkg.sv: we should probably be generating them from the
+# hjson every time.
+BAD_DATA_ADDR = 1 << 0
+BAD_INSN_ADDR = 1 << 1
+CALL_STACK = 1 << 2
+ILLEGAL_INSN = 1 << 3
+LOOP = 1 << 4
+FATAL_IMEM = 1 << 5
+FATAL_DMEM = 1 << 6
+FATAL_REG = 1 << 7
class Alert:
'''An object describing something the program did wrong
- This maps onto alerts in the implementation. The err_code value is the
+ This maps onto alerts in the implementation. The err_bit value is the
value that should be OR'd into the ERR_BITS external register.
'''
- # Subclasses should override this class field or the error_code method
- err_code = None # type: Optional[int]
+ # Subclasses should override this class field or the error_bit method
+ err_bit = None # type: Optional[int]
- def error_code(self) -> int:
- assert self.err_code is not None
- return self.err_code
+ def error_bit(self) -> int:
+ assert self.err_bit is not None
+ return self.err_bit
class BadAddrError(Alert):
@@ -43,10 +43,8 @@
self.addr = addr
self.what = what
- def error_code(self) -> int:
- return (ERR_CODE_BAD_INSN_ADDR
- if self.operation == 'fetch'
- else ERR_CODE_BAD_DATA_ADDR)
+ def error_bit(self) -> int:
+ return BAD_INSN_ADDR if self.operation == 'fetch' else BAD_DATA_ADDR
def __str__(self) -> str:
return ('Bad {} address of {:#08x}: {}.'
@@ -56,7 +54,7 @@
class LoopError(Alert):
'''Generated when doing something wrong with a LOOP/LOOPI'''
- err_code = ERR_CODE_LOOP
+ err_bit = LOOP
def __init__(self, what: str):
self.what = what
@@ -67,7 +65,7 @@
class IllegalInsnError(Alert):
'''Generated on a bad instruction'''
- err_code = ERR_CODE_ILLEGAL_INSN
+ err_bit = ILLEGAL_INSN
def __init__(self, word: int, msg: str):
self.word = word
@@ -75,3 +73,16 @@
def __str__(self) -> str:
return ('Illegal instruction {:#010x}: {}'.format(self.word, self.msg))
+
+
+class CallStackError(Alert):
+ '''Raised when under- or over-flowing the call stack'''
+
+ err_bit = CALL_STACK
+
+ def __init__(self, is_overflow: bool):
+ self.is_overflow = is_overflow
+
+ def __str__(self) -> str:
+ xflow = 'overflow' if self.is_overflow else 'underflow'
+ return 'Instruction caused {} of x1 call stack.'.format(xflow)
diff --git a/hw/ip/otbn/dv/otbnsim/sim/gpr.py b/hw/ip/otbn/dv/otbnsim/sim/gpr.py
index e70cebb..ea64eb8 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/gpr.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/gpr.py
@@ -4,23 +4,10 @@
from typing import List
-from .alert import Alert, ERR_CODE_CALL_STACK
+from .alert import CallStackError
from .reg import Reg, RegFile
-class CallStackError(Alert):
- '''Raised when under- or over-flowing the call stack'''
-
- err_code = ERR_CODE_CALL_STACK
-
- def __init__(self, is_overflow: bool):
- self.is_overflow = is_overflow
-
- def __str__(self) -> str:
- xflow = 'overflow' if self.is_overflow else 'underflow'
- return 'Instruction caused {} of x1 call stack.'.format(xflow)
-
-
class CallStackReg(Reg):
'''A register used to represent x1'''
diff --git a/hw/ip/otbn/dv/otbnsim/sim/insn.py b/hw/ip/otbn/dv/otbnsim/sim/insn.py
index 2f2cc61..1ba49b2 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/insn.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/insn.py
@@ -4,7 +4,7 @@
from typing import Dict
-from .alert import ERR_CODE_NO_ERROR, LoopError
+from .alert import LoopError
from .flags import FlagReg
from .isa import (DecodeError, OTBNInsn, RV32RegReg, RV32RegImm, RV32ImmShift,
insn_for_mnemonic, logical_byte_shift)
@@ -315,7 +315,7 @@
def execute(self, state: OTBNState) -> None:
# Set INTR_STATE.done and STATUS, reflecting the fact we've stopped.
- state._stop(ERR_CODE_NO_ERROR)
+ state._stop(0)
class LOOP(OTBNInsn):
diff --git a/hw/ip/otbn/dv/otbnsim/sim/state.py b/hw/ip/otbn/dv/otbnsim/sim/state.py
index 077d4ce..7d78084 100644
--- a/hw/ip/otbn/dv/otbnsim/sim/state.py
+++ b/hw/ip/otbn/dv/otbnsim/sim/state.py
@@ -164,7 +164,7 @@
def die(self, alerts: List[Alert]) -> None:
err_bits = 0
for alert in alerts:
- err_bits |= alert.error_code()
+ err_bits |= alert.error_bit()
self._abort()
self._stop(err_bits)
