[i2c, rtl] Lint Fixes
Fixes to Ascent and Verilator errors and warnings
Signed-off-by: Igor Kouznetsov <igor.kouznetsov@wdc.com>
diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
index 7746664..148d67a 100644
--- a/hw/ip/i2c/data/i2c.hjson
+++ b/hw/ip/i2c/data/i2c.hjson
@@ -285,19 +285,19 @@
hwaccess: "hwo"
hwext: "true"
fields: [
- { bits: "5:0"
+ { bits: "6:0"
name: "FMTLVL"
desc: "Current fill level of FMT fifo"
}
- { bits: "21:16"
+ { bits: "22:16"
name: "RXLVL"
desc: "Current fill level of RX fifo"
}
- { bits: "13:8"
+ { bits: "14:8"
name: "TXLVL"
desc: "Current fill level of TX fifo"
}
- { bits: "29:24"
+ { bits: "30:24"
name: "ACQLVL"
desc: "Current fill level of ACQ fifo"
}
diff --git a/hw/ip/i2c/rtl/i2c_core.sv b/hw/ip/i2c/rtl/i2c_core.sv
index abe2d8a..e86ad26 100644
--- a/hw/ip/i2c/rtl/i2c_core.sv
+++ b/hw/ip/i2c/rtl/i2c_core.sv
@@ -240,10 +240,10 @@
always_comb begin
unique case(i2c_fifo_fmtilvl)
- 2'h0: fmt_watermark_d = (fmt_fifo_depth <= 6'd1);
- 2'h1: fmt_watermark_d = (fmt_fifo_depth <= 6'd4);
- 2'h2: fmt_watermark_d = (fmt_fifo_depth <= 6'd8);
- default: fmt_watermark_d = (fmt_fifo_depth <= 6'd16);
+ 2'h0: fmt_watermark_d = (fmt_fifo_depth <= 7'd1);
+ 2'h1: fmt_watermark_d = (fmt_fifo_depth <= 7'd4);
+ 2'h2: fmt_watermark_d = (fmt_fifo_depth <= 7'd8);
+ default: fmt_watermark_d = (fmt_fifo_depth <= 7'd16);
endcase
end
@@ -251,11 +251,11 @@
always_comb begin
unique case(i2c_fifo_rxilvl)
- 3'h0: rx_watermark_d = (rx_fifo_depth >= 6'd1);
- 3'h1: rx_watermark_d = (rx_fifo_depth >= 6'd4);
- 3'h2: rx_watermark_d = (rx_fifo_depth >= 6'd8);
- 3'h3: rx_watermark_d = (rx_fifo_depth >= 6'd16);
- 3'h4: rx_watermark_d = (rx_fifo_depth >= 6'd30);
+ 3'h0: rx_watermark_d = (rx_fifo_depth >= 7'd1);
+ 3'h1: rx_watermark_d = (rx_fifo_depth >= 7'd4);
+ 3'h2: rx_watermark_d = (rx_fifo_depth >= 7'd8);
+ 3'h3: rx_watermark_d = (rx_fifo_depth >= 7'd16);
+ 3'h4: rx_watermark_d = (rx_fifo_depth >= 7'd30);
default: rx_watermark_d = 1'b0;
endcase
end
diff --git a/hw/ip/i2c/rtl/i2c_fsm.sv b/hw/ip/i2c/rtl/i2c_fsm.sv
index 4daf75a..c1a0ca9 100644
--- a/hw/ip/i2c/rtl/i2c_fsm.sv
+++ b/hw/ip/i2c/rtl/i2c_fsm.sv
@@ -18,7 +18,7 @@
input fmt_fifo_rvalid_i, // indicates there is valid data in fmt_fifo
input fmt_fifo_wvalid_i, // indicates data is being put into fmt_fifo
- input [5:0] fmt_fifo_depth_i, // fmt_fifo_depth
+ input [6:0] fmt_fifo_depth_i, // fmt_fifo_depth
output logic fmt_fifo_rready_o, // populates fmt_fifo
input [7:0] fmt_byte_i, // byte in fmt_fifo to be sent to target
input fmt_flag_start_before_i, // issue start before sending byte
@@ -32,7 +32,7 @@
input tx_fifo_rvalid_i, // indicates there is valid data in tx_fifo
input tx_fifo_wvalid_i, // indicates data is being put into tx_fifo
- input [5:0] tx_fifo_depth_i, // tx_fifo_depth
+ input [6:0] tx_fifo_depth_i, // tx_fifo_depth
output logic tx_fifo_rready_o, // populates tx_fifo
input [7:0] tx_fifo_rdata_i, // byte in tx_fifo to be sent to host
@@ -631,7 +631,7 @@
// TransmitAck: target waits for host to ACK transmission
TransmitAck : begin
target_idle_o = 1'b0;
- if (tx_fifo_depth_i == 6'd1 && !tx_fifo_wvalid_i && host_ack) event_tx_empty_o = 1'b1;
+ if (tx_fifo_depth_i == 7'd1 && !tx_fifo_wvalid_i && host_ack) event_tx_empty_o = 1'b1;
if (host_ack && (start_det || stop_det)) event_ack_stop_o = 1'b1;
end
// PopTxFifo: populate tx_fifo
@@ -999,7 +999,7 @@
state_d = ClockStop;
load_tcount = 1'b1;
tcount_sel = tClockStop;
- end else if (fmt_fifo_depth_i == 6'd1 && !fmt_fifo_wvalid_i) begin
+ end else if (fmt_fifo_depth_i == 7'd1 && !fmt_fifo_wvalid_i) begin
state_d = Idle;
load_tcount = 1'b1;
tcount_sel = tNoDelay;
@@ -1122,7 +1122,7 @@
PopTxFifo : begin
if (!target_enable_i) begin
state_d = Idle;
- end else if (tx_fifo_depth_i == 6'd1 && !tx_fifo_wvalid_i) begin
+ end else if (tx_fifo_depth_i == 7'd1 && !tx_fifo_wvalid_i) begin
state_d = StretchTxEmpty;
end else begin
state_d = TransmitWait;
diff --git a/hw/ip/i2c/rtl/i2c_reg_pkg.sv b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
index d6c5b77..78f84c1 100644
--- a/hw/ip/i2c/rtl/i2c_reg_pkg.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
@@ -475,16 +475,16 @@
typedef struct packed {
struct packed {
- logic [5:0] d;
+ logic [6:0] d;
} fmtlvl;
struct packed {
- logic [5:0] d;
+ logic [6:0] d;
} txlvl;
struct packed {
- logic [5:0] d;
+ logic [6:0] d;
} rxlvl;
struct packed {
- logic [5:0] d;
+ logic [6:0] d;
} acqlvl;
} i2c_hw2reg_fifo_status_reg_t;
@@ -542,10 +542,10 @@
// HW -> register type
typedef struct packed {
- i2c_hw2reg_intr_state_reg_t intr_state; // [119:88]
- i2c_hw2reg_status_reg_t status; // [87:78]
- i2c_hw2reg_rdata_reg_t rdata; // [77:70]
- i2c_hw2reg_fifo_status_reg_t fifo_status; // [69:46]
+ i2c_hw2reg_intr_state_reg_t intr_state; // [123:92]
+ i2c_hw2reg_status_reg_t status; // [91:82]
+ i2c_hw2reg_rdata_reg_t rdata; // [81:74]
+ i2c_hw2reg_fifo_status_reg_t fifo_status; // [73:46]
i2c_hw2reg_val_reg_t val; // [45:14]
i2c_hw2reg_acqdata_reg_t acqdata; // [13:4]
i2c_hw2reg_stretch_ctrl_reg_t stretch_ctrl; // [3:0]
@@ -601,7 +601,7 @@
parameter logic [0:0] I2C_STATUS_TXEMPTY_RESVAL = 1'h 1;
parameter logic [0:0] I2C_STATUS_ACQEMPTY_RESVAL = 1'h 1;
parameter logic [7:0] I2C_RDATA_RESVAL = 8'h 0;
- parameter logic [29:0] I2C_FIFO_STATUS_RESVAL = 30'h 0;
+ parameter logic [30:0] I2C_FIFO_STATUS_RESVAL = 31'h 0;
parameter logic [31:0] I2C_VAL_RESVAL = 32'h 0;
parameter logic [9:0] I2C_ACQDATA_RESVAL = 10'h 0;
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index c01e787..c9eb1a7 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -289,13 +289,13 @@
logic fifo_ctrl_acqrst_we;
logic fifo_ctrl_txrst_wd;
logic fifo_ctrl_txrst_we;
- logic [5:0] fifo_status_fmtlvl_qs;
+ logic [6:0] fifo_status_fmtlvl_qs;
logic fifo_status_fmtlvl_re;
- logic [5:0] fifo_status_txlvl_qs;
+ logic [6:0] fifo_status_txlvl_qs;
logic fifo_status_txlvl_re;
- logic [5:0] fifo_status_rxlvl_qs;
+ logic [6:0] fifo_status_rxlvl_qs;
logic fifo_status_rxlvl_re;
- logic [5:0] fifo_status_acqlvl_qs;
+ logic [6:0] fifo_status_acqlvl_qs;
logic fifo_status_acqlvl_re;
logic ovrd_txovrden_qs;
logic ovrd_txovrden_wd;
@@ -2025,9 +2025,9 @@
// R[fifo_status]: V(True)
- // F[fmtlvl]: 5:0
+ // F[fmtlvl]: 6:0
prim_subreg_ext #(
- .DW (6)
+ .DW (7)
) u_fifo_status_fmtlvl (
.re (fifo_status_fmtlvl_re),
.we (1'b0),
@@ -2040,9 +2040,9 @@
);
- // F[txlvl]: 13:8
+ // F[txlvl]: 14:8
prim_subreg_ext #(
- .DW (6)
+ .DW (7)
) u_fifo_status_txlvl (
.re (fifo_status_txlvl_re),
.we (1'b0),
@@ -2055,9 +2055,9 @@
);
- // F[rxlvl]: 21:16
+ // F[rxlvl]: 22:16
prim_subreg_ext #(
- .DW (6)
+ .DW (7)
) u_fifo_status_rxlvl (
.re (fifo_status_rxlvl_re),
.we (1'b0),
@@ -2070,9 +2070,9 @@
);
- // F[acqlvl]: 29:24
+ // F[acqlvl]: 30:24
prim_subreg_ext #(
- .DW (6)
+ .DW (7)
) u_fifo_status_acqlvl (
.re (fifo_status_acqlvl_re),
.we (1'b0),
@@ -3282,10 +3282,10 @@
end
addr_hit[8]: begin
- reg_rdata_next[5:0] = fifo_status_fmtlvl_qs;
- reg_rdata_next[13:8] = fifo_status_txlvl_qs;
- reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
- reg_rdata_next[29:24] = fifo_status_acqlvl_qs;
+ reg_rdata_next[6:0] = fifo_status_fmtlvl_qs;
+ reg_rdata_next[14:8] = fifo_status_txlvl_qs;
+ reg_rdata_next[22:16] = fifo_status_rxlvl_qs;
+ reg_rdata_next[30:24] = fifo_status_acqlvl_qs;
end
addr_hit[9]: begin
diff --git a/sw/device/lib/dif/dif_i2c_unittest.cc b/sw/device/lib/dif/dif_i2c_unittest.cc
index f67e8f2..067f25a 100644
--- a/sw/device/lib/dif/dif_i2c_unittest.cc
+++ b/sw/device/lib/dif/dif_i2c_unittest.cc
@@ -550,7 +550,7 @@
uint8_t rx, fmt;
EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
EXPECT_EQ(dif_i2c_get_fifo_levels(&i2c_, &rx, &fmt), kDifI2cOk);
- EXPECT_EQ(rx, 0x7);
+ EXPECT_EQ(rx, 0x47);
EXPECT_EQ(fmt, 0x29);
rx = 0, fmt = 0;
@@ -562,7 +562,7 @@
rx = 0, fmt = 0;
EXPECT_READ32(I2C_FIFO_STATUS_REG_OFFSET, 0x10293847);
EXPECT_EQ(dif_i2c_get_fifo_levels(&i2c_, &rx, nullptr), kDifI2cOk);
- EXPECT_EQ(rx, 0x7);
+ EXPECT_EQ(rx, 0x47);
EXPECT_EQ(fmt, 0x0);
}
