[pwrmgr] template pwrmgr hjson
- There are now 3 seprate core files
- only_reg, pkg, and component (similar to alert_handler)
- The only_reg core file will be duplicated at the top level,
while the pkg / component core files will be top agnostic
and can be referenced by other modules
Signed-off-by: Timothy Chen <timothytim@google.com>
[pwrmgr] Various fixes for python lint
Signed-off-by: Timothy Chen <timothytim@google.com>
[pwrmgr] Fix typo
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/pwrmgr/data/pwrmgr.hjson b/hw/ip/pwrmgr/data/pwrmgr.hjson
index a7e48f3..c32ed85 100644
--- a/hw/ip/pwrmgr/data/pwrmgr.hjson
+++ b/hw/ip/pwrmgr/data/pwrmgr.hjson
@@ -62,16 +62,31 @@
package: "pwrmgr_pkg",
},
- { struct: "pwr_peri",
+ { struct: "logic",
+ width: 3,
type: "uni",
- name: "pwr_peri",
+ name: "wakeups",
act: "rcv",
- package: "pwrmgr_pkg",
+ package: "",
+ },
+
+ { struct: "logic",
+ width: 2,
+ type: "uni",
+ name: "rstreqs",
+ act: "rcv",
+ package: "",
},
],
param_list: [
+ { name: "NumWkups",
+ desc: "Number of wakeups",
+ type: "int",
+ default: "16",
+ local: "true"
+ },
],
regwidth: "32",
@@ -254,36 +269,44 @@
]
},
- { name: "WAKEUP_EN",
- desc: "Bit mask for enabled wakeups",
- swaccess: "rw",
- hwaccess: "hro",
- regwen: "WAKEUP_EN_REGWEN",
- resval: "0"
- fields: [
- { bits: "15:0",
- name: "EN",
- desc: '''
- Whenever a particular bit is set to 1, that wakeup is also enabled.
- Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
- ''',
- },
- ]
+ { multireg:
+ { name: "WAKEUP_EN",
+ desc: "Bit mask for enabled wakeups",
+ swaccess: "rw",
+ hwaccess: "hro",
+ regwen: "WAKEUP_EN_REGWEN",
+ resval: "0"
+ cname: "wakeup_en",
+ count: "NumWkups"
+ fields: [
+ { bits: "0",
+ name: "EN",
+ desc: '''
+ Whenever a particular bit is set to 1, that wakeup is also enabled.
+ Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.
+ ''',
+ },
+ ]
+ },
},
- { name: "WAKE_STATUS",
- desc: "A read only register of all current wake requests post enable mask",
- swaccess: "ro",
- hwaccess: "none",
- resval: "0"
- fields: [
- { bits: "15:0",
- name: "VAL",
- desc: '''
- Current value of wake requests
- ''',
- },
- ]
+ { multireg:
+ { name: "WAKE_STATUS",
+ desc: "A read only register of all current wake requests post enable mask",
+ swaccess: "ro",
+ hwaccess: "none",
+ resval: "0"
+ cname: "wake_status",
+ count: "NumWkups",
+ fields: [
+ { bits: "0",
+ name: "VAL",
+ desc: '''
+ Current value of wake requests
+ ''',
+ },
+ ]
+ },
},
{ name: "RESET_EN_REGWEN",
@@ -394,3 +417,4 @@
},
]
}
+
diff --git a/hw/ip/pwrmgr/pwrmgr.core b/hw/ip/pwrmgr/pwrmgr.core
index 09a72ed..a7719f4 100644
--- a/hw/ip/pwrmgr/pwrmgr.core
+++ b/hw/ip/pwrmgr/pwrmgr.core
@@ -8,18 +8,9 @@
filesets:
files_rtl:
depend:
- - lowrisc:ip:tlul
- - lowrisc:prim:all
+ - lowrisc:ip:pwrmgr_component
+ - lowrisc:ip:pwrmgr_only_reg
- lowrisc:ip:pwrmgr_pkg
- files:
- - rtl/pwrmgr_reg_pkg.sv
- - rtl/pwrmgr_reg_top.sv
- - rtl/pwrmgr.sv
- - rtl/pwrmgr_cdc.sv
- - rtl/pwrmgr_slow_fsm.sv
- - rtl/pwrmgr_fsm.sv
- - rtl/pwrmgr_wake_info.sv
- file_type: systemVerilogSource
files_verilator_waiver:
depend:
diff --git a/hw/ip/pwrmgr/pwrmgr_component.core b/hw/ip/pwrmgr/pwrmgr_component.core
new file mode 100644
index 0000000..9034b53
--- /dev/null
+++ b/hw/ip/pwrmgr/pwrmgr_component.core
@@ -0,0 +1,24 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:pwrmgr_component:0.1"
+description: "Power manager comopnents"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:tlul
+ - lowrisc:ip:pwrmgr_pkg
+ files:
+ - rtl/pwrmgr.sv
+ - rtl/pwrmgr_cdc.sv
+ - rtl/pwrmgr_slow_fsm.sv
+ - rtl/pwrmgr_fsm.sv
+ - rtl/pwrmgr_wake_info.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/ip/pwrmgr/pwrmgr_only_reg.core b/hw/ip/pwrmgr/pwrmgr_only_reg.core
new file mode 100644
index 0000000..c6baa50
--- /dev/null
+++ b/hw/ip/pwrmgr/pwrmgr_only_reg.core
@@ -0,0 +1,20 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:pwrmgr_only_reg:0.1"
+description: "pwrmgr IP only register"
+
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:tlul:headers
+ files:
+ - rtl/pwrmgr_reg_pkg.sv
+ - rtl/pwrmgr_reg_top.sv
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_rtl
diff --git a/hw/ip/pwrmgr/pwrmgr_pkg.core b/hw/ip/pwrmgr/pwrmgr_pkg.core
index 73cbca7..7723ab7 100644
--- a/hw/ip/pwrmgr/pwrmgr_pkg.core
+++ b/hw/ip/pwrmgr/pwrmgr_pkg.core
@@ -3,12 +3,14 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:ip:pwrmgr_pkg:0.1"
-description: "Flash Package"
+description: "Power manager package"
+# pwrmgr pkg does not actually depend on ip:tlul
+# but it's used as "serialization" point for the ip/top level split
filesets:
files_rtl:
depend:
- - lowrisc:constants:top_pkg
+ - lowrisc:ip:tlul
files:
- rtl/pwrmgr_pkg.sv
file_type: systemVerilogSource
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr.sv b/hw/ip/pwrmgr/rtl/pwrmgr.sv
index b86cf17..02375ce 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr.sv
@@ -7,7 +7,7 @@
`include "prim_assert.sv"
-module pwrmgr import pwrmgr_pkg::*;
+module pwrmgr import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
(
// Clocks and resets
input clk_slow_i,
@@ -45,14 +45,21 @@
// processor interface
input pwr_cpu_t pwr_cpu_i,
- // peripherals interface, includes pinmux
- input pwr_peri_t pwr_peri_i,
+ // peripherals wakeup and reset requests
+ input [NumWkups-1:0] wakeups_i,
+ input [HwRstReqs-1:0] rstreqs_i,
output intr_wakeup_o
);
- import pwrmgr_reg_pkg::*;
+ ////////////////////////////
+ /// async declarations
+ ////////////////////////////
+ pwr_peri_t peri_reqs_raw;
+
+ assign peri_reqs_raw.wakeups = wakeups_i;
+ assign peri_reqs_raw.rstreqs = rstreqs_i;
////////////////////////////
/// clk_i domain declarations
@@ -78,7 +85,7 @@
// Captured signals
// These signals, though on clk_i domain, are safe for clk_slow_i to use
- pwrmgr_reg2hw_wakeup_en_reg_t slow_wakeup_en;
+ logic [NumWkups-1:0] slow_wakeup_en;
pwrmgr_reg2hw_reset_en_reg_t slow_reset_en;
pwr_ast_rsp_t slow_ast;
@@ -161,7 +168,7 @@
.ack_pwrup_i(ack_pwrup),
.cfg_cdc_sync_i(reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q),
.cdc_sync_done_o(hw2reg.cfg_cdc_sync.de),
- .wakeup_en_i(reg2hw.wakeup_en.q),
+ .wakeup_en_i(reg2hw.wakeup_en),
.reset_en_i(reg2hw.reset_en.q),
.main_pd_ni(reg2hw.control.main_pd_n.q),
.io_clk_en_i(reg2hw.control.io_clk_en.q),
@@ -175,7 +182,7 @@
.ast_i(pwr_ast_i),
// peripheral signals
- .peri_i(pwr_peri_i)
+ .peri_i(peri_reqs_raw)
);
assign hw2reg.cfg_cdc_sync.d = 1'b0;
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_cdc.sv b/hw/ip/pwrmgr/rtl/pwrmgr_cdc.sv
index 9f71c17..34bf19a 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_cdc.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_cdc.sv
@@ -7,7 +7,7 @@
`include "prim_assert.sv"
-module pwrmgr_cdc import pwrmgr_pkg::*;
+module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
(
// Clocks and resets
input clk_slow_i,
@@ -20,7 +20,7 @@
input slow_ack_pwrdn_i,
input slow_pwrup_cause_toggle_i,
input pwrup_cause_e slow_pwrup_cause_i,
- output pwrmgr_reg_pkg::pwrmgr_reg2hw_wakeup_en_reg_t slow_wakeup_en_o,
+ output logic [NumWkups-1:0] slow_wakeup_en_o,
output pwrmgr_reg_pkg::pwrmgr_reg2hw_reset_en_reg_t slow_reset_en_o,
output logic slow_main_pd_no,
output logic slow_io_clk_en_o,
@@ -35,7 +35,7 @@
input req_pwrdn_i,
input ack_pwrup_i,
input cfg_cdc_sync_i,
- input pwrmgr_reg_pkg::pwrmgr_reg2hw_wakeup_en_reg_t wakeup_en_i,
+ input [NumWkups-1:0] wakeup_en_i,
input pwrmgr_reg_pkg::pwrmgr_reg2hw_reset_en_reg_t reset_en_i,
input main_pd_ni,
input io_clk_en_i,
@@ -92,7 +92,7 @@
// So there is no general concern about recombining as there is
// no intent to use them in a related manner.
prim_flop_2sync # (
- .Width(HwRstReqs + WakeUpPeris)
+ .Width(HwRstReqs + NumWkups)
) i_slow_ext_req_sync (
.clk_i (clk_slow_i),
.rst_ni (rst_slow_ni),
@@ -213,7 +213,7 @@
end
prim_flop_2sync # (
- .Width(HwRstReqs + WakeUpPeris)
+ .Width(HwRstReqs + NumWkups)
) i_ext_req_sync (
.clk_i,
.rst_ni,
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
index 79f238a..f3f5378 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_pkg.sv
@@ -15,9 +15,8 @@
parameter PowerDomains = 2; // this maybe needs to be a topgen populated number, or from topcfg?
// variables referenced only by pwrmgr
- localparam WakeUpPeris = 16; // this needs to be a topgen populated number, or from topcfg?
- localparam TotalWakeWidth = WakeUpPeris + 2; // Abort and fall through are added
-
+ // pwrmgr_reg_pkg::NumWkups; // should this be coming from top_pkg instead?
+ localparam TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added
// pwrmgr to ast
typedef struct packed {
@@ -141,21 +140,18 @@
core_sleeping: 1'b0
};
- // peripherals to pwrmgr
- // TODO, switch this to two logic arrays once the option to support
- // logic during intermodule.py is in.
- // Structs are used for now since these happen to support dangling port
- // defaults.
- typedef struct packed {
- logic [WakeUpPeris-1:0] wakeups;
- logic [HwRstReqs-1:0] rstreqs;
- } pwr_peri_t;
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups;
+ logic [HwRstReqs-1:0] rstreqs;
// default value (for dangling ports)
- parameter pwr_peri_t PWR_PERI_DEFAULT = '{
- wakeups: WakeUpPeris'(1'b1),
- rstreqs: '0
- };
+ parameter WAKEUPS_DEFAULT = '0;
+ parameter RSTREQS_DEFAULT = '0;
+
+ // peripherals to pwrmgr
+ typedef struct packed {
+ logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups;
+ logic [HwRstReqs-1:0] rstreqs;
+ } pwr_peri_t;
// power-up causes
typedef enum logic [1:0] {
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/hw/ip/pwrmgr/rtl/pwrmgr_reg_pkg.sv
index 6b48a62..4a6a9d7 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_reg_pkg.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_reg_pkg.sv
@@ -6,6 +6,9 @@
package pwrmgr_reg_pkg;
+ // Param list
+ parameter int NumWkups = 16;
+
////////////////////////////
// Typedefs for registers //
////////////////////////////
@@ -43,8 +46,8 @@
} pwrmgr_reg2hw_cfg_cdc_sync_reg_t;
typedef struct packed {
- logic [15:0] q;
- } pwrmgr_reg2hw_wakeup_en_reg_t;
+ logic q;
+ } pwrmgr_reg2hw_wakeup_en_mreg_t;
typedef struct packed {
logic [1:0] q;
@@ -113,7 +116,7 @@
pwrmgr_reg2hw_intr_test_reg_t intr_test; // [47:46]
pwrmgr_reg2hw_control_reg_t control; // [45:42]
pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [41:40]
- pwrmgr_reg2hw_wakeup_en_reg_t wakeup_en; // [39:24]
+ pwrmgr_reg2hw_wakeup_en_mreg_t [15:0] wakeup_en; // [39:24]
pwrmgr_reg2hw_reset_en_reg_t reset_en; // [23:22]
pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [21:21]
pwrmgr_reg2hw_wake_info_reg_t wake_info; // [20:0]
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
index 1253a40..6080cf4 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_reg_top.sv
@@ -99,10 +99,70 @@
logic wakeup_en_regwen_qs;
logic wakeup_en_regwen_wd;
logic wakeup_en_regwen_we;
- logic [15:0] wakeup_en_qs;
- logic [15:0] wakeup_en_wd;
- logic wakeup_en_we;
- logic [15:0] wake_status_qs;
+ logic wakeup_en_en0_qs;
+ logic wakeup_en_en0_wd;
+ logic wakeup_en_en0_we;
+ logic wakeup_en_en1_qs;
+ logic wakeup_en_en1_wd;
+ logic wakeup_en_en1_we;
+ logic wakeup_en_en2_qs;
+ logic wakeup_en_en2_wd;
+ logic wakeup_en_en2_we;
+ logic wakeup_en_en3_qs;
+ logic wakeup_en_en3_wd;
+ logic wakeup_en_en3_we;
+ logic wakeup_en_en4_qs;
+ logic wakeup_en_en4_wd;
+ logic wakeup_en_en4_we;
+ logic wakeup_en_en5_qs;
+ logic wakeup_en_en5_wd;
+ logic wakeup_en_en5_we;
+ logic wakeup_en_en6_qs;
+ logic wakeup_en_en6_wd;
+ logic wakeup_en_en6_we;
+ logic wakeup_en_en7_qs;
+ logic wakeup_en_en7_wd;
+ logic wakeup_en_en7_we;
+ logic wakeup_en_en8_qs;
+ logic wakeup_en_en8_wd;
+ logic wakeup_en_en8_we;
+ logic wakeup_en_en9_qs;
+ logic wakeup_en_en9_wd;
+ logic wakeup_en_en9_we;
+ logic wakeup_en_en10_qs;
+ logic wakeup_en_en10_wd;
+ logic wakeup_en_en10_we;
+ logic wakeup_en_en11_qs;
+ logic wakeup_en_en11_wd;
+ logic wakeup_en_en11_we;
+ logic wakeup_en_en12_qs;
+ logic wakeup_en_en12_wd;
+ logic wakeup_en_en12_we;
+ logic wakeup_en_en13_qs;
+ logic wakeup_en_en13_wd;
+ logic wakeup_en_en13_we;
+ logic wakeup_en_en14_qs;
+ logic wakeup_en_en14_wd;
+ logic wakeup_en_en14_we;
+ logic wakeup_en_en15_qs;
+ logic wakeup_en_en15_wd;
+ logic wakeup_en_en15_we;
+ logic wake_status_val0_qs;
+ logic wake_status_val1_qs;
+ logic wake_status_val2_qs;
+ logic wake_status_val3_qs;
+ logic wake_status_val4_qs;
+ logic wake_status_val5_qs;
+ logic wake_status_val6_qs;
+ logic wake_status_val7_qs;
+ logic wake_status_val8_qs;
+ logic wake_status_val9_qs;
+ logic wake_status_val10_qs;
+ logic wake_status_val11_qs;
+ logic wake_status_val12_qs;
+ logic wake_status_val13_qs;
+ logic wake_status_val14_qs;
+ logic wake_status_val15_qs;
logic reset_en_regwen_qs;
logic reset_en_regwen_wd;
logic reset_en_regwen_we;
@@ -373,19 +433,22 @@
);
+
+ // Subregister 0 of Multireg wakeup_en
// R[wakeup_en]: V(False)
+ // F[en0]: 0:0
prim_subreg #(
- .DW (16),
+ .DW (1),
.SWACCESS("RW"),
- .RESVAL (16'h0)
- ) u_wakeup_en (
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface (qualified with register enable)
- .we (wakeup_en_we & wakeup_en_regwen_qs),
- .wd (wakeup_en_wd),
+ .we (wakeup_en_en0_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en0_wd),
// from internal hardware
.de (1'b0),
@@ -393,17 +456,487 @@
// to internal hardware
.qe (),
- .q (reg2hw.wakeup_en.q ),
+ .q (reg2hw.wakeup_en[0].q ),
// to register interface (read)
- .qs (wakeup_en_qs)
+ .qs (wakeup_en_en0_qs)
);
+ // F[en1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en1_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[1].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en1_qs)
+ );
+
+
+ // F[en2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en2_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[2].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en2_qs)
+ );
+
+
+ // F[en3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en3_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[3].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en3_qs)
+ );
+
+
+ // F[en4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en4_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[4].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en4_qs)
+ );
+
+
+ // F[en5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en5_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[5].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en5_qs)
+ );
+
+
+ // F[en6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en6_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[6].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en6_qs)
+ );
+
+
+ // F[en7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en7_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[7].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en7_qs)
+ );
+
+
+ // F[en8]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en8 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en8_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en8_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[8].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en8_qs)
+ );
+
+
+ // F[en9]: 9:9
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en9 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en9_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en9_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[9].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en9_qs)
+ );
+
+
+ // F[en10]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en10 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en10_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en10_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[10].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en10_qs)
+ );
+
+
+ // F[en11]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en11 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en11_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en11_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[11].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en11_qs)
+ );
+
+
+ // F[en12]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en12 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en12_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en12_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[12].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en12_qs)
+ );
+
+
+ // F[en13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en13 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en13_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[13].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en13_qs)
+ );
+
+
+ // F[en14]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en14 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en14_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en14_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[14].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en14_qs)
+ );
+
+
+ // F[en15]: 15:15
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_wakeup_en_en15 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (wakeup_en_en15_we & wakeup_en_regwen_qs),
+ .wd (wakeup_en_en15_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.wakeup_en[15].q ),
+
+ // to register interface (read)
+ .qs (wakeup_en_en15_qs)
+ );
+
+
+
+
+ // Subregister 0 of Multireg wake_status
// R[wake_status]: V(False)
+ // F[val0]: 0:0
// constant-only read
- assign wake_status_qs = 16'h0;
+ assign wake_status_val0_qs = 1'h0;
+
+
+ // F[val1]: 1:1
+ // constant-only read
+ assign wake_status_val1_qs = 1'h0;
+
+
+ // F[val2]: 2:2
+ // constant-only read
+ assign wake_status_val2_qs = 1'h0;
+
+
+ // F[val3]: 3:3
+ // constant-only read
+ assign wake_status_val3_qs = 1'h0;
+
+
+ // F[val4]: 4:4
+ // constant-only read
+ assign wake_status_val4_qs = 1'h0;
+
+
+ // F[val5]: 5:5
+ // constant-only read
+ assign wake_status_val5_qs = 1'h0;
+
+
+ // F[val6]: 6:6
+ // constant-only read
+ assign wake_status_val6_qs = 1'h0;
+
+
+ // F[val7]: 7:7
+ // constant-only read
+ assign wake_status_val7_qs = 1'h0;
+
+
+ // F[val8]: 8:8
+ // constant-only read
+ assign wake_status_val8_qs = 1'h0;
+
+
+ // F[val9]: 9:9
+ // constant-only read
+ assign wake_status_val9_qs = 1'h0;
+
+
+ // F[val10]: 10:10
+ // constant-only read
+ assign wake_status_val10_qs = 1'h0;
+
+
+ // F[val11]: 11:11
+ // constant-only read
+ assign wake_status_val11_qs = 1'h0;
+
+
+ // F[val12]: 12:12
+ // constant-only read
+ assign wake_status_val12_qs = 1'h0;
+
+
+ // F[val13]: 13:13
+ // constant-only read
+ assign wake_status_val13_qs = 1'h0;
+
+
+ // F[val14]: 14:14
+ // constant-only read
+ assign wake_status_val14_qs = 1'h0;
+
+
+ // F[val15]: 15:15
+ // constant-only read
+ assign wake_status_val15_qs = 1'h0;
+
// R[reset_en_regwen]: V(False)
@@ -611,8 +1144,68 @@
assign wakeup_en_regwen_we = addr_hit[6] & reg_we & ~wr_err;
assign wakeup_en_regwen_wd = reg_wdata[0];
- assign wakeup_en_we = addr_hit[7] & reg_we & ~wr_err;
- assign wakeup_en_wd = reg_wdata[15:0];
+ assign wakeup_en_en0_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en0_wd = reg_wdata[0];
+
+ assign wakeup_en_en1_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en1_wd = reg_wdata[1];
+
+ assign wakeup_en_en2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en2_wd = reg_wdata[2];
+
+ assign wakeup_en_en3_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en3_wd = reg_wdata[3];
+
+ assign wakeup_en_en4_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en4_wd = reg_wdata[4];
+
+ assign wakeup_en_en5_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en5_wd = reg_wdata[5];
+
+ assign wakeup_en_en6_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en6_wd = reg_wdata[6];
+
+ assign wakeup_en_en7_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en7_wd = reg_wdata[7];
+
+ assign wakeup_en_en8_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en8_wd = reg_wdata[8];
+
+ assign wakeup_en_en9_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en9_wd = reg_wdata[9];
+
+ assign wakeup_en_en10_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en10_wd = reg_wdata[10];
+
+ assign wakeup_en_en11_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en11_wd = reg_wdata[11];
+
+ assign wakeup_en_en12_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en12_wd = reg_wdata[12];
+
+ assign wakeup_en_en13_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en13_wd = reg_wdata[13];
+
+ assign wakeup_en_en14_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en14_wd = reg_wdata[14];
+
+ assign wakeup_en_en15_we = addr_hit[7] & reg_we & ~wr_err;
+ assign wakeup_en_en15_wd = reg_wdata[15];
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
assign reset_en_regwen_we = addr_hit[9] & reg_we & ~wr_err;
@@ -673,11 +1266,41 @@
end
addr_hit[7]: begin
- reg_rdata_next[15:0] = wakeup_en_qs;
+ reg_rdata_next[0] = wakeup_en_en0_qs;
+ reg_rdata_next[1] = wakeup_en_en1_qs;
+ reg_rdata_next[2] = wakeup_en_en2_qs;
+ reg_rdata_next[3] = wakeup_en_en3_qs;
+ reg_rdata_next[4] = wakeup_en_en4_qs;
+ reg_rdata_next[5] = wakeup_en_en5_qs;
+ reg_rdata_next[6] = wakeup_en_en6_qs;
+ reg_rdata_next[7] = wakeup_en_en7_qs;
+ reg_rdata_next[8] = wakeup_en_en8_qs;
+ reg_rdata_next[9] = wakeup_en_en9_qs;
+ reg_rdata_next[10] = wakeup_en_en10_qs;
+ reg_rdata_next[11] = wakeup_en_en11_qs;
+ reg_rdata_next[12] = wakeup_en_en12_qs;
+ reg_rdata_next[13] = wakeup_en_en13_qs;
+ reg_rdata_next[14] = wakeup_en_en14_qs;
+ reg_rdata_next[15] = wakeup_en_en15_qs;
end
addr_hit[8]: begin
- reg_rdata_next[15:0] = wake_status_qs;
+ reg_rdata_next[0] = wake_status_val0_qs;
+ reg_rdata_next[1] = wake_status_val1_qs;
+ reg_rdata_next[2] = wake_status_val2_qs;
+ reg_rdata_next[3] = wake_status_val3_qs;
+ reg_rdata_next[4] = wake_status_val4_qs;
+ reg_rdata_next[5] = wake_status_val5_qs;
+ reg_rdata_next[6] = wake_status_val6_qs;
+ reg_rdata_next[7] = wake_status_val7_qs;
+ reg_rdata_next[8] = wake_status_val8_qs;
+ reg_rdata_next[9] = wake_status_val9_qs;
+ reg_rdata_next[10] = wake_status_val10_qs;
+ reg_rdata_next[11] = wake_status_val11_qs;
+ reg_rdata_next[12] = wake_status_val12_qs;
+ reg_rdata_next[13] = wake_status_val13_qs;
+ reg_rdata_next[14] = wake_status_val14_qs;
+ reg_rdata_next[15] = wake_status_val15_qs;
end
addr_hit[9]: begin
diff --git a/hw/ip/pwrmgr/rtl/pwrmgr_wake_info.sv b/hw/ip/pwrmgr/rtl/pwrmgr_wake_info.sv
index 50eabc9..fd84c4e 100644
--- a/hw/ip/pwrmgr/rtl/pwrmgr_wake_info.sv
+++ b/hw/ip/pwrmgr/rtl/pwrmgr_wake_info.sv
@@ -7,14 +7,15 @@
`include "prim_assert.sv"
-module pwrmgr_wake_info import pwrmgr_pkg::*; (
+module pwrmgr_wake_info import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;
+(
input clk_i,
input rst_ni,
input wr_i,
input [TotalWakeWidth-1:0] data_i,
input start_capture_i,
input record_dis_i,
- input [WakeUpPeris-1:0] wakeups_i,
+ input [NumWkups-1:0] wakeups_i,
input fall_through_i,
input abort_i,
output logic [TotalWakeWidth-1:0] info_o
@@ -45,8 +46,8 @@
end else if (wr_i) begin
info_o <= info_o & ~data_i; // W1C
end else if (record_en) begin // If set once, hold until clear
- info_o[0 +: WakeUpPeris] <= info_o[0 +: WakeUpPeris] | wakeups_i;
- info_o[WakeUpPeris +: 2] <= info_o[WakeUpPeris +: 2] | {abort_i, fall_through_i};
+ info_o[0 +: NumWkups] <= info_o[0 +: NumWkups] | wakeups_i;
+ info_o[NumWkups +: 2] <= info_o[NumWkups +: 2] | {abort_i, fall_through_i};
end
end
diff --git a/hw/ip/pwrmgr/util/reg_pwrmgr.py b/hw/ip/pwrmgr/util/reg_pwrmgr.py
new file mode 100755
index 0000000..4c74ce0
--- /dev/null
+++ b/hw/ip/pwrmgr/util/reg_pwrmgr.py
@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+r"""Convert mako template to Hjson register description
+"""
+import argparse
+import sys
+from io import StringIO
+
+from mako.template import Template
+
+
+def main():
+ parser = argparse.ArgumentParser(prog="reg_pwrmgr")
+ parser.add_argument('input',
+ nargs='?',
+ metavar='file',
+ type=argparse.FileType('r'),
+ default=sys.stdin,
+ help='input template file')
+ parser.add_argument('--n_wkups',
+ type=int,
+ default=16,
+ help='Number of Wakeup sources')
+
+ args = parser.parse_args()
+
+ # Determine output: if stdin then stdout if not then ??
+ out = StringIO()
+
+ reg_tpl = Template(args.input.read())
+ out.write(
+ reg_tpl.render(NumWkups=args.n_wkups))
+
+ print(out.getvalue())
+
+ out.close()
+
+
+if __name__ == "__main__":
+ main()
diff --git a/hw/ip/rstmgr/rstmgr_pkg.core b/hw/ip/rstmgr/rstmgr_pkg.core
index 8ebf4d0..dd1ef82 100644
--- a/hw/ip/rstmgr/rstmgr_pkg.core
+++ b/hw/ip/rstmgr/rstmgr_pkg.core
@@ -9,6 +9,7 @@
files_rtl:
depend:
- lowrisc:constants:top_pkg
+ - lowrisc:ip:pwrmgr_pkg
files:
- rtl/rstmgr_pkg.sv
file_type: systemVerilogSource
