commit | 6e518c5b24c1ac1d527706ec03a8e9145f9f1066 | [log] [tgz] |
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author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Oct 02 16:45:16 2020 +0100 |
committer | Rupert Swarbrick <rswarbrick@gmail.com> | Mon Oct 05 14:43:07 2020 +0100 |
tree | 4e94bd098c6dde1a3ffd5149511f36365a407def | |
parent | b35a77dd756aabab9abd263943fbba8dcb62b20d [diff] |
[otbn] Add proper error tracking to otbn_core_model This turned out to be a bit painful: if you want to update more than one SystemVerilog variable, you need to put the logic in a task, but then verilator notices that you're being called from an always_ff block and tells you to use non-blocking assignments (not unreasonably). It also complains if you mix blocking and non-blocking assignments. If you still need to inspect the return code from DPI functions, you might try to change this pattern: retcode = call_dpi(arg1, arg2); unique case (retcode) ... endcase to this one: unique case (call_dpi(arg1, arg2)) ... endcase but that doesn't work because call_dpi(..) gets evaluated (with side-effects) for each branch of the case statement until a match is found. So I gave up, packing the status bits that I cared about into an integer and just doing the stateful updates in the C++ code. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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