Flash updates
- provide configuration protection to region registers
- update interrupts to be edge triggered so there is not a storm
- Updates to reggen validate.py for multireg and unique regwen
diff --git a/hw/ip/flash_ctrl/doc/flash_ctrl.hjson b/hw/ip/flash_ctrl/doc/flash_ctrl.hjson
index 972d824..efaed29 100644
--- a/hw/ip/flash_ctrl/doc/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/doc/flash_ctrl.hjson
@@ -115,6 +115,36 @@
},
]
},
+ { multireg: {
+ cname: "FLASH_CTRL",
+ name: "REGION_CFG_REGWEN"
+ desc: "Memory region registers configuration enable.",
+ count: 8,
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "REGION",
+ resval: "1"
+ desc: "Region register write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Region locked",
+ desc: '''
+ Region can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Region enabled",
+ desc: '''
+ Region can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
{ multireg: {
cname: "FLASH_CTRL",
@@ -123,6 +153,8 @@
count: 8,
swaccess: "rw",
hwaccess: "hro",
+ regwen: "REGION_CFG_REGWEN_REGION",
+ regwen_incr: "true",
fields: [
{ bits: "0",
name: "EN",
@@ -202,11 +234,44 @@
{ multireg: {
cname: "FLASH_CTRL",
+ name: "BANK_CFG_REGWEN"
+ desc: "Bank configuration registers configuration enable.",
+ count: 2,
+ swaccess: "rw0c",
+ hwaccess: "none",
+ fields: [
+ { bits: "0",
+ name: "BANK",
+ resval: "1"
+ desc: "Bank register write enable. Once set to 0, it can longer be configured to 1",
+ enum: [
+ { value: "0",
+ name: "Bank locked",
+ desc: '''
+ Bank can no longer be configured until next reset
+ '''
+ },
+ { value: "1",
+ name: "Bank enabled",
+ desc: '''
+ Bank can be configured
+ '''
+ },
+ ]
+ },
+ ],
+ },
+ },
+
+ { multireg: {
+ cname: "FLASH_CTRL",
name: "MP_BANK_CFG",
desc: "Memory protect bank configuration",
count: 2,
swaccess: "rw",
hwaccess: "hro",
+ regwen: "BANK_CFG_REGWEN_BANK"
+ regwen_incr: "true",
fields: [
{ bits: "1",
name: "ERASE_EN",
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv
index 1e917e1..c16c165 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_reg_block.sv
@@ -11,6 +11,7 @@
typedef class flash_ctrl_reg_intr_test;
typedef class flash_ctrl_reg_control;
typedef class flash_ctrl_reg_addr;
+typedef class flash_ctrl_reg_region_cfg_regwen;
typedef class flash_ctrl_reg_mp_region_cfg0;
typedef class flash_ctrl_reg_mp_region_cfg1;
typedef class flash_ctrl_reg_mp_region_cfg2;
@@ -20,6 +21,7 @@
typedef class flash_ctrl_reg_mp_region_cfg6;
typedef class flash_ctrl_reg_mp_region_cfg7;
typedef class flash_ctrl_reg_default_region;
+typedef class flash_ctrl_reg_bank_cfg_regwen;
typedef class flash_ctrl_reg_mp_bank_cfg;
typedef class flash_ctrl_reg_op_status;
typedef class flash_ctrl_reg_status;
@@ -408,6 +410,120 @@
endclass : flash_ctrl_reg_addr
+// Class: flash_ctrl_reg_region_cfg_regwen
+class flash_ctrl_reg_region_cfg_regwen extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field region0;
+ rand dv_base_reg_field region1;
+ rand dv_base_reg_field region2;
+ rand dv_base_reg_field region3;
+ rand dv_base_reg_field region4;
+ rand dv_base_reg_field region5;
+ rand dv_base_reg_field region6;
+ rand dv_base_reg_field region7;
+
+ `uvm_object_utils(flash_ctrl_reg_region_cfg_regwen)
+
+ function new(string name = "flash_ctrl_reg_region_cfg_regwen",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ region0 = dv_base_reg_field::type_id::create("region0");
+ region0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region1 = dv_base_reg_field::type_id::create("region1");
+ region1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region2 = dv_base_reg_field::type_id::create("region2");
+ region2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region3 = dv_base_reg_field::type_id::create("region3");
+ region3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region4 = dv_base_reg_field::type_id::create("region4");
+ region4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region5 = dv_base_reg_field::type_id::create("region5");
+ region5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region6 = dv_base_reg_field::type_id::create("region6");
+ region6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(6),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region7 = dv_base_reg_field::type_id::create("region7");
+ region7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(7),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_region_cfg_regwen
+
// Class: flash_ctrl_reg_mp_region_cfg0
class flash_ctrl_reg_mp_region_cfg0 extends dv_base_reg;
// fields
@@ -1182,6 +1298,48 @@
endclass : flash_ctrl_reg_default_region
+// Class: flash_ctrl_reg_bank_cfg_regwen
+class flash_ctrl_reg_bank_cfg_regwen extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field bank0;
+ rand dv_base_reg_field bank1;
+
+ `uvm_object_utils(flash_ctrl_reg_bank_cfg_regwen)
+
+ function new(string name = "flash_ctrl_reg_bank_cfg_regwen",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ bank0 = dv_base_reg_field::type_id::create("bank0");
+ bank0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ bank1 = dv_base_reg_field::type_id::create("bank1");
+ bank1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_bank_cfg_regwen
+
// Class: flash_ctrl_reg_mp_bank_cfg
class flash_ctrl_reg_mp_bank_cfg extends dv_base_reg;
// fields
@@ -1478,6 +1636,7 @@
rand flash_ctrl_reg_intr_test intr_test;
rand flash_ctrl_reg_control control;
rand flash_ctrl_reg_addr addr;
+ rand flash_ctrl_reg_region_cfg_regwen region_cfg_regwen;
rand flash_ctrl_reg_mp_region_cfg0 mp_region_cfg0;
rand flash_ctrl_reg_mp_region_cfg1 mp_region_cfg1;
rand flash_ctrl_reg_mp_region_cfg2 mp_region_cfg2;
@@ -1487,6 +1646,7 @@
rand flash_ctrl_reg_mp_region_cfg6 mp_region_cfg6;
rand flash_ctrl_reg_mp_region_cfg7 mp_region_cfg7;
rand flash_ctrl_reg_default_region default_region;
+ rand flash_ctrl_reg_bank_cfg_regwen bank_cfg_regwen;
rand flash_ctrl_reg_mp_bank_cfg mp_bank_cfg;
rand flash_ctrl_reg_op_status op_status;
rand flash_ctrl_reg_status status;
@@ -1541,101 +1701,113 @@
default_map.add_reg(.rg(addr),
.offset(32'h10),
.rights("RW"));
+ region_cfg_regwen = flash_ctrl_reg_region_cfg_regwen::type_id::create("region_cfg_regwen");
+ region_cfg_regwen.configure(.blk_parent(this));
+ region_cfg_regwen.build();
+ default_map.add_reg(.rg(region_cfg_regwen),
+ .offset(32'h14),
+ .rights("RW"));
mp_region_cfg0 = flash_ctrl_reg_mp_region_cfg0::type_id::create("mp_region_cfg0");
mp_region_cfg0.configure(.blk_parent(this));
mp_region_cfg0.build();
default_map.add_reg(.rg(mp_region_cfg0),
- .offset(32'h14),
+ .offset(32'h18),
.rights("RW"));
mp_region_cfg1 = flash_ctrl_reg_mp_region_cfg1::type_id::create("mp_region_cfg1");
mp_region_cfg1.configure(.blk_parent(this));
mp_region_cfg1.build();
default_map.add_reg(.rg(mp_region_cfg1),
- .offset(32'h18),
+ .offset(32'h1c),
.rights("RW"));
mp_region_cfg2 = flash_ctrl_reg_mp_region_cfg2::type_id::create("mp_region_cfg2");
mp_region_cfg2.configure(.blk_parent(this));
mp_region_cfg2.build();
default_map.add_reg(.rg(mp_region_cfg2),
- .offset(32'h1c),
+ .offset(32'h20),
.rights("RW"));
mp_region_cfg3 = flash_ctrl_reg_mp_region_cfg3::type_id::create("mp_region_cfg3");
mp_region_cfg3.configure(.blk_parent(this));
mp_region_cfg3.build();
default_map.add_reg(.rg(mp_region_cfg3),
- .offset(32'h20),
+ .offset(32'h24),
.rights("RW"));
mp_region_cfg4 = flash_ctrl_reg_mp_region_cfg4::type_id::create("mp_region_cfg4");
mp_region_cfg4.configure(.blk_parent(this));
mp_region_cfg4.build();
default_map.add_reg(.rg(mp_region_cfg4),
- .offset(32'h24),
+ .offset(32'h28),
.rights("RW"));
mp_region_cfg5 = flash_ctrl_reg_mp_region_cfg5::type_id::create("mp_region_cfg5");
mp_region_cfg5.configure(.blk_parent(this));
mp_region_cfg5.build();
default_map.add_reg(.rg(mp_region_cfg5),
- .offset(32'h28),
+ .offset(32'h2c),
.rights("RW"));
mp_region_cfg6 = flash_ctrl_reg_mp_region_cfg6::type_id::create("mp_region_cfg6");
mp_region_cfg6.configure(.blk_parent(this));
mp_region_cfg6.build();
default_map.add_reg(.rg(mp_region_cfg6),
- .offset(32'h2c),
+ .offset(32'h30),
.rights("RW"));
mp_region_cfg7 = flash_ctrl_reg_mp_region_cfg7::type_id::create("mp_region_cfg7");
mp_region_cfg7.configure(.blk_parent(this));
mp_region_cfg7.build();
default_map.add_reg(.rg(mp_region_cfg7),
- .offset(32'h30),
+ .offset(32'h34),
.rights("RW"));
default_region = flash_ctrl_reg_default_region::type_id::create("default_region");
default_region.configure(.blk_parent(this));
default_region.build();
default_map.add_reg(.rg(default_region),
- .offset(32'h34),
+ .offset(32'h38),
+ .rights("RW"));
+ bank_cfg_regwen = flash_ctrl_reg_bank_cfg_regwen::type_id::create("bank_cfg_regwen");
+ bank_cfg_regwen.configure(.blk_parent(this));
+ bank_cfg_regwen.build();
+ default_map.add_reg(.rg(bank_cfg_regwen),
+ .offset(32'h3c),
.rights("RW"));
mp_bank_cfg = flash_ctrl_reg_mp_bank_cfg::type_id::create("mp_bank_cfg");
mp_bank_cfg.configure(.blk_parent(this));
mp_bank_cfg.build();
default_map.add_reg(.rg(mp_bank_cfg),
- .offset(32'h38),
+ .offset(32'h40),
.rights("RW"));
op_status = flash_ctrl_reg_op_status::type_id::create("op_status");
op_status.configure(.blk_parent(this));
op_status.build();
default_map.add_reg(.rg(op_status),
- .offset(32'h3c),
+ .offset(32'h44),
.rights("RW"));
status = flash_ctrl_reg_status::type_id::create("status");
status.configure(.blk_parent(this));
status.build();
default_map.add_reg(.rg(status),
- .offset(32'h40),
+ .offset(32'h48),
.rights("RO"));
scratch = flash_ctrl_reg_scratch::type_id::create("scratch");
scratch.configure(.blk_parent(this));
scratch.build();
default_map.add_reg(.rg(scratch),
- .offset(32'h44),
+ .offset(32'h4c),
.rights("RW"));
fifo_lvl = flash_ctrl_reg_fifo_lvl::type_id::create("fifo_lvl");
fifo_lvl.configure(.blk_parent(this));
fifo_lvl.build();
default_map.add_reg(.rg(fifo_lvl),
- .offset(32'h48),
+ .offset(32'h50),
.rights("RW"));
// create memories
prog_fifo = flash_ctrl_mem_prog_fifo::type_id::create("prog_fifo");
prog_fifo.configure(.parent(this));
default_map.add_mem(.mem(prog_fifo),
- .offset(32'h4c),
+ .offset(32'h54),
.rights("WO"));
rd_fifo = flash_ctrl_mem_rd_fifo::type_id::create("rd_fifo");
rd_fifo.configure(.parent(this));
default_map.add_mem(.mem(rd_fifo),
- .offset(32'h50),
+ .offset(32'h58),
.rights("RO"));
endfunction : build
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index bdfff59..f3e770d 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -425,6 +425,28 @@
assign init_busy = flash_i.init_busy;
// Interrupts
+ // Generate edge triggered signals for sources that are level
+ logic [3:0] intr_src;
+ logic [3:0] intr_src_q;
+ logic [3:0] intr_assert;
+
+ assign intr_src = { ~prog_fifo_rvalid,
+ reg2hw.fifo_lvl.prog.q == prog_fifo_depth,
+ ~rd_fifo_wready,
+ reg2hw.fifo_lvl.rd.q == rd_fifo_depth
+ };
+
+ always_ff @(posedge clk_i or negedge rst_ni) begin
+ if (!rst_ni) begin
+ intr_src_q <= 'h0;
+ end else begin
+ intr_src_q <= intr_src;
+ end
+ end
+
+ assign intr_assert = ~intr_src_q & intr_src;
+
+
assign intr_prog_empty_o = reg2hw.intr_enable.prog_empty.q & reg2hw.intr_state.prog_empty.q;
assign intr_prog_lvl_o = reg2hw.intr_enable.prog_lvl.q & reg2hw.intr_state.prog_lvl.q;
assign intr_rd_full_o = reg2hw.intr_enable.rd_full.q & reg2hw.intr_state.rd_full.q;
@@ -433,22 +455,22 @@
assign intr_op_error_o = reg2hw.intr_enable.op_error.q & reg2hw.intr_state.op_error.q;
assign hw2reg.intr_state.prog_empty.d = 1'b1;
- assign hw2reg.intr_state.prog_empty.de = ~prog_fifo_rvalid |
+ assign hw2reg.intr_state.prog_empty.de = intr_assert[3] |
(reg2hw.intr_test.prog_empty.qe &
reg2hw.intr_test.prog_empty.q);
assign hw2reg.intr_state.prog_lvl.d = 1'b1;
- assign hw2reg.intr_state.prog_lvl.de = (reg2hw.fifo_lvl.prog.q == prog_fifo_depth) |
+ assign hw2reg.intr_state.prog_lvl.de = intr_assert[2] |
(reg2hw.intr_test.prog_lvl.qe &
reg2hw.intr_test.prog_lvl.q);
assign hw2reg.intr_state.rd_full.d = 1'b1;
- assign hw2reg.intr_state.rd_full.de = ~rd_fifo_wready |
+ assign hw2reg.intr_state.rd_full.de = intr_assert[1] |
(reg2hw.intr_test.rd_full.qe &
reg2hw.intr_test.rd_full.q);
assign hw2reg.intr_state.rd_lvl.d = 1'b1;
- assign hw2reg.intr_state.rd_lvl.de = (reg2hw.fifo_lvl.rd.q == rd_fifo_depth) |
+ assign hw2reg.intr_state.rd_lvl.de = intr_assert[0] |
(reg2hw.intr_test.rd_lvl.qe &
reg2hw.intr_test.rd_lvl.q);
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index dfc0262..9a68b92 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -7,7 +7,9 @@
package flash_ctrl_reg_pkg;
// Param list
+ localparam int REGION_CFG_REGWEN = 8;
localparam int MP_REGION_CFG = 8;
+ localparam int BANK_CFG_REGWEN = 2;
localparam int MP_BANK_CFG = 2;
// Register to internal design logic
@@ -367,25 +369,27 @@
parameter FLASH_CTRL_INTR_TEST_OFFSET = 7'h 8;
parameter FLASH_CTRL_CONTROL_OFFSET = 7'h c;
parameter FLASH_CTRL_ADDR_OFFSET = 7'h 10;
- parameter FLASH_CTRL_MP_REGION_CFG0_OFFSET = 7'h 14;
- parameter FLASH_CTRL_MP_REGION_CFG1_OFFSET = 7'h 18;
- parameter FLASH_CTRL_MP_REGION_CFG2_OFFSET = 7'h 1c;
- parameter FLASH_CTRL_MP_REGION_CFG3_OFFSET = 7'h 20;
- parameter FLASH_CTRL_MP_REGION_CFG4_OFFSET = 7'h 24;
- parameter FLASH_CTRL_MP_REGION_CFG5_OFFSET = 7'h 28;
- parameter FLASH_CTRL_MP_REGION_CFG6_OFFSET = 7'h 2c;
- parameter FLASH_CTRL_MP_REGION_CFG7_OFFSET = 7'h 30;
- parameter FLASH_CTRL_DEFAULT_REGION_OFFSET = 7'h 34;
- parameter FLASH_CTRL_MP_BANK_CFG_OFFSET = 7'h 38;
- parameter FLASH_CTRL_OP_STATUS_OFFSET = 7'h 3c;
- parameter FLASH_CTRL_STATUS_OFFSET = 7'h 40;
- parameter FLASH_CTRL_SCRATCH_OFFSET = 7'h 44;
- parameter FLASH_CTRL_FIFO_LVL_OFFSET = 7'h 48;
+ parameter FLASH_CTRL_REGION_CFG_REGWEN_OFFSET = 7'h 14;
+ parameter FLASH_CTRL_MP_REGION_CFG0_OFFSET = 7'h 18;
+ parameter FLASH_CTRL_MP_REGION_CFG1_OFFSET = 7'h 1c;
+ parameter FLASH_CTRL_MP_REGION_CFG2_OFFSET = 7'h 20;
+ parameter FLASH_CTRL_MP_REGION_CFG3_OFFSET = 7'h 24;
+ parameter FLASH_CTRL_MP_REGION_CFG4_OFFSET = 7'h 28;
+ parameter FLASH_CTRL_MP_REGION_CFG5_OFFSET = 7'h 2c;
+ parameter FLASH_CTRL_MP_REGION_CFG6_OFFSET = 7'h 30;
+ parameter FLASH_CTRL_MP_REGION_CFG7_OFFSET = 7'h 34;
+ parameter FLASH_CTRL_DEFAULT_REGION_OFFSET = 7'h 38;
+ parameter FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 7'h 3c;
+ parameter FLASH_CTRL_MP_BANK_CFG_OFFSET = 7'h 40;
+ parameter FLASH_CTRL_OP_STATUS_OFFSET = 7'h 44;
+ parameter FLASH_CTRL_STATUS_OFFSET = 7'h 48;
+ parameter FLASH_CTRL_SCRATCH_OFFSET = 7'h 4c;
+ parameter FLASH_CTRL_FIFO_LVL_OFFSET = 7'h 50;
// Window parameter
- parameter FLASH_CTRL_PROG_FIFO_OFFSET = 7'h 4c;
+ parameter FLASH_CTRL_PROG_FIFO_OFFSET = 7'h 54;
parameter FLASH_CTRL_PROG_FIFO_SIZE = 7'h 4;
- parameter FLASH_CTRL_RD_FIFO_OFFSET = 7'h 50;
+ parameter FLASH_CTRL_RD_FIFO_OFFSET = 7'h 58;
parameter FLASH_CTRL_RD_FIFO_SIZE = 7'h 4;
// Register Index
@@ -395,6 +399,7 @@
FLASH_CTRL_INTR_TEST,
FLASH_CTRL_CONTROL,
FLASH_CTRL_ADDR,
+ FLASH_CTRL_REGION_CFG_REGWEN,
FLASH_CTRL_MP_REGION_CFG0,
FLASH_CTRL_MP_REGION_CFG1,
FLASH_CTRL_MP_REGION_CFG2,
@@ -404,6 +409,7 @@
FLASH_CTRL_MP_REGION_CFG6,
FLASH_CTRL_MP_REGION_CFG7,
FLASH_CTRL_DEFAULT_REGION,
+ FLASH_CTRL_BANK_CFG_REGWEN,
FLASH_CTRL_MP_BANK_CFG,
FLASH_CTRL_OP_STATUS,
FLASH_CTRL_STATUS,
@@ -412,26 +418,28 @@
} flash_ctrl_id_e;
// Register width information to check illegal writes
- localparam logic [3:0] FLASH_CTRL_PERMIT [19] = '{
+ localparam logic [3:0] FLASH_CTRL_PERMIT [21] = '{
4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
4'b 1111, // index[ 3] FLASH_CTRL_CONTROL
4'b 1111, // index[ 4] FLASH_CTRL_ADDR
- 4'b 1111, // index[ 5] FLASH_CTRL_MP_REGION_CFG0
- 4'b 1111, // index[ 6] FLASH_CTRL_MP_REGION_CFG1
- 4'b 1111, // index[ 7] FLASH_CTRL_MP_REGION_CFG2
- 4'b 1111, // index[ 8] FLASH_CTRL_MP_REGION_CFG3
- 4'b 1111, // index[ 9] FLASH_CTRL_MP_REGION_CFG4
- 4'b 1111, // index[10] FLASH_CTRL_MP_REGION_CFG5
- 4'b 1111, // index[11] FLASH_CTRL_MP_REGION_CFG6
- 4'b 1111, // index[12] FLASH_CTRL_MP_REGION_CFG7
- 4'b 0001, // index[13] FLASH_CTRL_DEFAULT_REGION
- 4'b 0001, // index[14] FLASH_CTRL_MP_BANK_CFG
- 4'b 0001, // index[15] FLASH_CTRL_OP_STATUS
- 4'b 1111, // index[16] FLASH_CTRL_STATUS
- 4'b 1111, // index[17] FLASH_CTRL_SCRATCH
- 4'b 0011 // index[18] FLASH_CTRL_FIFO_LVL
+ 4'b 0001, // index[ 5] FLASH_CTRL_REGION_CFG_REGWEN
+ 4'b 1111, // index[ 6] FLASH_CTRL_MP_REGION_CFG0
+ 4'b 1111, // index[ 7] FLASH_CTRL_MP_REGION_CFG1
+ 4'b 1111, // index[ 8] FLASH_CTRL_MP_REGION_CFG2
+ 4'b 1111, // index[ 9] FLASH_CTRL_MP_REGION_CFG3
+ 4'b 1111, // index[10] FLASH_CTRL_MP_REGION_CFG4
+ 4'b 1111, // index[11] FLASH_CTRL_MP_REGION_CFG5
+ 4'b 1111, // index[12] FLASH_CTRL_MP_REGION_CFG6
+ 4'b 1111, // index[13] FLASH_CTRL_MP_REGION_CFG7
+ 4'b 0001, // index[14] FLASH_CTRL_DEFAULT_REGION
+ 4'b 0001, // index[15] FLASH_CTRL_BANK_CFG_REGWEN
+ 4'b 0001, // index[16] FLASH_CTRL_MP_BANK_CFG
+ 4'b 0001, // index[17] FLASH_CTRL_OP_STATUS
+ 4'b 1111, // index[18] FLASH_CTRL_STATUS
+ 4'b 1111, // index[19] FLASH_CTRL_SCRATCH
+ 4'b 0011 // index[20] FLASH_CTRL_FIFO_LVL
};
endpackage
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index 64b6ef1..c44f403 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -87,10 +87,10 @@
reg_steer = 2; // Default set to register
// TODO: Can below codes be unique case () inside ?
- if (tl_i.a_address[AW-1:0] >= 76 && tl_i.a_address[AW-1:0] < 80) begin
+ if (tl_i.a_address[AW-1:0] >= 84 && tl_i.a_address[AW-1:0] < 88) begin
reg_steer = 0;
end
- if (tl_i.a_address[AW-1:0] >= 80 && tl_i.a_address[AW-1:0] < 84) begin
+ if (tl_i.a_address[AW-1:0] >= 88 && tl_i.a_address[AW-1:0] < 92) begin
reg_steer = 1;
end
end
@@ -186,6 +186,30 @@
logic [31:0] addr_qs;
logic [31:0] addr_wd;
logic addr_we;
+ logic region_cfg_regwen_region0_qs;
+ logic region_cfg_regwen_region0_wd;
+ logic region_cfg_regwen_region0_we;
+ logic region_cfg_regwen_region1_qs;
+ logic region_cfg_regwen_region1_wd;
+ logic region_cfg_regwen_region1_we;
+ logic region_cfg_regwen_region2_qs;
+ logic region_cfg_regwen_region2_wd;
+ logic region_cfg_regwen_region2_we;
+ logic region_cfg_regwen_region3_qs;
+ logic region_cfg_regwen_region3_wd;
+ logic region_cfg_regwen_region3_we;
+ logic region_cfg_regwen_region4_qs;
+ logic region_cfg_regwen_region4_wd;
+ logic region_cfg_regwen_region4_we;
+ logic region_cfg_regwen_region5_qs;
+ logic region_cfg_regwen_region5_wd;
+ logic region_cfg_regwen_region5_we;
+ logic region_cfg_regwen_region6_qs;
+ logic region_cfg_regwen_region6_wd;
+ logic region_cfg_regwen_region6_we;
+ logic region_cfg_regwen_region7_qs;
+ logic region_cfg_regwen_region7_wd;
+ logic region_cfg_regwen_region7_we;
logic mp_region_cfg0_en0_qs;
logic mp_region_cfg0_en0_wd;
logic mp_region_cfg0_en0_we;
@@ -339,6 +363,12 @@
logic default_region_erase_en_qs;
logic default_region_erase_en_wd;
logic default_region_erase_en_we;
+ logic bank_cfg_regwen_bank0_qs;
+ logic bank_cfg_regwen_bank0_wd;
+ logic bank_cfg_regwen_bank0_we;
+ logic bank_cfg_regwen_bank1_qs;
+ logic bank_cfg_regwen_bank1_wd;
+ logic bank_cfg_regwen_bank1_we;
logic mp_bank_cfg_erase_en0_qs;
logic mp_bank_cfg_erase_en0_wd;
logic mp_bank_cfg_erase_en0_we;
@@ -943,6 +973,216 @@
);
+ // R[region_cfg_regwen]: V(False)
+
+ // F[region0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region0_we),
+ .wd (region_cfg_regwen_region0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region0_qs)
+ );
+
+
+ // F[region1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region1_we),
+ .wd (region_cfg_regwen_region1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region1_qs)
+ );
+
+
+ // F[region2]: 2:2
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region2_we),
+ .wd (region_cfg_regwen_region2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region2_qs)
+ );
+
+
+ // F[region3]: 3:3
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region3_we),
+ .wd (region_cfg_regwen_region3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region3_qs)
+ );
+
+
+ // F[region4]: 4:4
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region4_we),
+ .wd (region_cfg_regwen_region4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region4_qs)
+ );
+
+
+ // F[region5]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region5_we),
+ .wd (region_cfg_regwen_region5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region5_qs)
+ );
+
+
+ // F[region6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region6_we),
+ .wd (region_cfg_regwen_region6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region6_qs)
+ );
+
+
+ // F[region7]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_region_cfg_regwen_region7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (region_cfg_regwen_region7_we),
+ .wd (region_cfg_regwen_region7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (region_cfg_regwen_region7_qs)
+ );
+
+
// R[mp_region_cfg0]: V(False)
// F[en0]: 0:0
@@ -954,8 +1194,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg0_en0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg0_en0_we & region_cfg_regwen_region0_qs),
.wd (mp_region_cfg0_en0_wd),
// from internal hardware
@@ -980,8 +1220,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg0_rd_en0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg0_rd_en0_we & region_cfg_regwen_region0_qs),
.wd (mp_region_cfg0_rd_en0_wd),
// from internal hardware
@@ -1006,8 +1246,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg0_prog_en0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg0_prog_en0_we & region_cfg_regwen_region0_qs),
.wd (mp_region_cfg0_prog_en0_wd),
// from internal hardware
@@ -1032,8 +1272,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg0_erase_en0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg0_erase_en0_we & region_cfg_regwen_region0_qs),
.wd (mp_region_cfg0_erase_en0_wd),
// from internal hardware
@@ -1058,8 +1298,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg0_base0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg0_base0_we & region_cfg_regwen_region0_qs),
.wd (mp_region_cfg0_base0_wd),
// from internal hardware
@@ -1084,8 +1324,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg0_size0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg0_size0_we & region_cfg_regwen_region0_qs),
.wd (mp_region_cfg0_size0_wd),
// from internal hardware
@@ -1112,8 +1352,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg1_en1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg1_en1_we & region_cfg_regwen_region1_qs),
.wd (mp_region_cfg1_en1_wd),
// from internal hardware
@@ -1138,8 +1378,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg1_rd_en1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg1_rd_en1_we & region_cfg_regwen_region1_qs),
.wd (mp_region_cfg1_rd_en1_wd),
// from internal hardware
@@ -1164,8 +1404,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg1_prog_en1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg1_prog_en1_we & region_cfg_regwen_region1_qs),
.wd (mp_region_cfg1_prog_en1_wd),
// from internal hardware
@@ -1190,8 +1430,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg1_erase_en1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg1_erase_en1_we & region_cfg_regwen_region1_qs),
.wd (mp_region_cfg1_erase_en1_wd),
// from internal hardware
@@ -1216,8 +1456,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg1_base1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg1_base1_we & region_cfg_regwen_region1_qs),
.wd (mp_region_cfg1_base1_wd),
// from internal hardware
@@ -1242,8 +1482,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg1_size1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg1_size1_we & region_cfg_regwen_region1_qs),
.wd (mp_region_cfg1_size1_wd),
// from internal hardware
@@ -1270,8 +1510,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg2_en2_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg2_en2_we & region_cfg_regwen_region2_qs),
.wd (mp_region_cfg2_en2_wd),
// from internal hardware
@@ -1296,8 +1536,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg2_rd_en2_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg2_rd_en2_we & region_cfg_regwen_region2_qs),
.wd (mp_region_cfg2_rd_en2_wd),
// from internal hardware
@@ -1322,8 +1562,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg2_prog_en2_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg2_prog_en2_we & region_cfg_regwen_region2_qs),
.wd (mp_region_cfg2_prog_en2_wd),
// from internal hardware
@@ -1348,8 +1588,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg2_erase_en2_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg2_erase_en2_we & region_cfg_regwen_region2_qs),
.wd (mp_region_cfg2_erase_en2_wd),
// from internal hardware
@@ -1374,8 +1614,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg2_base2_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg2_base2_we & region_cfg_regwen_region2_qs),
.wd (mp_region_cfg2_base2_wd),
// from internal hardware
@@ -1400,8 +1640,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg2_size2_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg2_size2_we & region_cfg_regwen_region2_qs),
.wd (mp_region_cfg2_size2_wd),
// from internal hardware
@@ -1428,8 +1668,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg3_en3_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg3_en3_we & region_cfg_regwen_region3_qs),
.wd (mp_region_cfg3_en3_wd),
// from internal hardware
@@ -1454,8 +1694,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg3_rd_en3_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg3_rd_en3_we & region_cfg_regwen_region3_qs),
.wd (mp_region_cfg3_rd_en3_wd),
// from internal hardware
@@ -1480,8 +1720,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg3_prog_en3_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg3_prog_en3_we & region_cfg_regwen_region3_qs),
.wd (mp_region_cfg3_prog_en3_wd),
// from internal hardware
@@ -1506,8 +1746,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg3_erase_en3_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg3_erase_en3_we & region_cfg_regwen_region3_qs),
.wd (mp_region_cfg3_erase_en3_wd),
// from internal hardware
@@ -1532,8 +1772,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg3_base3_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg3_base3_we & region_cfg_regwen_region3_qs),
.wd (mp_region_cfg3_base3_wd),
// from internal hardware
@@ -1558,8 +1798,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg3_size3_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg3_size3_we & region_cfg_regwen_region3_qs),
.wd (mp_region_cfg3_size3_wd),
// from internal hardware
@@ -1586,8 +1826,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg4_en4_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg4_en4_we & region_cfg_regwen_region4_qs),
.wd (mp_region_cfg4_en4_wd),
// from internal hardware
@@ -1612,8 +1852,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg4_rd_en4_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg4_rd_en4_we & region_cfg_regwen_region4_qs),
.wd (mp_region_cfg4_rd_en4_wd),
// from internal hardware
@@ -1638,8 +1878,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg4_prog_en4_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg4_prog_en4_we & region_cfg_regwen_region4_qs),
.wd (mp_region_cfg4_prog_en4_wd),
// from internal hardware
@@ -1664,8 +1904,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg4_erase_en4_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg4_erase_en4_we & region_cfg_regwen_region4_qs),
.wd (mp_region_cfg4_erase_en4_wd),
// from internal hardware
@@ -1690,8 +1930,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg4_base4_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg4_base4_we & region_cfg_regwen_region4_qs),
.wd (mp_region_cfg4_base4_wd),
// from internal hardware
@@ -1716,8 +1956,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg4_size4_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg4_size4_we & region_cfg_regwen_region4_qs),
.wd (mp_region_cfg4_size4_wd),
// from internal hardware
@@ -1744,8 +1984,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg5_en5_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg5_en5_we & region_cfg_regwen_region5_qs),
.wd (mp_region_cfg5_en5_wd),
// from internal hardware
@@ -1770,8 +2010,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg5_rd_en5_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg5_rd_en5_we & region_cfg_regwen_region5_qs),
.wd (mp_region_cfg5_rd_en5_wd),
// from internal hardware
@@ -1796,8 +2036,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg5_prog_en5_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg5_prog_en5_we & region_cfg_regwen_region5_qs),
.wd (mp_region_cfg5_prog_en5_wd),
// from internal hardware
@@ -1822,8 +2062,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg5_erase_en5_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg5_erase_en5_we & region_cfg_regwen_region5_qs),
.wd (mp_region_cfg5_erase_en5_wd),
// from internal hardware
@@ -1848,8 +2088,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg5_base5_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg5_base5_we & region_cfg_regwen_region5_qs),
.wd (mp_region_cfg5_base5_wd),
// from internal hardware
@@ -1874,8 +2114,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg5_size5_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg5_size5_we & region_cfg_regwen_region5_qs),
.wd (mp_region_cfg5_size5_wd),
// from internal hardware
@@ -1902,8 +2142,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg6_en6_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg6_en6_we & region_cfg_regwen_region6_qs),
.wd (mp_region_cfg6_en6_wd),
// from internal hardware
@@ -1928,8 +2168,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg6_rd_en6_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg6_rd_en6_we & region_cfg_regwen_region6_qs),
.wd (mp_region_cfg6_rd_en6_wd),
// from internal hardware
@@ -1954,8 +2194,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg6_prog_en6_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg6_prog_en6_we & region_cfg_regwen_region6_qs),
.wd (mp_region_cfg6_prog_en6_wd),
// from internal hardware
@@ -1980,8 +2220,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg6_erase_en6_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg6_erase_en6_we & region_cfg_regwen_region6_qs),
.wd (mp_region_cfg6_erase_en6_wd),
// from internal hardware
@@ -2006,8 +2246,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg6_base6_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg6_base6_we & region_cfg_regwen_region6_qs),
.wd (mp_region_cfg6_base6_wd),
// from internal hardware
@@ -2032,8 +2272,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg6_size6_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg6_size6_we & region_cfg_regwen_region6_qs),
.wd (mp_region_cfg6_size6_wd),
// from internal hardware
@@ -2060,8 +2300,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg7_en7_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg7_en7_we & region_cfg_regwen_region7_qs),
.wd (mp_region_cfg7_en7_wd),
// from internal hardware
@@ -2086,8 +2326,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg7_rd_en7_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg7_rd_en7_we & region_cfg_regwen_region7_qs),
.wd (mp_region_cfg7_rd_en7_wd),
// from internal hardware
@@ -2112,8 +2352,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg7_prog_en7_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg7_prog_en7_we & region_cfg_regwen_region7_qs),
.wd (mp_region_cfg7_prog_en7_wd),
// from internal hardware
@@ -2138,8 +2378,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg7_erase_en7_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg7_erase_en7_we & region_cfg_regwen_region7_qs),
.wd (mp_region_cfg7_erase_en7_wd),
// from internal hardware
@@ -2164,8 +2404,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg7_base7_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg7_base7_we & region_cfg_regwen_region7_qs),
.wd (mp_region_cfg7_base7_wd),
// from internal hardware
@@ -2190,8 +2430,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_region_cfg7_size7_we),
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg7_size7_we & region_cfg_regwen_region7_qs),
.wd (mp_region_cfg7_size7_wd),
// from internal hardware
@@ -2287,6 +2527,60 @@
);
+ // R[bank_cfg_regwen]: V(False)
+
+ // F[bank0]: 0:0
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank_cfg_regwen_bank0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank_cfg_regwen_bank0_we),
+ .wd (bank_cfg_regwen_bank0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank_cfg_regwen_bank0_qs)
+ );
+
+
+ // F[bank1]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_bank_cfg_regwen_bank1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (bank_cfg_regwen_bank1_we),
+ .wd (bank_cfg_regwen_bank1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (bank_cfg_regwen_bank1_qs)
+ );
+
+
// R[mp_bank_cfg]: V(False)
// F[erase_en0]: 1:1
@@ -2298,8 +2592,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_bank_cfg_erase_en0_we),
+ // from register interface (qualified with register enable)
+ .we (mp_bank_cfg_erase_en0_we & bank_cfg_regwen_bank_qs),
.wd (mp_bank_cfg_erase_en0_wd),
// from internal hardware
@@ -2324,8 +2618,8 @@
.clk_i (clk_i ),
.rst_ni (rst_ni ),
- // from register interface
- .we (mp_bank_cfg_erase_en1_we),
+ // from register interface (qualified with register enable)
+ .we (mp_bank_cfg_erase_en1_we & bank_cfg_regwen_bank_qs),
.wd (mp_bank_cfg_erase_en1_wd),
// from internal hardware
@@ -2584,7 +2878,7 @@
- logic [18:0] addr_hit;
+ logic [20:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
@@ -2592,20 +2886,22 @@
addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
addr_hit[ 3] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
addr_hit[ 4] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
- addr_hit[ 5] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET);
- addr_hit[ 6] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET);
- addr_hit[ 7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET);
- addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET);
- addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET);
- addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET);
- addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET);
- addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET);
- addr_hit[13] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
- addr_hit[14] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
- addr_hit[15] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
- addr_hit[16] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
- addr_hit[17] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
- addr_hit[18] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
+ addr_hit[ 5] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_OFFSET);
+ addr_hit[ 6] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET);
+ addr_hit[ 7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET);
+ addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET);
+ addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET);
+ addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET);
+ addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET);
+ addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET);
+ addr_hit[13] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET);
+ addr_hit[14] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
+ addr_hit[15] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
+ addr_hit[16] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
+ addr_hit[17] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
+ addr_hit[18] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
+ addr_hit[19] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
+ addr_hit[20] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -2632,6 +2928,8 @@
if (addr_hit[16] && reg_we && (FLASH_CTRL_PERMIT[16] != (FLASH_CTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[17] && reg_we && (FLASH_CTRL_PERMIT[17] != (FLASH_CTRL_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[18] && reg_we && (FLASH_CTRL_PERMIT[18] != (FLASH_CTRL_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (FLASH_CTRL_PERMIT[19] != (FLASH_CTRL_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[20] && reg_we && (FLASH_CTRL_PERMIT[20] != (FLASH_CTRL_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
@@ -2706,192 +3004,222 @@
assign addr_we = addr_hit[4] & reg_we & ~wr_err;
assign addr_wd = reg_wdata[31:0];
- assign mp_region_cfg0_en0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region0_wd = reg_wdata[0];
+
+ assign region_cfg_regwen_region1_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region1_wd = reg_wdata[1];
+
+ assign region_cfg_regwen_region2_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region2_wd = reg_wdata[2];
+
+ assign region_cfg_regwen_region3_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region3_wd = reg_wdata[3];
+
+ assign region_cfg_regwen_region4_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region4_wd = reg_wdata[4];
+
+ assign region_cfg_regwen_region5_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region5_wd = reg_wdata[5];
+
+ assign region_cfg_regwen_region6_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region6_wd = reg_wdata[6];
+
+ assign region_cfg_regwen_region7_we = addr_hit[5] & reg_we & ~wr_err;
+ assign region_cfg_regwen_region7_wd = reg_wdata[7];
+
+ assign mp_region_cfg0_en0_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg0_en0_wd = reg_wdata[0];
- assign mp_region_cfg0_rd_en0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign mp_region_cfg0_rd_en0_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg0_rd_en0_wd = reg_wdata[1];
- assign mp_region_cfg0_prog_en0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign mp_region_cfg0_prog_en0_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg0_prog_en0_wd = reg_wdata[2];
- assign mp_region_cfg0_erase_en0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign mp_region_cfg0_erase_en0_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg0_erase_en0_wd = reg_wdata[3];
- assign mp_region_cfg0_base0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign mp_region_cfg0_base0_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg0_base0_wd = reg_wdata[12:4];
- assign mp_region_cfg0_size0_we = addr_hit[5] & reg_we & ~wr_err;
+ assign mp_region_cfg0_size0_we = addr_hit[6] & reg_we & ~wr_err;
assign mp_region_cfg0_size0_wd = reg_wdata[24:16];
- assign mp_region_cfg1_en1_we = addr_hit[6] & reg_we & ~wr_err;
+ assign mp_region_cfg1_en1_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg1_en1_wd = reg_wdata[0];
- assign mp_region_cfg1_rd_en1_we = addr_hit[6] & reg_we & ~wr_err;
+ assign mp_region_cfg1_rd_en1_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg1_rd_en1_wd = reg_wdata[1];
- assign mp_region_cfg1_prog_en1_we = addr_hit[6] & reg_we & ~wr_err;
+ assign mp_region_cfg1_prog_en1_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg1_prog_en1_wd = reg_wdata[2];
- assign mp_region_cfg1_erase_en1_we = addr_hit[6] & reg_we & ~wr_err;
+ assign mp_region_cfg1_erase_en1_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg1_erase_en1_wd = reg_wdata[3];
- assign mp_region_cfg1_base1_we = addr_hit[6] & reg_we & ~wr_err;
+ assign mp_region_cfg1_base1_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg1_base1_wd = reg_wdata[12:4];
- assign mp_region_cfg1_size1_we = addr_hit[6] & reg_we & ~wr_err;
+ assign mp_region_cfg1_size1_we = addr_hit[7] & reg_we & ~wr_err;
assign mp_region_cfg1_size1_wd = reg_wdata[24:16];
- assign mp_region_cfg2_en2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign mp_region_cfg2_en2_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg2_en2_wd = reg_wdata[0];
- assign mp_region_cfg2_rd_en2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign mp_region_cfg2_rd_en2_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg2_rd_en2_wd = reg_wdata[1];
- assign mp_region_cfg2_prog_en2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign mp_region_cfg2_prog_en2_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg2_prog_en2_wd = reg_wdata[2];
- assign mp_region_cfg2_erase_en2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign mp_region_cfg2_erase_en2_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg2_erase_en2_wd = reg_wdata[3];
- assign mp_region_cfg2_base2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign mp_region_cfg2_base2_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg2_base2_wd = reg_wdata[12:4];
- assign mp_region_cfg2_size2_we = addr_hit[7] & reg_we & ~wr_err;
+ assign mp_region_cfg2_size2_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg2_size2_wd = reg_wdata[24:16];
- assign mp_region_cfg3_en3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mp_region_cfg3_en3_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg3_en3_wd = reg_wdata[0];
- assign mp_region_cfg3_rd_en3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mp_region_cfg3_rd_en3_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg3_rd_en3_wd = reg_wdata[1];
- assign mp_region_cfg3_prog_en3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mp_region_cfg3_prog_en3_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg3_prog_en3_wd = reg_wdata[2];
- assign mp_region_cfg3_erase_en3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mp_region_cfg3_erase_en3_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg3_erase_en3_wd = reg_wdata[3];
- assign mp_region_cfg3_base3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mp_region_cfg3_base3_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg3_base3_wd = reg_wdata[12:4];
- assign mp_region_cfg3_size3_we = addr_hit[8] & reg_we & ~wr_err;
+ assign mp_region_cfg3_size3_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg3_size3_wd = reg_wdata[24:16];
- assign mp_region_cfg4_en4_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mp_region_cfg4_en4_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg4_en4_wd = reg_wdata[0];
- assign mp_region_cfg4_rd_en4_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mp_region_cfg4_rd_en4_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg4_rd_en4_wd = reg_wdata[1];
- assign mp_region_cfg4_prog_en4_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mp_region_cfg4_prog_en4_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg4_prog_en4_wd = reg_wdata[2];
- assign mp_region_cfg4_erase_en4_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mp_region_cfg4_erase_en4_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg4_erase_en4_wd = reg_wdata[3];
- assign mp_region_cfg4_base4_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mp_region_cfg4_base4_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg4_base4_wd = reg_wdata[12:4];
- assign mp_region_cfg4_size4_we = addr_hit[9] & reg_we & ~wr_err;
+ assign mp_region_cfg4_size4_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg4_size4_wd = reg_wdata[24:16];
- assign mp_region_cfg5_en5_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mp_region_cfg5_en5_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg5_en5_wd = reg_wdata[0];
- assign mp_region_cfg5_rd_en5_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mp_region_cfg5_rd_en5_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg5_rd_en5_wd = reg_wdata[1];
- assign mp_region_cfg5_prog_en5_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mp_region_cfg5_prog_en5_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg5_prog_en5_wd = reg_wdata[2];
- assign mp_region_cfg5_erase_en5_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mp_region_cfg5_erase_en5_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg5_erase_en5_wd = reg_wdata[3];
- assign mp_region_cfg5_base5_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mp_region_cfg5_base5_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg5_base5_wd = reg_wdata[12:4];
- assign mp_region_cfg5_size5_we = addr_hit[10] & reg_we & ~wr_err;
+ assign mp_region_cfg5_size5_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg5_size5_wd = reg_wdata[24:16];
- assign mp_region_cfg6_en6_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mp_region_cfg6_en6_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg6_en6_wd = reg_wdata[0];
- assign mp_region_cfg6_rd_en6_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mp_region_cfg6_rd_en6_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg6_rd_en6_wd = reg_wdata[1];
- assign mp_region_cfg6_prog_en6_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mp_region_cfg6_prog_en6_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg6_prog_en6_wd = reg_wdata[2];
- assign mp_region_cfg6_erase_en6_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mp_region_cfg6_erase_en6_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg6_erase_en6_wd = reg_wdata[3];
- assign mp_region_cfg6_base6_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mp_region_cfg6_base6_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg6_base6_wd = reg_wdata[12:4];
- assign mp_region_cfg6_size6_we = addr_hit[11] & reg_we & ~wr_err;
+ assign mp_region_cfg6_size6_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg6_size6_wd = reg_wdata[24:16];
- assign mp_region_cfg7_en7_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mp_region_cfg7_en7_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg7_en7_wd = reg_wdata[0];
- assign mp_region_cfg7_rd_en7_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mp_region_cfg7_rd_en7_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg7_rd_en7_wd = reg_wdata[1];
- assign mp_region_cfg7_prog_en7_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mp_region_cfg7_prog_en7_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg7_prog_en7_wd = reg_wdata[2];
- assign mp_region_cfg7_erase_en7_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mp_region_cfg7_erase_en7_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg7_erase_en7_wd = reg_wdata[3];
- assign mp_region_cfg7_base7_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mp_region_cfg7_base7_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg7_base7_wd = reg_wdata[12:4];
- assign mp_region_cfg7_size7_we = addr_hit[12] & reg_we & ~wr_err;
+ assign mp_region_cfg7_size7_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg7_size7_wd = reg_wdata[24:16];
- assign default_region_rd_en_we = addr_hit[13] & reg_we & ~wr_err;
+ assign default_region_rd_en_we = addr_hit[14] & reg_we & ~wr_err;
assign default_region_rd_en_wd = reg_wdata[0];
- assign default_region_prog_en_we = addr_hit[13] & reg_we & ~wr_err;
+ assign default_region_prog_en_we = addr_hit[14] & reg_we & ~wr_err;
assign default_region_prog_en_wd = reg_wdata[1];
- assign default_region_erase_en_we = addr_hit[13] & reg_we & ~wr_err;
+ assign default_region_erase_en_we = addr_hit[14] & reg_we & ~wr_err;
assign default_region_erase_en_wd = reg_wdata[2];
- assign mp_bank_cfg_erase_en0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign bank_cfg_regwen_bank0_we = addr_hit[15] & reg_we & ~wr_err;
+ assign bank_cfg_regwen_bank0_wd = reg_wdata[0];
+
+ assign bank_cfg_regwen_bank1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign bank_cfg_regwen_bank1_wd = reg_wdata[1];
+
+ assign mp_bank_cfg_erase_en0_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en0_wd = reg_wdata[1];
- assign mp_bank_cfg_erase_en1_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_bank_cfg_erase_en1_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_bank_cfg_erase_en1_wd = reg_wdata[2];
- assign op_status_done_we = addr_hit[15] & reg_we & ~wr_err;
+ assign op_status_done_we = addr_hit[17] & reg_we & ~wr_err;
assign op_status_done_wd = reg_wdata[0];
- assign op_status_err_we = addr_hit[15] & reg_we & ~wr_err;
+ assign op_status_err_we = addr_hit[17] & reg_we & ~wr_err;
assign op_status_err_wd = reg_wdata[1];
- assign status_rd_full_re = addr_hit[16] && reg_re;
+ assign status_rd_full_re = addr_hit[18] && reg_re;
- assign status_rd_empty_re = addr_hit[16] && reg_re;
+ assign status_rd_empty_re = addr_hit[18] && reg_re;
- assign status_prog_full_re = addr_hit[16] && reg_re;
+ assign status_prog_full_re = addr_hit[18] && reg_re;
- assign status_prog_empty_re = addr_hit[16] && reg_re;
+ assign status_prog_empty_re = addr_hit[18] && reg_re;
- assign status_init_wip_re = addr_hit[16] && reg_re;
+ assign status_init_wip_re = addr_hit[18] && reg_re;
- assign status_error_page_re = addr_hit[16] && reg_re;
+ assign status_error_page_re = addr_hit[18] && reg_re;
- assign status_error_bank_re = addr_hit[16] && reg_re;
+ assign status_error_bank_re = addr_hit[18] && reg_re;
- assign scratch_we = addr_hit[17] & reg_we & ~wr_err;
+ assign scratch_we = addr_hit[19] & reg_we & ~wr_err;
assign scratch_wd = reg_wdata[31:0];
- assign fifo_lvl_prog_we = addr_hit[18] & reg_we & ~wr_err;
+ assign fifo_lvl_prog_we = addr_hit[20] & reg_we & ~wr_err;
assign fifo_lvl_prog_wd = reg_wdata[4:0];
- assign fifo_lvl_rd_we = addr_hit[18] & reg_we & ~wr_err;
+ assign fifo_lvl_rd_we = addr_hit[20] & reg_we & ~wr_err;
assign fifo_lvl_rd_wd = reg_wdata[12:8];
// Read data return
@@ -2938,6 +3266,17 @@
end
addr_hit[5]: begin
+ reg_rdata_next[0] = region_cfg_regwen_region0_qs;
+ reg_rdata_next[1] = region_cfg_regwen_region1_qs;
+ reg_rdata_next[2] = region_cfg_regwen_region2_qs;
+ reg_rdata_next[3] = region_cfg_regwen_region3_qs;
+ reg_rdata_next[4] = region_cfg_regwen_region4_qs;
+ reg_rdata_next[5] = region_cfg_regwen_region5_qs;
+ reg_rdata_next[6] = region_cfg_regwen_region6_qs;
+ reg_rdata_next[7] = region_cfg_regwen_region7_qs;
+ end
+
+ addr_hit[6]: begin
reg_rdata_next[0] = mp_region_cfg0_en0_qs;
reg_rdata_next[1] = mp_region_cfg0_rd_en0_qs;
reg_rdata_next[2] = mp_region_cfg0_prog_en0_qs;
@@ -2946,7 +3285,7 @@
reg_rdata_next[24:16] = mp_region_cfg0_size0_qs;
end
- addr_hit[6]: begin
+ addr_hit[7]: begin
reg_rdata_next[0] = mp_region_cfg1_en1_qs;
reg_rdata_next[1] = mp_region_cfg1_rd_en1_qs;
reg_rdata_next[2] = mp_region_cfg1_prog_en1_qs;
@@ -2955,7 +3294,7 @@
reg_rdata_next[24:16] = mp_region_cfg1_size1_qs;
end
- addr_hit[7]: begin
+ addr_hit[8]: begin
reg_rdata_next[0] = mp_region_cfg2_en2_qs;
reg_rdata_next[1] = mp_region_cfg2_rd_en2_qs;
reg_rdata_next[2] = mp_region_cfg2_prog_en2_qs;
@@ -2964,7 +3303,7 @@
reg_rdata_next[24:16] = mp_region_cfg2_size2_qs;
end
- addr_hit[8]: begin
+ addr_hit[9]: begin
reg_rdata_next[0] = mp_region_cfg3_en3_qs;
reg_rdata_next[1] = mp_region_cfg3_rd_en3_qs;
reg_rdata_next[2] = mp_region_cfg3_prog_en3_qs;
@@ -2973,7 +3312,7 @@
reg_rdata_next[24:16] = mp_region_cfg3_size3_qs;
end
- addr_hit[9]: begin
+ addr_hit[10]: begin
reg_rdata_next[0] = mp_region_cfg4_en4_qs;
reg_rdata_next[1] = mp_region_cfg4_rd_en4_qs;
reg_rdata_next[2] = mp_region_cfg4_prog_en4_qs;
@@ -2982,7 +3321,7 @@
reg_rdata_next[24:16] = mp_region_cfg4_size4_qs;
end
- addr_hit[10]: begin
+ addr_hit[11]: begin
reg_rdata_next[0] = mp_region_cfg5_en5_qs;
reg_rdata_next[1] = mp_region_cfg5_rd_en5_qs;
reg_rdata_next[2] = mp_region_cfg5_prog_en5_qs;
@@ -2991,7 +3330,7 @@
reg_rdata_next[24:16] = mp_region_cfg5_size5_qs;
end
- addr_hit[11]: begin
+ addr_hit[12]: begin
reg_rdata_next[0] = mp_region_cfg6_en6_qs;
reg_rdata_next[1] = mp_region_cfg6_rd_en6_qs;
reg_rdata_next[2] = mp_region_cfg6_prog_en6_qs;
@@ -3000,7 +3339,7 @@
reg_rdata_next[24:16] = mp_region_cfg6_size6_qs;
end
- addr_hit[12]: begin
+ addr_hit[13]: begin
reg_rdata_next[0] = mp_region_cfg7_en7_qs;
reg_rdata_next[1] = mp_region_cfg7_rd_en7_qs;
reg_rdata_next[2] = mp_region_cfg7_prog_en7_qs;
@@ -3009,23 +3348,28 @@
reg_rdata_next[24:16] = mp_region_cfg7_size7_qs;
end
- addr_hit[13]: begin
+ addr_hit[14]: begin
reg_rdata_next[0] = default_region_rd_en_qs;
reg_rdata_next[1] = default_region_prog_en_qs;
reg_rdata_next[2] = default_region_erase_en_qs;
end
- addr_hit[14]: begin
+ addr_hit[15]: begin
+ reg_rdata_next[0] = bank_cfg_regwen_bank0_qs;
+ reg_rdata_next[1] = bank_cfg_regwen_bank1_qs;
+ end
+
+ addr_hit[16]: begin
reg_rdata_next[1] = mp_bank_cfg_erase_en0_qs;
reg_rdata_next[2] = mp_bank_cfg_erase_en1_qs;
end
- addr_hit[15]: begin
+ addr_hit[17]: begin
reg_rdata_next[0] = op_status_done_qs;
reg_rdata_next[1] = op_status_err_qs;
end
- addr_hit[16]: begin
+ addr_hit[18]: begin
reg_rdata_next[0] = status_rd_full_qs;
reg_rdata_next[1] = status_rd_empty_qs;
reg_rdata_next[2] = status_prog_full_qs;
@@ -3035,11 +3379,11 @@
reg_rdata_next[17] = status_error_bank_qs;
end
- addr_hit[17]: begin
+ addr_hit[19]: begin
reg_rdata_next[31:0] = scratch_qs;
end
- addr_hit[18]: begin
+ addr_hit[20]: begin
reg_rdata_next[4:0] = fifo_lvl_prog_qs;
reg_rdata_next[12:8] = fifo_lvl_rd_qs;
end
diff --git a/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h b/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h
index 54dba3e..13cfa46 100644
--- a/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h
+++ b/hw/ip/flash_ctrl/sw/flash_ctrl_regs.h
@@ -53,8 +53,19 @@
// Address for flash operation
#define FLASH_CTRL_ADDR(id) (FLASH_CTRL##id##_BASE_ADDR + 0x10)
+// Memory region registers configuration enable.
+#define FLASH_CTRL_REGION_CFG_REGWEN(id) (FLASH_CTRL##id##_BASE_ADDR + 0x14)
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION0 0
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION1 1
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION2 2
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION3 3
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION4 4
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION5 5
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION6 6
+#define FLASH_CTRL_REGION_CFG_REGWEN_REGION7 7
+
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG0(id) (FLASH_CTRL##id##_BASE_ADDR + 0x14)
+#define FLASH_CTRL_MP_REGION_CFG0(id) (FLASH_CTRL##id##_BASE_ADDR + 0x18)
#define FLASH_CTRL_MP_REGION_CFG0_EN0 0
#define FLASH_CTRL_MP_REGION_CFG0_RD_EN0 1
#define FLASH_CTRL_MP_REGION_CFG0_PROG_EN0 2
@@ -65,7 +76,7 @@
#define FLASH_CTRL_MP_REGION_CFG0_SIZE0_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG1(id) (FLASH_CTRL##id##_BASE_ADDR + 0x18)
+#define FLASH_CTRL_MP_REGION_CFG1(id) (FLASH_CTRL##id##_BASE_ADDR + 0x1c)
#define FLASH_CTRL_MP_REGION_CFG1_EN1 0
#define FLASH_CTRL_MP_REGION_CFG1_RD_EN1 1
#define FLASH_CTRL_MP_REGION_CFG1_PROG_EN1 2
@@ -76,7 +87,7 @@
#define FLASH_CTRL_MP_REGION_CFG1_SIZE1_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG2(id) (FLASH_CTRL##id##_BASE_ADDR + 0x1c)
+#define FLASH_CTRL_MP_REGION_CFG2(id) (FLASH_CTRL##id##_BASE_ADDR + 0x20)
#define FLASH_CTRL_MP_REGION_CFG2_EN2 0
#define FLASH_CTRL_MP_REGION_CFG2_RD_EN2 1
#define FLASH_CTRL_MP_REGION_CFG2_PROG_EN2 2
@@ -87,7 +98,7 @@
#define FLASH_CTRL_MP_REGION_CFG2_SIZE2_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG3(id) (FLASH_CTRL##id##_BASE_ADDR + 0x20)
+#define FLASH_CTRL_MP_REGION_CFG3(id) (FLASH_CTRL##id##_BASE_ADDR + 0x24)
#define FLASH_CTRL_MP_REGION_CFG3_EN3 0
#define FLASH_CTRL_MP_REGION_CFG3_RD_EN3 1
#define FLASH_CTRL_MP_REGION_CFG3_PROG_EN3 2
@@ -98,7 +109,7 @@
#define FLASH_CTRL_MP_REGION_CFG3_SIZE3_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG4(id) (FLASH_CTRL##id##_BASE_ADDR + 0x24)
+#define FLASH_CTRL_MP_REGION_CFG4(id) (FLASH_CTRL##id##_BASE_ADDR + 0x28)
#define FLASH_CTRL_MP_REGION_CFG4_EN4 0
#define FLASH_CTRL_MP_REGION_CFG4_RD_EN4 1
#define FLASH_CTRL_MP_REGION_CFG4_PROG_EN4 2
@@ -109,7 +120,7 @@
#define FLASH_CTRL_MP_REGION_CFG4_SIZE4_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG5(id) (FLASH_CTRL##id##_BASE_ADDR + 0x28)
+#define FLASH_CTRL_MP_REGION_CFG5(id) (FLASH_CTRL##id##_BASE_ADDR + 0x2c)
#define FLASH_CTRL_MP_REGION_CFG5_EN5 0
#define FLASH_CTRL_MP_REGION_CFG5_RD_EN5 1
#define FLASH_CTRL_MP_REGION_CFG5_PROG_EN5 2
@@ -120,7 +131,7 @@
#define FLASH_CTRL_MP_REGION_CFG5_SIZE5_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG6(id) (FLASH_CTRL##id##_BASE_ADDR + 0x2c)
+#define FLASH_CTRL_MP_REGION_CFG6(id) (FLASH_CTRL##id##_BASE_ADDR + 0x30)
#define FLASH_CTRL_MP_REGION_CFG6_EN6 0
#define FLASH_CTRL_MP_REGION_CFG6_RD_EN6 1
#define FLASH_CTRL_MP_REGION_CFG6_PROG_EN6 2
@@ -131,7 +142,7 @@
#define FLASH_CTRL_MP_REGION_CFG6_SIZE6_OFFSET 16
// Memory protection configuration
-#define FLASH_CTRL_MP_REGION_CFG7(id) (FLASH_CTRL##id##_BASE_ADDR + 0x30)
+#define FLASH_CTRL_MP_REGION_CFG7(id) (FLASH_CTRL##id##_BASE_ADDR + 0x34)
#define FLASH_CTRL_MP_REGION_CFG7_EN7 0
#define FLASH_CTRL_MP_REGION_CFG7_RD_EN7 1
#define FLASH_CTRL_MP_REGION_CFG7_PROG_EN7 2
@@ -142,23 +153,28 @@
#define FLASH_CTRL_MP_REGION_CFG7_SIZE7_OFFSET 16
// Default region permissions
-#define FLASH_CTRL_DEFAULT_REGION(id) (FLASH_CTRL##id##_BASE_ADDR + 0x34)
+#define FLASH_CTRL_DEFAULT_REGION(id) (FLASH_CTRL##id##_BASE_ADDR + 0x38)
#define FLASH_CTRL_DEFAULT_REGION_RD_EN 0
#define FLASH_CTRL_DEFAULT_REGION_PROG_EN 1
#define FLASH_CTRL_DEFAULT_REGION_ERASE_EN 2
+// Bank configuration registers configuration enable.
+#define FLASH_CTRL_BANK_CFG_REGWEN(id) (FLASH_CTRL##id##_BASE_ADDR + 0x3c)
+#define FLASH_CTRL_BANK_CFG_REGWEN_BANK0 0
+#define FLASH_CTRL_BANK_CFG_REGWEN_BANK1 1
+
// Memory protect bank configuration
-#define FLASH_CTRL_MP_BANK_CFG(id) (FLASH_CTRL##id##_BASE_ADDR + 0x38)
+#define FLASH_CTRL_MP_BANK_CFG(id) (FLASH_CTRL##id##_BASE_ADDR + 0x40)
#define FLASH_CTRL_MP_BANK_CFG_ERASE_EN0 1
#define FLASH_CTRL_MP_BANK_CFG_ERASE_EN1 2
// Flash Operation Status
-#define FLASH_CTRL_OP_STATUS(id) (FLASH_CTRL##id##_BASE_ADDR + 0x3c)
+#define FLASH_CTRL_OP_STATUS(id) (FLASH_CTRL##id##_BASE_ADDR + 0x44)
#define FLASH_CTRL_OP_STATUS_DONE 0
#define FLASH_CTRL_OP_STATUS_ERR 1
// Flash Controller Status
-#define FLASH_CTRL_STATUS(id) (FLASH_CTRL##id##_BASE_ADDR + 0x40)
+#define FLASH_CTRL_STATUS(id) (FLASH_CTRL##id##_BASE_ADDR + 0x48)
#define FLASH_CTRL_STATUS_RD_FULL 0
#define FLASH_CTRL_STATUS_RD_EMPTY 1
#define FLASH_CTRL_STATUS_PROG_FULL 2
@@ -169,21 +185,21 @@
#define FLASH_CTRL_STATUS_ERROR_BANK 17
// Flash Controller Scratch
-#define FLASH_CTRL_SCRATCH(id) (FLASH_CTRL##id##_BASE_ADDR + 0x44)
+#define FLASH_CTRL_SCRATCH(id) (FLASH_CTRL##id##_BASE_ADDR + 0x4c)
// Programmable depth where fifos should generate interrupts
-#define FLASH_CTRL_FIFO_LVL(id) (FLASH_CTRL##id##_BASE_ADDR + 0x48)
+#define FLASH_CTRL_FIFO_LVL(id) (FLASH_CTRL##id##_BASE_ADDR + 0x50)
#define FLASH_CTRL_FIFO_LVL_PROG_MASK 0x1f
#define FLASH_CTRL_FIFO_LVL_PROG_OFFSET 0
#define FLASH_CTRL_FIFO_LVL_RD_MASK 0x1f
#define FLASH_CTRL_FIFO_LVL_RD_OFFSET 8
// Memory area: Flash program fifo.
-#define FLASH_CTRL_PROG_FIFO(id) (FLASH_CTRL##id##_BASE_ADDR + 0x4c)
+#define FLASH_CTRL_PROG_FIFO(id) (FLASH_CTRL##id##_BASE_ADDR + 0x54)
#define FLASH_CTRL_PROG_FIFO_SIZE_WORDS 1
#define FLASH_CTRL_PROG_FIFO_SIZE_BYTES 4
// Memory area: Flash read fifo.
-#define FLASH_CTRL_RD_FIFO(id) (FLASH_CTRL##id##_BASE_ADDR + 0x50)
+#define FLASH_CTRL_RD_FIFO(id) (FLASH_CTRL##id##_BASE_ADDR + 0x58)
#define FLASH_CTRL_RD_FIFO_SIZE_WORDS 1
#define FLASH_CTRL_RD_FIFO_SIZE_BYTES 4
#endif // _FLASH_CTRL_REG_DEFS_
diff --git a/hw/top_earlgrey/dv/env/chip_reg_block.sv b/hw/top_earlgrey/dv/env/chip_reg_block.sv
index c89bf67..46f842c 100644
--- a/hw/top_earlgrey/dv/env/chip_reg_block.sv
+++ b/hw/top_earlgrey/dv/env/chip_reg_block.sv
@@ -6,6 +6,74 @@
// Do Not Edit directly
// Forward declare all register/memory/block classes
+typedef class spi_device_reg_intr_state;
+typedef class spi_device_reg_intr_enable;
+typedef class spi_device_reg_intr_test;
+typedef class spi_device_reg_control;
+typedef class spi_device_reg_cfg;
+typedef class spi_device_reg_fifo_level;
+typedef class spi_device_reg_async_fifo_level;
+typedef class spi_device_reg_status;
+typedef class spi_device_reg_rxf_ptr;
+typedef class spi_device_reg_txf_ptr;
+typedef class spi_device_reg_rxf_addr;
+typedef class spi_device_reg_txf_addr;
+typedef class spi_device_mem_buffer;
+typedef class spi_device_reg_block;
+
+typedef class flash_ctrl_reg_intr_state;
+typedef class flash_ctrl_reg_intr_enable;
+typedef class flash_ctrl_reg_intr_test;
+typedef class flash_ctrl_reg_control;
+typedef class flash_ctrl_reg_addr;
+typedef class flash_ctrl_reg_region_cfg_regwen;
+typedef class flash_ctrl_reg_mp_region_cfg0;
+typedef class flash_ctrl_reg_mp_region_cfg1;
+typedef class flash_ctrl_reg_mp_region_cfg2;
+typedef class flash_ctrl_reg_mp_region_cfg3;
+typedef class flash_ctrl_reg_mp_region_cfg4;
+typedef class flash_ctrl_reg_mp_region_cfg5;
+typedef class flash_ctrl_reg_mp_region_cfg6;
+typedef class flash_ctrl_reg_mp_region_cfg7;
+typedef class flash_ctrl_reg_default_region;
+typedef class flash_ctrl_reg_bank_cfg_regwen;
+typedef class flash_ctrl_reg_mp_bank_cfg;
+typedef class flash_ctrl_reg_op_status;
+typedef class flash_ctrl_reg_status;
+typedef class flash_ctrl_reg_scratch;
+typedef class flash_ctrl_reg_fifo_lvl;
+typedef class flash_ctrl_mem_prog_fifo;
+typedef class flash_ctrl_mem_rd_fifo;
+typedef class flash_ctrl_reg_block;
+
+typedef class rv_timer_reg_ctrl;
+typedef class rv_timer_reg_cfg0;
+typedef class rv_timer_reg_timer_v_lower0;
+typedef class rv_timer_reg_timer_v_upper0;
+typedef class rv_timer_reg_compare_lower0_0;
+typedef class rv_timer_reg_compare_upper0_0;
+typedef class rv_timer_reg_intr_enable0;
+typedef class rv_timer_reg_intr_state0;
+typedef class rv_timer_reg_intr_test0;
+typedef class rv_timer_reg_block;
+
+typedef class gpio_reg_intr_state;
+typedef class gpio_reg_intr_enable;
+typedef class gpio_reg_intr_test;
+typedef class gpio_reg_data_in;
+typedef class gpio_reg_direct_out;
+typedef class gpio_reg_masked_out_lower;
+typedef class gpio_reg_masked_out_upper;
+typedef class gpio_reg_direct_oe;
+typedef class gpio_reg_masked_oe_lower;
+typedef class gpio_reg_masked_oe_upper;
+typedef class gpio_reg_intr_ctrl_en_rising;
+typedef class gpio_reg_intr_ctrl_en_falling;
+typedef class gpio_reg_intr_ctrl_en_lvlhigh;
+typedef class gpio_reg_intr_ctrl_en_lvllow;
+typedef class gpio_reg_ctrl_en_input_filter;
+typedef class gpio_reg_block;
+
typedef class hmac_reg_intr_state;
typedef class hmac_reg_intr_enable;
typedef class hmac_reg_intr_test;
@@ -34,46 +102,6 @@
typedef class hmac_mem_msg_fifo;
typedef class hmac_reg_block;
-typedef class gpio_reg_intr_state;
-typedef class gpio_reg_intr_enable;
-typedef class gpio_reg_intr_test;
-typedef class gpio_reg_data_in;
-typedef class gpio_reg_direct_out;
-typedef class gpio_reg_masked_out_lower;
-typedef class gpio_reg_masked_out_upper;
-typedef class gpio_reg_direct_oe;
-typedef class gpio_reg_masked_oe_lower;
-typedef class gpio_reg_masked_oe_upper;
-typedef class gpio_reg_intr_ctrl_en_rising;
-typedef class gpio_reg_intr_ctrl_en_falling;
-typedef class gpio_reg_intr_ctrl_en_lvlhigh;
-typedef class gpio_reg_intr_ctrl_en_lvllow;
-typedef class gpio_reg_ctrl_en_input_filter;
-typedef class gpio_reg_block;
-
-typedef class flash_ctrl_reg_intr_state;
-typedef class flash_ctrl_reg_intr_enable;
-typedef class flash_ctrl_reg_intr_test;
-typedef class flash_ctrl_reg_control;
-typedef class flash_ctrl_reg_addr;
-typedef class flash_ctrl_reg_mp_region_cfg0;
-typedef class flash_ctrl_reg_mp_region_cfg1;
-typedef class flash_ctrl_reg_mp_region_cfg2;
-typedef class flash_ctrl_reg_mp_region_cfg3;
-typedef class flash_ctrl_reg_mp_region_cfg4;
-typedef class flash_ctrl_reg_mp_region_cfg5;
-typedef class flash_ctrl_reg_mp_region_cfg6;
-typedef class flash_ctrl_reg_mp_region_cfg7;
-typedef class flash_ctrl_reg_default_region;
-typedef class flash_ctrl_reg_mp_bank_cfg;
-typedef class flash_ctrl_reg_op_status;
-typedef class flash_ctrl_reg_status;
-typedef class flash_ctrl_reg_scratch;
-typedef class flash_ctrl_reg_fifo_lvl;
-typedef class flash_ctrl_mem_prog_fifo;
-typedef class flash_ctrl_mem_rd_fifo;
-typedef class flash_ctrl_reg_block;
-
typedef class uart_reg_intr_state;
typedef class uart_reg_intr_enable;
typedef class uart_reg_intr_test;
@@ -88,32 +116,6 @@
typedef class uart_reg_timeout_ctrl;
typedef class uart_reg_block;
-typedef class spi_device_reg_intr_state;
-typedef class spi_device_reg_intr_enable;
-typedef class spi_device_reg_intr_test;
-typedef class spi_device_reg_control;
-typedef class spi_device_reg_cfg;
-typedef class spi_device_reg_fifo_level;
-typedef class spi_device_reg_async_fifo_level;
-typedef class spi_device_reg_status;
-typedef class spi_device_reg_rxf_ptr;
-typedef class spi_device_reg_txf_ptr;
-typedef class spi_device_reg_rxf_addr;
-typedef class spi_device_reg_txf_addr;
-typedef class spi_device_mem_buffer;
-typedef class spi_device_reg_block;
-
-typedef class rv_timer_reg_ctrl;
-typedef class rv_timer_reg_cfg0;
-typedef class rv_timer_reg_timer_v_lower0;
-typedef class rv_timer_reg_timer_v_upper0;
-typedef class rv_timer_reg_compare_lower0_0;
-typedef class rv_timer_reg_compare_upper0_0;
-typedef class rv_timer_reg_intr_enable0;
-typedef class rv_timer_reg_intr_state0;
-typedef class rv_timer_reg_intr_test0;
-typedef class rv_timer_reg_block;
-
typedef class rv_plic_reg_ip0;
typedef class rv_plic_reg_ip1;
typedef class rv_plic_reg_le0;
@@ -184,6 +186,3672 @@
typedef class chip_mem_eflash;
typedef class chip_reg_block;
+// Block: spi_device
+// Class: spi_device_reg_intr_state
+class spi_device_reg_intr_state extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rxf;
+ rand dv_base_reg_field rxlvl;
+ rand dv_base_reg_field txlvl;
+ rand dv_base_reg_field rxerr;
+ rand dv_base_reg_field rxoverflow;
+ rand dv_base_reg_field txunderflow;
+
+ `uvm_object_utils(spi_device_reg_intr_state)
+
+ function new(string name = "spi_device_reg_intr_state",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rxf = dv_base_reg_field::type_id::create("rxf");
+ rxf.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+ rxlvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txlvl = dv_base_reg_field::type_id::create("txlvl");
+ txlvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxerr = dv_base_reg_field::type_id::create("rxerr");
+ rxerr.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxoverflow = dv_base_reg_field::type_id::create("rxoverflow");
+ rxoverflow.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txunderflow = dv_base_reg_field::type_id::create("txunderflow");
+ txunderflow.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_intr_state
+
+// Class: spi_device_reg_intr_enable
+class spi_device_reg_intr_enable extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rxf;
+ rand dv_base_reg_field rxlvl;
+ rand dv_base_reg_field txlvl;
+ rand dv_base_reg_field rxerr;
+ rand dv_base_reg_field rxoverflow;
+ rand dv_base_reg_field txunderflow;
+
+ `uvm_object_utils(spi_device_reg_intr_enable)
+
+ function new(string name = "spi_device_reg_intr_enable",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rxf = dv_base_reg_field::type_id::create("rxf");
+ rxf.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+ rxlvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txlvl = dv_base_reg_field::type_id::create("txlvl");
+ txlvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxerr = dv_base_reg_field::type_id::create("rxerr");
+ rxerr.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxoverflow = dv_base_reg_field::type_id::create("rxoverflow");
+ rxoverflow.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txunderflow = dv_base_reg_field::type_id::create("txunderflow");
+ txunderflow.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_intr_enable
+
+// Class: spi_device_reg_intr_test
+class spi_device_reg_intr_test extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rxf;
+ rand dv_base_reg_field rxlvl;
+ rand dv_base_reg_field txlvl;
+ rand dv_base_reg_field rxerr;
+ rand dv_base_reg_field rxoverflow;
+ rand dv_base_reg_field txunderflow;
+
+ `uvm_object_utils(spi_device_reg_intr_test)
+
+ function new(string name = "spi_device_reg_intr_test",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rxf = dv_base_reg_field::type_id::create("rxf");
+ rxf.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+ rxlvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txlvl = dv_base_reg_field::type_id::create("txlvl");
+ txlvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxerr = dv_base_reg_field::type_id::create("rxerr");
+ rxerr.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxoverflow = dv_base_reg_field::type_id::create("rxoverflow");
+ rxoverflow.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txunderflow = dv_base_reg_field::type_id::create("txunderflow");
+ txunderflow.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_intr_test
+
+// Class: spi_device_reg_control
+class spi_device_reg_control extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field abort;
+ rand dv_base_reg_field mode;
+ rand dv_base_reg_field rst_txfifo;
+ rand dv_base_reg_field rst_rxfifo;
+
+ `uvm_object_utils(spi_device_reg_control)
+
+ function new(string name = "spi_device_reg_control",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ abort = dv_base_reg_field::type_id::create("abort");
+ abort.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ mode = dv_base_reg_field::type_id::create("mode");
+ mode.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rst_txfifo = dv_base_reg_field::type_id::create("rst_txfifo");
+ rst_txfifo.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rst_rxfifo = dv_base_reg_field::type_id::create("rst_rxfifo");
+ rst_rxfifo.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(17),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_control
+
+// Class: spi_device_reg_cfg
+class spi_device_reg_cfg extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field cpol;
+ rand dv_base_reg_field cpha;
+ rand dv_base_reg_field tx_order;
+ rand dv_base_reg_field rx_order;
+ rand dv_base_reg_field timer_v;
+
+ `uvm_object_utils(spi_device_reg_cfg)
+
+ function new(string name = "spi_device_reg_cfg",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ cpol = dv_base_reg_field::type_id::create("cpol");
+ cpol.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ cpha = dv_base_reg_field::type_id::create("cpha");
+ cpha.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ tx_order = dv_base_reg_field::type_id::create("tx_order");
+ tx_order.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rx_order = dv_base_reg_field::type_id::create("rx_order");
+ rx_order.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ timer_v = dv_base_reg_field::type_id::create("timer_v");
+ timer_v.configure(
+ .parent(this),
+ .size(8),
+ .lsb_pos(8),
+ .access("RW"),
+ .volatile(0),
+ .reset(127),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_cfg
+
+// Class: spi_device_reg_fifo_level
+class spi_device_reg_fifo_level extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rxlvl;
+ rand dv_base_reg_field txlvl;
+
+ `uvm_object_utils(spi_device_reg_fifo_level)
+
+ function new(string name = "spi_device_reg_fifo_level",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+ rxlvl.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(128),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txlvl = dv_base_reg_field::type_id::create("txlvl");
+ txlvl.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_fifo_level
+
+// Class: spi_device_reg_async_fifo_level
+class spi_device_reg_async_fifo_level extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rxlvl;
+ rand dv_base_reg_field txlvl;
+
+ `uvm_object_utils(spi_device_reg_async_fifo_level)
+
+ function new(string name = "spi_device_reg_async_fifo_level",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rxlvl = dv_base_reg_field::type_id::create("rxlvl");
+ rxlvl.configure(
+ .parent(this),
+ .size(8),
+ .lsb_pos(0),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txlvl = dv_base_reg_field::type_id::create("txlvl");
+ txlvl.configure(
+ .parent(this),
+ .size(8),
+ .lsb_pos(16),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_async_fifo_level
+
+// Class: spi_device_reg_status
+class spi_device_reg_status extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rxf_full;
+ rand dv_base_reg_field rxf_empty;
+ rand dv_base_reg_field txf_full;
+ rand dv_base_reg_field txf_empty;
+ rand dv_base_reg_field abort_done;
+ rand dv_base_reg_field csb;
+
+ `uvm_object_utils(spi_device_reg_status)
+
+ function new(string name = "spi_device_reg_status",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rxf_full = dv_base_reg_field::type_id::create("rxf_full");
+ rxf_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rxf_empty = dv_base_reg_field::type_id::create("rxf_empty");
+ rxf_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RO"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txf_full = dv_base_reg_field::type_id::create("txf_full");
+ txf_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ txf_empty = dv_base_reg_field::type_id::create("txf_empty");
+ txf_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RO"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ abort_done = dv_base_reg_field::type_id::create("abort_done");
+ abort_done.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("RO"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ csb = dv_base_reg_field::type_id::create("csb");
+ csb.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("RO"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_status
+
+// Class: spi_device_reg_rxf_ptr
+class spi_device_reg_rxf_ptr extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rptr;
+ rand dv_base_reg_field wptr;
+
+ `uvm_object_utils(spi_device_reg_rxf_ptr)
+
+ function new(string name = "spi_device_reg_rxf_ptr",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rptr = dv_base_reg_field::type_id::create("rptr");
+ rptr.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ wptr = dv_base_reg_field::type_id::create("wptr");
+ wptr.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_rxf_ptr
+
+// Class: spi_device_reg_txf_ptr
+class spi_device_reg_txf_ptr extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rptr;
+ rand dv_base_reg_field wptr;
+
+ `uvm_object_utils(spi_device_reg_txf_ptr)
+
+ function new(string name = "spi_device_reg_txf_ptr",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rptr = dv_base_reg_field::type_id::create("rptr");
+ rptr.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ wptr = dv_base_reg_field::type_id::create("wptr");
+ wptr.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_txf_ptr
+
+// Class: spi_device_reg_rxf_addr
+class spi_device_reg_rxf_addr extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field base;
+ rand dv_base_reg_field limit;
+
+ `uvm_object_utils(spi_device_reg_rxf_addr)
+
+ function new(string name = "spi_device_reg_rxf_addr",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ base = dv_base_reg_field::type_id::create("base");
+ base.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ limit = dv_base_reg_field::type_id::create("limit");
+ limit.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(508),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_rxf_addr
+
+// Class: spi_device_reg_txf_addr
+class spi_device_reg_txf_addr extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field base;
+ rand dv_base_reg_field limit;
+
+ `uvm_object_utils(spi_device_reg_txf_addr)
+
+ function new(string name = "spi_device_reg_txf_addr",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ base = dv_base_reg_field::type_id::create("base");
+ base.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(512),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ limit = dv_base_reg_field::type_id::create("limit");
+ limit.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(1020),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : spi_device_reg_txf_addr
+
+// Class: spi_device_mem_buffer
+class spi_device_mem_buffer extends dv_base_mem;
+
+ `uvm_object_utils(spi_device_mem_buffer)
+
+ function new(string name = "spi_device_mem_buffer",
+ longint unsigned size = 512,
+ int unsigned n_bits = 32,
+ string access = "RW"/* TODO:"RW"*/,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, size, n_bits, access, has_coverage);
+ endfunction : new
+
+endclass : spi_device_mem_buffer
+
+// Class: spi_device_reg_block
+class spi_device_reg_block extends dv_base_reg_block;
+ // registers
+ rand spi_device_reg_intr_state intr_state;
+ rand spi_device_reg_intr_enable intr_enable;
+ rand spi_device_reg_intr_test intr_test;
+ rand spi_device_reg_control control;
+ rand spi_device_reg_cfg cfg;
+ rand spi_device_reg_fifo_level fifo_level;
+ rand spi_device_reg_async_fifo_level async_fifo_level;
+ rand spi_device_reg_status status;
+ rand spi_device_reg_rxf_ptr rxf_ptr;
+ rand spi_device_reg_txf_ptr txf_ptr;
+ rand spi_device_reg_rxf_addr rxf_addr;
+ rand spi_device_reg_txf_addr txf_addr;
+ // memories
+ rand spi_device_mem_buffer buffer;
+
+ `uvm_object_utils(spi_device_reg_block)
+
+ function new(string name = "spi_device_reg_block",
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, has_coverage);
+ endfunction : new
+
+ virtual function void build(uvm_reg_addr_t base_addr);
+ // create default map
+ this.default_map = create_map(.name("default_map"),
+ .base_addr(base_addr),
+ .n_bytes(4),
+ .endian(UVM_LITTLE_ENDIAN));
+
+ // create registers
+ intr_state = spi_device_reg_intr_state::type_id::create("intr_state");
+ intr_state.configure(.blk_parent(this));
+ intr_state.build();
+ default_map.add_reg(.rg(intr_state),
+ .offset(32'h0),
+ .rights("RW"));
+ intr_enable = spi_device_reg_intr_enable::type_id::create("intr_enable");
+ intr_enable.configure(.blk_parent(this));
+ intr_enable.build();
+ default_map.add_reg(.rg(intr_enable),
+ .offset(32'h4),
+ .rights("RW"));
+ intr_test = spi_device_reg_intr_test::type_id::create("intr_test");
+ intr_test.configure(.blk_parent(this));
+ intr_test.build();
+ default_map.add_reg(.rg(intr_test),
+ .offset(32'h8),
+ .rights("WO"));
+ control = spi_device_reg_control::type_id::create("control");
+ control.configure(.blk_parent(this));
+ control.build();
+ default_map.add_reg(.rg(control),
+ .offset(32'hc),
+ .rights("RW"));
+ cfg = spi_device_reg_cfg::type_id::create("cfg");
+ cfg.configure(.blk_parent(this));
+ cfg.build();
+ default_map.add_reg(.rg(cfg),
+ .offset(32'h10),
+ .rights("RW"));
+ fifo_level = spi_device_reg_fifo_level::type_id::create("fifo_level");
+ fifo_level.configure(.blk_parent(this));
+ fifo_level.build();
+ default_map.add_reg(.rg(fifo_level),
+ .offset(32'h14),
+ .rights("RW"));
+ async_fifo_level = spi_device_reg_async_fifo_level::type_id::create("async_fifo_level");
+ async_fifo_level.configure(.blk_parent(this));
+ async_fifo_level.build();
+ default_map.add_reg(.rg(async_fifo_level),
+ .offset(32'h18),
+ .rights("RO"));
+ status = spi_device_reg_status::type_id::create("status");
+ status.configure(.blk_parent(this));
+ status.build();
+ default_map.add_reg(.rg(status),
+ .offset(32'h1c),
+ .rights("RO"));
+ rxf_ptr = spi_device_reg_rxf_ptr::type_id::create("rxf_ptr");
+ rxf_ptr.configure(.blk_parent(this));
+ rxf_ptr.build();
+ default_map.add_reg(.rg(rxf_ptr),
+ .offset(32'h20),
+ .rights("RW"));
+ txf_ptr = spi_device_reg_txf_ptr::type_id::create("txf_ptr");
+ txf_ptr.configure(.blk_parent(this));
+ txf_ptr.build();
+ default_map.add_reg(.rg(txf_ptr),
+ .offset(32'h24),
+ .rights("RW"));
+ rxf_addr = spi_device_reg_rxf_addr::type_id::create("rxf_addr");
+ rxf_addr.configure(.blk_parent(this));
+ rxf_addr.build();
+ default_map.add_reg(.rg(rxf_addr),
+ .offset(32'h28),
+ .rights("RW"));
+ txf_addr = spi_device_reg_txf_addr::type_id::create("txf_addr");
+ txf_addr.configure(.blk_parent(this));
+ txf_addr.build();
+ default_map.add_reg(.rg(txf_addr),
+ .offset(32'h2c),
+ .rights("RW"));
+
+ // create memories
+ buffer = spi_device_mem_buffer::type_id::create("buffer");
+ buffer.configure(.parent(this));
+ default_map.add_mem(.mem(buffer),
+ .offset(32'h800),
+ .rights("RW"));
+ endfunction : build
+
+endclass : spi_device_reg_block
+
+// Block: flash_ctrl
+// Class: flash_ctrl_reg_intr_state
+class flash_ctrl_reg_intr_state extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prog_empty;
+ rand dv_base_reg_field prog_lvl;
+ rand dv_base_reg_field rd_full;
+ rand dv_base_reg_field rd_lvl;
+ rand dv_base_reg_field op_done;
+ rand dv_base_reg_field op_error;
+
+ `uvm_object_utils(flash_ctrl_reg_intr_state)
+
+ function new(string name = "flash_ctrl_reg_intr_state",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prog_empty = dv_base_reg_field::type_id::create("prog_empty");
+ prog_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_lvl = dv_base_reg_field::type_id::create("prog_lvl");
+ prog_lvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_full = dv_base_reg_field::type_id::create("rd_full");
+ rd_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_lvl = dv_base_reg_field::type_id::create("rd_lvl");
+ rd_lvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op_done = dv_base_reg_field::type_id::create("op_done");
+ op_done.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op_error = dv_base_reg_field::type_id::create("op_error");
+ op_error.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_intr_state
+
+// Class: flash_ctrl_reg_intr_enable
+class flash_ctrl_reg_intr_enable extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prog_empty;
+ rand dv_base_reg_field prog_lvl;
+ rand dv_base_reg_field rd_full;
+ rand dv_base_reg_field rd_lvl;
+ rand dv_base_reg_field op_done;
+ rand dv_base_reg_field op_error;
+
+ `uvm_object_utils(flash_ctrl_reg_intr_enable)
+
+ function new(string name = "flash_ctrl_reg_intr_enable",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prog_empty = dv_base_reg_field::type_id::create("prog_empty");
+ prog_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_lvl = dv_base_reg_field::type_id::create("prog_lvl");
+ prog_lvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_full = dv_base_reg_field::type_id::create("rd_full");
+ rd_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_lvl = dv_base_reg_field::type_id::create("rd_lvl");
+ rd_lvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op_done = dv_base_reg_field::type_id::create("op_done");
+ op_done.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op_error = dv_base_reg_field::type_id::create("op_error");
+ op_error.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_intr_enable
+
+// Class: flash_ctrl_reg_intr_test
+class flash_ctrl_reg_intr_test extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prog_empty;
+ rand dv_base_reg_field prog_lvl;
+ rand dv_base_reg_field rd_full;
+ rand dv_base_reg_field rd_lvl;
+ rand dv_base_reg_field op_done;
+ rand dv_base_reg_field op_error;
+
+ `uvm_object_utils(flash_ctrl_reg_intr_test)
+
+ function new(string name = "flash_ctrl_reg_intr_test",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prog_empty = dv_base_reg_field::type_id::create("prog_empty");
+ prog_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_lvl = dv_base_reg_field::type_id::create("prog_lvl");
+ prog_lvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_full = dv_base_reg_field::type_id::create("rd_full");
+ rd_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_lvl = dv_base_reg_field::type_id::create("rd_lvl");
+ rd_lvl.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op_done = dv_base_reg_field::type_id::create("op_done");
+ op_done.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op_error = dv_base_reg_field::type_id::create("op_error");
+ op_error.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_intr_test
+
+// Class: flash_ctrl_reg_control
+class flash_ctrl_reg_control extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field start;
+ rand dv_base_reg_field op;
+ rand dv_base_reg_field erase_sel;
+ rand dv_base_reg_field fifo_rst;
+ rand dv_base_reg_field num;
+
+ `uvm_object_utils(flash_ctrl_reg_control)
+
+ function new(string name = "flash_ctrl_reg_control",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ start = dv_base_reg_field::type_id::create("start");
+ start.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ op = dv_base_reg_field::type_id::create("op");
+ op.configure(
+ .parent(this),
+ .size(2),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_sel = dv_base_reg_field::type_id::create("erase_sel");
+ erase_sel.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(6),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ fifo_rst = dv_base_reg_field::type_id::create("fifo_rst");
+ fifo_rst.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(7),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ num = dv_base_reg_field::type_id::create("num");
+ num.configure(
+ .parent(this),
+ .size(12),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_control
+
+// Class: flash_ctrl_reg_addr
+class flash_ctrl_reg_addr extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field start;
+
+ `uvm_object_utils(flash_ctrl_reg_addr)
+
+ function new(string name = "flash_ctrl_reg_addr",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ start = dv_base_reg_field::type_id::create("start");
+ start.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_addr
+
+// Class: flash_ctrl_reg_region_cfg_regwen
+class flash_ctrl_reg_region_cfg_regwen extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field region0;
+ rand dv_base_reg_field region1;
+ rand dv_base_reg_field region2;
+ rand dv_base_reg_field region3;
+ rand dv_base_reg_field region4;
+ rand dv_base_reg_field region5;
+ rand dv_base_reg_field region6;
+ rand dv_base_reg_field region7;
+
+ `uvm_object_utils(flash_ctrl_reg_region_cfg_regwen)
+
+ function new(string name = "flash_ctrl_reg_region_cfg_regwen",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ region0 = dv_base_reg_field::type_id::create("region0");
+ region0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region1 = dv_base_reg_field::type_id::create("region1");
+ region1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region2 = dv_base_reg_field::type_id::create("region2");
+ region2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region3 = dv_base_reg_field::type_id::create("region3");
+ region3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region4 = dv_base_reg_field::type_id::create("region4");
+ region4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region5 = dv_base_reg_field::type_id::create("region5");
+ region5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(5),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region6 = dv_base_reg_field::type_id::create("region6");
+ region6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(6),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ region7 = dv_base_reg_field::type_id::create("region7");
+ region7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(7),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_region_cfg_regwen
+
+// Class: flash_ctrl_reg_mp_region_cfg0
+class flash_ctrl_reg_mp_region_cfg0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en0;
+ rand dv_base_reg_field rd_en0;
+ rand dv_base_reg_field prog_en0;
+ rand dv_base_reg_field erase_en0;
+ rand dv_base_reg_field base0;
+ rand dv_base_reg_field size0;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg0)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en0 = dv_base_reg_field::type_id::create("en0");
+ en0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en0 = dv_base_reg_field::type_id::create("rd_en0");
+ rd_en0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en0 = dv_base_reg_field::type_id::create("prog_en0");
+ prog_en0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en0 = dv_base_reg_field::type_id::create("erase_en0");
+ erase_en0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base0 = dv_base_reg_field::type_id::create("base0");
+ base0.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size0 = dv_base_reg_field::type_id::create("size0");
+ size0.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg0
+
+// Class: flash_ctrl_reg_mp_region_cfg1
+class flash_ctrl_reg_mp_region_cfg1 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en1;
+ rand dv_base_reg_field rd_en1;
+ rand dv_base_reg_field prog_en1;
+ rand dv_base_reg_field erase_en1;
+ rand dv_base_reg_field base1;
+ rand dv_base_reg_field size1;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg1)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg1",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en1 = dv_base_reg_field::type_id::create("en1");
+ en1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en1 = dv_base_reg_field::type_id::create("rd_en1");
+ rd_en1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en1 = dv_base_reg_field::type_id::create("prog_en1");
+ prog_en1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en1 = dv_base_reg_field::type_id::create("erase_en1");
+ erase_en1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base1 = dv_base_reg_field::type_id::create("base1");
+ base1.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size1 = dv_base_reg_field::type_id::create("size1");
+ size1.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg1
+
+// Class: flash_ctrl_reg_mp_region_cfg2
+class flash_ctrl_reg_mp_region_cfg2 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en2;
+ rand dv_base_reg_field rd_en2;
+ rand dv_base_reg_field prog_en2;
+ rand dv_base_reg_field erase_en2;
+ rand dv_base_reg_field base2;
+ rand dv_base_reg_field size2;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg2)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg2",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en2 = dv_base_reg_field::type_id::create("en2");
+ en2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en2 = dv_base_reg_field::type_id::create("rd_en2");
+ rd_en2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en2 = dv_base_reg_field::type_id::create("prog_en2");
+ prog_en2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en2 = dv_base_reg_field::type_id::create("erase_en2");
+ erase_en2.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base2 = dv_base_reg_field::type_id::create("base2");
+ base2.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size2 = dv_base_reg_field::type_id::create("size2");
+ size2.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg2
+
+// Class: flash_ctrl_reg_mp_region_cfg3
+class flash_ctrl_reg_mp_region_cfg3 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en3;
+ rand dv_base_reg_field rd_en3;
+ rand dv_base_reg_field prog_en3;
+ rand dv_base_reg_field erase_en3;
+ rand dv_base_reg_field base3;
+ rand dv_base_reg_field size3;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg3)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg3",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en3 = dv_base_reg_field::type_id::create("en3");
+ en3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en3 = dv_base_reg_field::type_id::create("rd_en3");
+ rd_en3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en3 = dv_base_reg_field::type_id::create("prog_en3");
+ prog_en3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en3 = dv_base_reg_field::type_id::create("erase_en3");
+ erase_en3.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base3 = dv_base_reg_field::type_id::create("base3");
+ base3.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size3 = dv_base_reg_field::type_id::create("size3");
+ size3.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg3
+
+// Class: flash_ctrl_reg_mp_region_cfg4
+class flash_ctrl_reg_mp_region_cfg4 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en4;
+ rand dv_base_reg_field rd_en4;
+ rand dv_base_reg_field prog_en4;
+ rand dv_base_reg_field erase_en4;
+ rand dv_base_reg_field base4;
+ rand dv_base_reg_field size4;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg4)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg4",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en4 = dv_base_reg_field::type_id::create("en4");
+ en4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en4 = dv_base_reg_field::type_id::create("rd_en4");
+ rd_en4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en4 = dv_base_reg_field::type_id::create("prog_en4");
+ prog_en4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en4 = dv_base_reg_field::type_id::create("erase_en4");
+ erase_en4.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base4 = dv_base_reg_field::type_id::create("base4");
+ base4.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size4 = dv_base_reg_field::type_id::create("size4");
+ size4.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg4
+
+// Class: flash_ctrl_reg_mp_region_cfg5
+class flash_ctrl_reg_mp_region_cfg5 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en5;
+ rand dv_base_reg_field rd_en5;
+ rand dv_base_reg_field prog_en5;
+ rand dv_base_reg_field erase_en5;
+ rand dv_base_reg_field base5;
+ rand dv_base_reg_field size5;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg5)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg5",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en5 = dv_base_reg_field::type_id::create("en5");
+ en5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en5 = dv_base_reg_field::type_id::create("rd_en5");
+ rd_en5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en5 = dv_base_reg_field::type_id::create("prog_en5");
+ prog_en5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en5 = dv_base_reg_field::type_id::create("erase_en5");
+ erase_en5.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base5 = dv_base_reg_field::type_id::create("base5");
+ base5.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size5 = dv_base_reg_field::type_id::create("size5");
+ size5.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg5
+
+// Class: flash_ctrl_reg_mp_region_cfg6
+class flash_ctrl_reg_mp_region_cfg6 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en6;
+ rand dv_base_reg_field rd_en6;
+ rand dv_base_reg_field prog_en6;
+ rand dv_base_reg_field erase_en6;
+ rand dv_base_reg_field base6;
+ rand dv_base_reg_field size6;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg6)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg6",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en6 = dv_base_reg_field::type_id::create("en6");
+ en6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en6 = dv_base_reg_field::type_id::create("rd_en6");
+ rd_en6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en6 = dv_base_reg_field::type_id::create("prog_en6");
+ prog_en6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en6 = dv_base_reg_field::type_id::create("erase_en6");
+ erase_en6.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base6 = dv_base_reg_field::type_id::create("base6");
+ base6.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size6 = dv_base_reg_field::type_id::create("size6");
+ size6.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg6
+
+// Class: flash_ctrl_reg_mp_region_cfg7
+class flash_ctrl_reg_mp_region_cfg7 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field en7;
+ rand dv_base_reg_field rd_en7;
+ rand dv_base_reg_field prog_en7;
+ rand dv_base_reg_field erase_en7;
+ rand dv_base_reg_field base7;
+ rand dv_base_reg_field size7;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_region_cfg7)
+
+ function new(string name = "flash_ctrl_reg_mp_region_cfg7",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ en7 = dv_base_reg_field::type_id::create("en7");
+ en7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_en7 = dv_base_reg_field::type_id::create("rd_en7");
+ rd_en7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en7 = dv_base_reg_field::type_id::create("prog_en7");
+ prog_en7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en7 = dv_base_reg_field::type_id::create("erase_en7");
+ erase_en7.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ base7 = dv_base_reg_field::type_id::create("base7");
+ base7.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(4),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ size7 = dv_base_reg_field::type_id::create("size7");
+ size7.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_region_cfg7
+
+// Class: flash_ctrl_reg_default_region
+class flash_ctrl_reg_default_region extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rd_en;
+ rand dv_base_reg_field prog_en;
+ rand dv_base_reg_field erase_en;
+
+ `uvm_object_utils(flash_ctrl_reg_default_region)
+
+ function new(string name = "flash_ctrl_reg_default_region",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rd_en = dv_base_reg_field::type_id::create("rd_en");
+ rd_en.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_en = dv_base_reg_field::type_id::create("prog_en");
+ prog_en.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en = dv_base_reg_field::type_id::create("erase_en");
+ erase_en.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_default_region
+
+// Class: flash_ctrl_reg_bank_cfg_regwen
+class flash_ctrl_reg_bank_cfg_regwen extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field bank0;
+ rand dv_base_reg_field bank1;
+
+ `uvm_object_utils(flash_ctrl_reg_bank_cfg_regwen)
+
+ function new(string name = "flash_ctrl_reg_bank_cfg_regwen",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ bank0 = dv_base_reg_field::type_id::create("bank0");
+ bank0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ bank1 = dv_base_reg_field::type_id::create("bank1");
+ bank1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("W0C"),
+ .volatile(1),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_bank_cfg_regwen
+
+// Class: flash_ctrl_reg_mp_bank_cfg
+class flash_ctrl_reg_mp_bank_cfg extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field erase_en0;
+ rand dv_base_reg_field erase_en1;
+
+ `uvm_object_utils(flash_ctrl_reg_mp_bank_cfg)
+
+ function new(string name = "flash_ctrl_reg_mp_bank_cfg",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ erase_en0 = dv_base_reg_field::type_id::create("erase_en0");
+ erase_en0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ erase_en1 = dv_base_reg_field::type_id::create("erase_en1");
+ erase_en1.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_mp_bank_cfg
+
+// Class: flash_ctrl_reg_op_status
+class flash_ctrl_reg_op_status extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field done;
+ rand dv_base_reg_field err;
+
+ `uvm_object_utils(flash_ctrl_reg_op_status)
+
+ function new(string name = "flash_ctrl_reg_op_status",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ done = dv_base_reg_field::type_id::create("done");
+ done.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ err = dv_base_reg_field::type_id::create("err");
+ err.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_op_status
+
+// Class: flash_ctrl_reg_status
+class flash_ctrl_reg_status extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field rd_full;
+ rand dv_base_reg_field rd_empty;
+ rand dv_base_reg_field prog_full;
+ rand dv_base_reg_field prog_empty;
+ rand dv_base_reg_field init_wip;
+ rand dv_base_reg_field error_page;
+ rand dv_base_reg_field error_bank;
+
+ `uvm_object_utils(flash_ctrl_reg_status)
+
+ function new(string name = "flash_ctrl_reg_status",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ rd_full = dv_base_reg_field::type_id::create("rd_full");
+ rd_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd_empty = dv_base_reg_field::type_id::create("rd_empty");
+ rd_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(1),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_full = dv_base_reg_field::type_id::create("prog_full");
+ prog_full.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(2),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ prog_empty = dv_base_reg_field::type_id::create("prog_empty");
+ prog_empty.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(3),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ init_wip = dv_base_reg_field::type_id::create("init_wip");
+ init_wip.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(4),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ error_page = dv_base_reg_field::type_id::create("error_page");
+ error_page.configure(
+ .parent(this),
+ .size(9),
+ .lsb_pos(8),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ error_bank = dv_base_reg_field::type_id::create("error_bank");
+ error_bank.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(17),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_status
+
+// Class: flash_ctrl_reg_scratch
+class flash_ctrl_reg_scratch extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field data;
+
+ `uvm_object_utils(flash_ctrl_reg_scratch)
+
+ function new(string name = "flash_ctrl_reg_scratch",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ data = dv_base_reg_field::type_id::create("data");
+ data.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_scratch
+
+// Class: flash_ctrl_reg_fifo_lvl
+class flash_ctrl_reg_fifo_lvl extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prog;
+ rand dv_base_reg_field rd;
+
+ `uvm_object_utils(flash_ctrl_reg_fifo_lvl)
+
+ function new(string name = "flash_ctrl_reg_fifo_lvl",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prog = dv_base_reg_field::type_id::create("prog");
+ prog.configure(
+ .parent(this),
+ .size(5),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(15),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ rd = dv_base_reg_field::type_id::create("rd");
+ rd.configure(
+ .parent(this),
+ .size(5),
+ .lsb_pos(8),
+ .access("RW"),
+ .volatile(0),
+ .reset(15),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : flash_ctrl_reg_fifo_lvl
+
+// Class: flash_ctrl_mem_prog_fifo
+class flash_ctrl_mem_prog_fifo extends dv_base_mem;
+
+ `uvm_object_utils(flash_ctrl_mem_prog_fifo)
+
+ function new(string name = "flash_ctrl_mem_prog_fifo",
+ longint unsigned size = 1,
+ int unsigned n_bits = 32,
+ string access = "RW"/* TODO:"WO"*/,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, size, n_bits, access, has_coverage);
+ endfunction : new
+
+endclass : flash_ctrl_mem_prog_fifo
+
+// Class: flash_ctrl_mem_rd_fifo
+class flash_ctrl_mem_rd_fifo extends dv_base_mem;
+
+ `uvm_object_utils(flash_ctrl_mem_rd_fifo)
+
+ function new(string name = "flash_ctrl_mem_rd_fifo",
+ longint unsigned size = 1,
+ int unsigned n_bits = 32,
+ string access = "RW"/* TODO:"RO"*/,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, size, n_bits, access, has_coverage);
+ endfunction : new
+
+endclass : flash_ctrl_mem_rd_fifo
+
+// Class: flash_ctrl_reg_block
+class flash_ctrl_reg_block extends dv_base_reg_block;
+ // registers
+ rand flash_ctrl_reg_intr_state intr_state;
+ rand flash_ctrl_reg_intr_enable intr_enable;
+ rand flash_ctrl_reg_intr_test intr_test;
+ rand flash_ctrl_reg_control control;
+ rand flash_ctrl_reg_addr addr;
+ rand flash_ctrl_reg_region_cfg_regwen region_cfg_regwen;
+ rand flash_ctrl_reg_mp_region_cfg0 mp_region_cfg0;
+ rand flash_ctrl_reg_mp_region_cfg1 mp_region_cfg1;
+ rand flash_ctrl_reg_mp_region_cfg2 mp_region_cfg2;
+ rand flash_ctrl_reg_mp_region_cfg3 mp_region_cfg3;
+ rand flash_ctrl_reg_mp_region_cfg4 mp_region_cfg4;
+ rand flash_ctrl_reg_mp_region_cfg5 mp_region_cfg5;
+ rand flash_ctrl_reg_mp_region_cfg6 mp_region_cfg6;
+ rand flash_ctrl_reg_mp_region_cfg7 mp_region_cfg7;
+ rand flash_ctrl_reg_default_region default_region;
+ rand flash_ctrl_reg_bank_cfg_regwen bank_cfg_regwen;
+ rand flash_ctrl_reg_mp_bank_cfg mp_bank_cfg;
+ rand flash_ctrl_reg_op_status op_status;
+ rand flash_ctrl_reg_status status;
+ rand flash_ctrl_reg_scratch scratch;
+ rand flash_ctrl_reg_fifo_lvl fifo_lvl;
+ // memories
+ rand flash_ctrl_mem_prog_fifo prog_fifo;
+ rand flash_ctrl_mem_rd_fifo rd_fifo;
+
+ `uvm_object_utils(flash_ctrl_reg_block)
+
+ function new(string name = "flash_ctrl_reg_block",
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, has_coverage);
+ endfunction : new
+
+ virtual function void build(uvm_reg_addr_t base_addr);
+ // create default map
+ this.default_map = create_map(.name("default_map"),
+ .base_addr(base_addr),
+ .n_bytes(4),
+ .endian(UVM_LITTLE_ENDIAN));
+
+ // create registers
+ intr_state = flash_ctrl_reg_intr_state::type_id::create("intr_state");
+ intr_state.configure(.blk_parent(this));
+ intr_state.build();
+ default_map.add_reg(.rg(intr_state),
+ .offset(32'h0),
+ .rights("RW"));
+ intr_enable = flash_ctrl_reg_intr_enable::type_id::create("intr_enable");
+ intr_enable.configure(.blk_parent(this));
+ intr_enable.build();
+ default_map.add_reg(.rg(intr_enable),
+ .offset(32'h4),
+ .rights("RW"));
+ intr_test = flash_ctrl_reg_intr_test::type_id::create("intr_test");
+ intr_test.configure(.blk_parent(this));
+ intr_test.build();
+ default_map.add_reg(.rg(intr_test),
+ .offset(32'h8),
+ .rights("WO"));
+ control = flash_ctrl_reg_control::type_id::create("control");
+ control.configure(.blk_parent(this));
+ control.build();
+ default_map.add_reg(.rg(control),
+ .offset(32'hc),
+ .rights("RW"));
+ addr = flash_ctrl_reg_addr::type_id::create("addr");
+ addr.configure(.blk_parent(this));
+ addr.build();
+ default_map.add_reg(.rg(addr),
+ .offset(32'h10),
+ .rights("RW"));
+ region_cfg_regwen = flash_ctrl_reg_region_cfg_regwen::type_id::create("region_cfg_regwen");
+ region_cfg_regwen.configure(.blk_parent(this));
+ region_cfg_regwen.build();
+ default_map.add_reg(.rg(region_cfg_regwen),
+ .offset(32'h14),
+ .rights("RW"));
+ mp_region_cfg0 = flash_ctrl_reg_mp_region_cfg0::type_id::create("mp_region_cfg0");
+ mp_region_cfg0.configure(.blk_parent(this));
+ mp_region_cfg0.build();
+ default_map.add_reg(.rg(mp_region_cfg0),
+ .offset(32'h18),
+ .rights("RW"));
+ mp_region_cfg1 = flash_ctrl_reg_mp_region_cfg1::type_id::create("mp_region_cfg1");
+ mp_region_cfg1.configure(.blk_parent(this));
+ mp_region_cfg1.build();
+ default_map.add_reg(.rg(mp_region_cfg1),
+ .offset(32'h1c),
+ .rights("RW"));
+ mp_region_cfg2 = flash_ctrl_reg_mp_region_cfg2::type_id::create("mp_region_cfg2");
+ mp_region_cfg2.configure(.blk_parent(this));
+ mp_region_cfg2.build();
+ default_map.add_reg(.rg(mp_region_cfg2),
+ .offset(32'h20),
+ .rights("RW"));
+ mp_region_cfg3 = flash_ctrl_reg_mp_region_cfg3::type_id::create("mp_region_cfg3");
+ mp_region_cfg3.configure(.blk_parent(this));
+ mp_region_cfg3.build();
+ default_map.add_reg(.rg(mp_region_cfg3),
+ .offset(32'h24),
+ .rights("RW"));
+ mp_region_cfg4 = flash_ctrl_reg_mp_region_cfg4::type_id::create("mp_region_cfg4");
+ mp_region_cfg4.configure(.blk_parent(this));
+ mp_region_cfg4.build();
+ default_map.add_reg(.rg(mp_region_cfg4),
+ .offset(32'h28),
+ .rights("RW"));
+ mp_region_cfg5 = flash_ctrl_reg_mp_region_cfg5::type_id::create("mp_region_cfg5");
+ mp_region_cfg5.configure(.blk_parent(this));
+ mp_region_cfg5.build();
+ default_map.add_reg(.rg(mp_region_cfg5),
+ .offset(32'h2c),
+ .rights("RW"));
+ mp_region_cfg6 = flash_ctrl_reg_mp_region_cfg6::type_id::create("mp_region_cfg6");
+ mp_region_cfg6.configure(.blk_parent(this));
+ mp_region_cfg6.build();
+ default_map.add_reg(.rg(mp_region_cfg6),
+ .offset(32'h30),
+ .rights("RW"));
+ mp_region_cfg7 = flash_ctrl_reg_mp_region_cfg7::type_id::create("mp_region_cfg7");
+ mp_region_cfg7.configure(.blk_parent(this));
+ mp_region_cfg7.build();
+ default_map.add_reg(.rg(mp_region_cfg7),
+ .offset(32'h34),
+ .rights("RW"));
+ default_region = flash_ctrl_reg_default_region::type_id::create("default_region");
+ default_region.configure(.blk_parent(this));
+ default_region.build();
+ default_map.add_reg(.rg(default_region),
+ .offset(32'h38),
+ .rights("RW"));
+ bank_cfg_regwen = flash_ctrl_reg_bank_cfg_regwen::type_id::create("bank_cfg_regwen");
+ bank_cfg_regwen.configure(.blk_parent(this));
+ bank_cfg_regwen.build();
+ default_map.add_reg(.rg(bank_cfg_regwen),
+ .offset(32'h3c),
+ .rights("RW"));
+ mp_bank_cfg = flash_ctrl_reg_mp_bank_cfg::type_id::create("mp_bank_cfg");
+ mp_bank_cfg.configure(.blk_parent(this));
+ mp_bank_cfg.build();
+ default_map.add_reg(.rg(mp_bank_cfg),
+ .offset(32'h40),
+ .rights("RW"));
+ op_status = flash_ctrl_reg_op_status::type_id::create("op_status");
+ op_status.configure(.blk_parent(this));
+ op_status.build();
+ default_map.add_reg(.rg(op_status),
+ .offset(32'h44),
+ .rights("RW"));
+ status = flash_ctrl_reg_status::type_id::create("status");
+ status.configure(.blk_parent(this));
+ status.build();
+ default_map.add_reg(.rg(status),
+ .offset(32'h48),
+ .rights("RO"));
+ scratch = flash_ctrl_reg_scratch::type_id::create("scratch");
+ scratch.configure(.blk_parent(this));
+ scratch.build();
+ default_map.add_reg(.rg(scratch),
+ .offset(32'h4c),
+ .rights("RW"));
+ fifo_lvl = flash_ctrl_reg_fifo_lvl::type_id::create("fifo_lvl");
+ fifo_lvl.configure(.blk_parent(this));
+ fifo_lvl.build();
+ default_map.add_reg(.rg(fifo_lvl),
+ .offset(32'h50),
+ .rights("RW"));
+
+ // create memories
+ prog_fifo = flash_ctrl_mem_prog_fifo::type_id::create("prog_fifo");
+ prog_fifo.configure(.parent(this));
+ default_map.add_mem(.mem(prog_fifo),
+ .offset(32'h54),
+ .rights("WO"));
+ rd_fifo = flash_ctrl_mem_rd_fifo::type_id::create("rd_fifo");
+ rd_fifo.configure(.parent(this));
+ default_map.add_mem(.mem(rd_fifo),
+ .offset(32'h58),
+ .rights("RO"));
+ endfunction : build
+
+endclass : flash_ctrl_reg_block
+
+// Block: rv_timer
+// Class: rv_timer_reg_ctrl
+class rv_timer_reg_ctrl extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field active0;
+
+ `uvm_object_utils(rv_timer_reg_ctrl)
+
+ function new(string name = "rv_timer_reg_ctrl",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ active0 = dv_base_reg_field::type_id::create("active0");
+ active0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_ctrl
+
+// Class: rv_timer_reg_cfg0
+class rv_timer_reg_cfg0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field prescale;
+ rand dv_base_reg_field step;
+
+ `uvm_object_utils(rv_timer_reg_cfg0)
+
+ function new(string name = "rv_timer_reg_cfg0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ prescale = dv_base_reg_field::type_id::create("prescale");
+ prescale.configure(
+ .parent(this),
+ .size(12),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ step = dv_base_reg_field::type_id::create("step");
+ step.configure(
+ .parent(this),
+ .size(8),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(0),
+ .reset(1),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_cfg0
+
+// Class: rv_timer_reg_timer_v_lower0
+class rv_timer_reg_timer_v_lower0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field v;
+
+ `uvm_object_utils(rv_timer_reg_timer_v_lower0)
+
+ function new(string name = "rv_timer_reg_timer_v_lower0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ v = dv_base_reg_field::type_id::create("v");
+ v.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_timer_v_lower0
+
+// Class: rv_timer_reg_timer_v_upper0
+class rv_timer_reg_timer_v_upper0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field v;
+
+ `uvm_object_utils(rv_timer_reg_timer_v_upper0)
+
+ function new(string name = "rv_timer_reg_timer_v_upper0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ v = dv_base_reg_field::type_id::create("v");
+ v.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_timer_v_upper0
+
+// Class: rv_timer_reg_compare_lower0_0
+class rv_timer_reg_compare_lower0_0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field v;
+
+ `uvm_object_utils(rv_timer_reg_compare_lower0_0)
+
+ function new(string name = "rv_timer_reg_compare_lower0_0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ v = dv_base_reg_field::type_id::create("v");
+ v.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(4294967295),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_compare_lower0_0
+
+// Class: rv_timer_reg_compare_upper0_0
+class rv_timer_reg_compare_upper0_0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field v;
+
+ `uvm_object_utils(rv_timer_reg_compare_upper0_0)
+
+ function new(string name = "rv_timer_reg_compare_upper0_0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ v = dv_base_reg_field::type_id::create("v");
+ v.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(4294967295),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_compare_upper0_0
+
+// Class: rv_timer_reg_intr_enable0
+class rv_timer_reg_intr_enable0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field ie0;
+
+ `uvm_object_utils(rv_timer_reg_intr_enable0)
+
+ function new(string name = "rv_timer_reg_intr_enable0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ ie0 = dv_base_reg_field::type_id::create("ie0");
+ ie0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_intr_enable0
+
+// Class: rv_timer_reg_intr_state0
+class rv_timer_reg_intr_state0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field is0;
+
+ `uvm_object_utils(rv_timer_reg_intr_state0)
+
+ function new(string name = "rv_timer_reg_intr_state0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ is0 = dv_base_reg_field::type_id::create("is0");
+ is0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_intr_state0
+
+// Class: rv_timer_reg_intr_test0
+class rv_timer_reg_intr_test0 extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field t0;
+
+ `uvm_object_utils(rv_timer_reg_intr_test0)
+
+ function new(string name = "rv_timer_reg_intr_test0",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ t0 = dv_base_reg_field::type_id::create("t0");
+ t0.configure(
+ .parent(this),
+ .size(1),
+ .lsb_pos(0),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : rv_timer_reg_intr_test0
+
+// Class: rv_timer_reg_block
+class rv_timer_reg_block extends dv_base_reg_block;
+ // registers
+ rand rv_timer_reg_ctrl ctrl;
+ rand rv_timer_reg_cfg0 cfg0;
+ rand rv_timer_reg_timer_v_lower0 timer_v_lower0;
+ rand rv_timer_reg_timer_v_upper0 timer_v_upper0;
+ rand rv_timer_reg_compare_lower0_0 compare_lower0_0;
+ rand rv_timer_reg_compare_upper0_0 compare_upper0_0;
+ rand rv_timer_reg_intr_enable0 intr_enable0;
+ rand rv_timer_reg_intr_state0 intr_state0;
+ rand rv_timer_reg_intr_test0 intr_test0;
+
+ `uvm_object_utils(rv_timer_reg_block)
+
+ function new(string name = "rv_timer_reg_block",
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, has_coverage);
+ endfunction : new
+
+ virtual function void build(uvm_reg_addr_t base_addr);
+ // create default map
+ this.default_map = create_map(.name("default_map"),
+ .base_addr(base_addr),
+ .n_bytes(4),
+ .endian(UVM_LITTLE_ENDIAN));
+
+ // create registers
+ ctrl = rv_timer_reg_ctrl::type_id::create("ctrl");
+ ctrl.configure(.blk_parent(this));
+ ctrl.build();
+ default_map.add_reg(.rg(ctrl),
+ .offset(32'h0),
+ .rights("RW"));
+ cfg0 = rv_timer_reg_cfg0::type_id::create("cfg0");
+ cfg0.configure(.blk_parent(this));
+ cfg0.build();
+ default_map.add_reg(.rg(cfg0),
+ .offset(32'h100),
+ .rights("RW"));
+ timer_v_lower0 = rv_timer_reg_timer_v_lower0::type_id::create("timer_v_lower0");
+ timer_v_lower0.configure(.blk_parent(this));
+ timer_v_lower0.build();
+ default_map.add_reg(.rg(timer_v_lower0),
+ .offset(32'h104),
+ .rights("RW"));
+ timer_v_upper0 = rv_timer_reg_timer_v_upper0::type_id::create("timer_v_upper0");
+ timer_v_upper0.configure(.blk_parent(this));
+ timer_v_upper0.build();
+ default_map.add_reg(.rg(timer_v_upper0),
+ .offset(32'h108),
+ .rights("RW"));
+ compare_lower0_0 = rv_timer_reg_compare_lower0_0::type_id::create("compare_lower0_0");
+ compare_lower0_0.configure(.blk_parent(this));
+ compare_lower0_0.build();
+ default_map.add_reg(.rg(compare_lower0_0),
+ .offset(32'h10c),
+ .rights("RW"));
+ compare_upper0_0 = rv_timer_reg_compare_upper0_0::type_id::create("compare_upper0_0");
+ compare_upper0_0.configure(.blk_parent(this));
+ compare_upper0_0.build();
+ default_map.add_reg(.rg(compare_upper0_0),
+ .offset(32'h110),
+ .rights("RW"));
+ intr_enable0 = rv_timer_reg_intr_enable0::type_id::create("intr_enable0");
+ intr_enable0.configure(.blk_parent(this));
+ intr_enable0.build();
+ default_map.add_reg(.rg(intr_enable0),
+ .offset(32'h114),
+ .rights("RW"));
+ intr_state0 = rv_timer_reg_intr_state0::type_id::create("intr_state0");
+ intr_state0.configure(.blk_parent(this));
+ intr_state0.build();
+ default_map.add_reg(.rg(intr_state0),
+ .offset(32'h118),
+ .rights("RW"));
+ intr_test0 = rv_timer_reg_intr_test0::type_id::create("intr_test0");
+ intr_test0.configure(.blk_parent(this));
+ intr_test0.build();
+ default_map.add_reg(.rg(intr_test0),
+ .offset(32'h11c),
+ .rights("WO"));
+ endfunction : build
+
+endclass : rv_timer_reg_block
+
+// Block: gpio
+// Class: gpio_reg_intr_state
+class gpio_reg_intr_state extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field gpio;
+
+ `uvm_object_utils(gpio_reg_intr_state)
+
+ function new(string name = "gpio_reg_intr_state",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ gpio = dv_base_reg_field::type_id::create("gpio");
+ gpio.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("W1C"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_state
+
+// Class: gpio_reg_intr_enable
+class gpio_reg_intr_enable extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field gpio;
+
+ `uvm_object_utils(gpio_reg_intr_enable)
+
+ function new(string name = "gpio_reg_intr_enable",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ gpio = dv_base_reg_field::type_id::create("gpio");
+ gpio.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_enable
+
+// Class: gpio_reg_intr_test
+class gpio_reg_intr_test extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field gpio;
+
+ `uvm_object_utils(gpio_reg_intr_test)
+
+ function new(string name = "gpio_reg_intr_test",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ gpio = dv_base_reg_field::type_id::create("gpio");
+ gpio.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("WO"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_test
+
+// Class: gpio_reg_data_in
+class gpio_reg_data_in extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field data_in;
+
+ `uvm_object_utils(gpio_reg_data_in)
+
+ function new(string name = "gpio_reg_data_in",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ data_in = dv_base_reg_field::type_id::create("data_in");
+ data_in.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_data_in
+
+// Class: gpio_reg_direct_out
+class gpio_reg_direct_out extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field direct_out;
+
+ `uvm_object_utils(gpio_reg_direct_out)
+
+ function new(string name = "gpio_reg_direct_out",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ direct_out = dv_base_reg_field::type_id::create("direct_out");
+ direct_out.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_direct_out
+
+// Class: gpio_reg_masked_out_lower
+class gpio_reg_masked_out_lower extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field data;
+ rand dv_base_reg_field mask;
+
+ `uvm_object_utils(gpio_reg_masked_out_lower)
+
+ function new(string name = "gpio_reg_masked_out_lower",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ data = dv_base_reg_field::type_id::create("data");
+ data.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ mask = dv_base_reg_field::type_id::create("mask");
+ mask.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("WO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_masked_out_lower
+
+// Class: gpio_reg_masked_out_upper
+class gpio_reg_masked_out_upper extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field data;
+ rand dv_base_reg_field mask;
+
+ `uvm_object_utils(gpio_reg_masked_out_upper)
+
+ function new(string name = "gpio_reg_masked_out_upper",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ data = dv_base_reg_field::type_id::create("data");
+ data.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ mask = dv_base_reg_field::type_id::create("mask");
+ mask.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("WO"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_masked_out_upper
+
+// Class: gpio_reg_direct_oe
+class gpio_reg_direct_oe extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field direct_oe;
+
+ `uvm_object_utils(gpio_reg_direct_oe)
+
+ function new(string name = "gpio_reg_direct_oe",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ direct_oe = dv_base_reg_field::type_id::create("direct_oe");
+ direct_oe.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_direct_oe
+
+// Class: gpio_reg_masked_oe_lower
+class gpio_reg_masked_oe_lower extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field data;
+ rand dv_base_reg_field mask;
+
+ `uvm_object_utils(gpio_reg_masked_oe_lower)
+
+ function new(string name = "gpio_reg_masked_oe_lower",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ data = dv_base_reg_field::type_id::create("data");
+ data.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ mask = dv_base_reg_field::type_id::create("mask");
+ mask.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_masked_oe_lower
+
+// Class: gpio_reg_masked_oe_upper
+class gpio_reg_masked_oe_upper extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field data;
+ rand dv_base_reg_field mask;
+
+ `uvm_object_utils(gpio_reg_masked_oe_upper)
+
+ function new(string name = "gpio_reg_masked_oe_upper",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ data = dv_base_reg_field::type_id::create("data");
+ data.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ mask = dv_base_reg_field::type_id::create("mask");
+ mask.configure(
+ .parent(this),
+ .size(16),
+ .lsb_pos(16),
+ .access("RW"),
+ .volatile(1),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_masked_oe_upper
+
+// Class: gpio_reg_intr_ctrl_en_rising
+class gpio_reg_intr_ctrl_en_rising extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field intr_ctrl_en_rising;
+
+ `uvm_object_utils(gpio_reg_intr_ctrl_en_rising)
+
+ function new(string name = "gpio_reg_intr_ctrl_en_rising",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ intr_ctrl_en_rising = dv_base_reg_field::type_id::create("intr_ctrl_en_rising");
+ intr_ctrl_en_rising.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_rising
+
+// Class: gpio_reg_intr_ctrl_en_falling
+class gpio_reg_intr_ctrl_en_falling extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field intr_ctrl_en_falling;
+
+ `uvm_object_utils(gpio_reg_intr_ctrl_en_falling)
+
+ function new(string name = "gpio_reg_intr_ctrl_en_falling",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ intr_ctrl_en_falling = dv_base_reg_field::type_id::create("intr_ctrl_en_falling");
+ intr_ctrl_en_falling.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_falling
+
+// Class: gpio_reg_intr_ctrl_en_lvlhigh
+class gpio_reg_intr_ctrl_en_lvlhigh extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field intr_ctrl_en_lvlhigh;
+
+ `uvm_object_utils(gpio_reg_intr_ctrl_en_lvlhigh)
+
+ function new(string name = "gpio_reg_intr_ctrl_en_lvlhigh",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ intr_ctrl_en_lvlhigh = dv_base_reg_field::type_id::create("intr_ctrl_en_lvlhigh");
+ intr_ctrl_en_lvlhigh.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_lvlhigh
+
+// Class: gpio_reg_intr_ctrl_en_lvllow
+class gpio_reg_intr_ctrl_en_lvllow extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field intr_ctrl_en_lvllow;
+
+ `uvm_object_utils(gpio_reg_intr_ctrl_en_lvllow)
+
+ function new(string name = "gpio_reg_intr_ctrl_en_lvllow",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ intr_ctrl_en_lvllow = dv_base_reg_field::type_id::create("intr_ctrl_en_lvllow");
+ intr_ctrl_en_lvllow.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_intr_ctrl_en_lvllow
+
+// Class: gpio_reg_ctrl_en_input_filter
+class gpio_reg_ctrl_en_input_filter extends dv_base_reg;
+ // fields
+ rand dv_base_reg_field ctrl_en_input_filter;
+
+ `uvm_object_utils(gpio_reg_ctrl_en_input_filter)
+
+ function new(string name = "gpio_reg_ctrl_en_input_filter",
+ int unsigned n_bits = 32,
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, n_bits, has_coverage);
+ endfunction : new
+
+ virtual function void build();
+ // create fields
+ ctrl_en_input_filter = dv_base_reg_field::type_id::create("ctrl_en_input_filter");
+ ctrl_en_input_filter.configure(
+ .parent(this),
+ .size(32),
+ .lsb_pos(0),
+ .access("RW"),
+ .volatile(0),
+ .reset(0),
+ .has_reset(1),
+ .is_rand(1),
+ .individually_accessible(1));
+ endfunction : build
+
+endclass : gpio_reg_ctrl_en_input_filter
+
+// Class: gpio_reg_block
+class gpio_reg_block extends dv_base_reg_block;
+ // registers
+ rand gpio_reg_intr_state intr_state;
+ rand gpio_reg_intr_enable intr_enable;
+ rand gpio_reg_intr_test intr_test;
+ rand gpio_reg_data_in data_in;
+ rand gpio_reg_direct_out direct_out;
+ rand gpio_reg_masked_out_lower masked_out_lower;
+ rand gpio_reg_masked_out_upper masked_out_upper;
+ rand gpio_reg_direct_oe direct_oe;
+ rand gpio_reg_masked_oe_lower masked_oe_lower;
+ rand gpio_reg_masked_oe_upper masked_oe_upper;
+ rand gpio_reg_intr_ctrl_en_rising intr_ctrl_en_rising;
+ rand gpio_reg_intr_ctrl_en_falling intr_ctrl_en_falling;
+ rand gpio_reg_intr_ctrl_en_lvlhigh intr_ctrl_en_lvlhigh;
+ rand gpio_reg_intr_ctrl_en_lvllow intr_ctrl_en_lvllow;
+ rand gpio_reg_ctrl_en_input_filter ctrl_en_input_filter;
+
+ `uvm_object_utils(gpio_reg_block)
+
+ function new(string name = "gpio_reg_block",
+ int has_coverage = UVM_NO_COVERAGE);
+ super.new(name, has_coverage);
+ endfunction : new
+
+ virtual function void build(uvm_reg_addr_t base_addr);
+ // create default map
+ this.default_map = create_map(.name("default_map"),
+ .base_addr(base_addr),
+ .n_bytes(4),
+ .endian(UVM_LITTLE_ENDIAN));
+
+ // create registers
+ intr_state = gpio_reg_intr_state::type_id::create("intr_state");
+ intr_state.configure(.blk_parent(this));
+ intr_state.build();
+ default_map.add_reg(.rg(intr_state),
+ .offset(32'h0),
+ .rights("RW"));
+ intr_enable = gpio_reg_intr_enable::type_id::create("intr_enable");
+ intr_enable.configure(.blk_parent(this));
+ intr_enable.build();
+ default_map.add_reg(.rg(intr_enable),
+ .offset(32'h4),
+ .rights("RW"));
+ intr_test = gpio_reg_intr_test::type_id::create("intr_test");
+ intr_test.configure(.blk_parent(this));
+ intr_test.build();
+ default_map.add_reg(.rg(intr_test),
+ .offset(32'h8),
+ .rights("WO"));
+ data_in = gpio_reg_data_in::type_id::create("data_in");
+ data_in.configure(.blk_parent(this));
+ data_in.build();
+ default_map.add_reg(.rg(data_in),
+ .offset(32'hc),
+ .rights("RO"));
+ direct_out = gpio_reg_direct_out::type_id::create("direct_out");
+ direct_out.configure(.blk_parent(this));
+ direct_out.build();
+ default_map.add_reg(.rg(direct_out),
+ .offset(32'h10),
+ .rights("RW"));
+ masked_out_lower = gpio_reg_masked_out_lower::type_id::create("masked_out_lower");
+ masked_out_lower.configure(.blk_parent(this));
+ masked_out_lower.build();
+ default_map.add_reg(.rg(masked_out_lower),
+ .offset(32'h14),
+ .rights("RW"));
+ masked_out_upper = gpio_reg_masked_out_upper::type_id::create("masked_out_upper");
+ masked_out_upper.configure(.blk_parent(this));
+ masked_out_upper.build();
+ default_map.add_reg(.rg(masked_out_upper),
+ .offset(32'h18),
+ .rights("RW"));
+ direct_oe = gpio_reg_direct_oe::type_id::create("direct_oe");
+ direct_oe.configure(.blk_parent(this));
+ direct_oe.build();
+ default_map.add_reg(.rg(direct_oe),
+ .offset(32'h1c),
+ .rights("RW"));
+ masked_oe_lower = gpio_reg_masked_oe_lower::type_id::create("masked_oe_lower");
+ masked_oe_lower.configure(.blk_parent(this));
+ masked_oe_lower.build();
+ default_map.add_reg(.rg(masked_oe_lower),
+ .offset(32'h20),
+ .rights("RW"));
+ masked_oe_upper = gpio_reg_masked_oe_upper::type_id::create("masked_oe_upper");
+ masked_oe_upper.configure(.blk_parent(this));
+ masked_oe_upper.build();
+ default_map.add_reg(.rg(masked_oe_upper),
+ .offset(32'h24),
+ .rights("RW"));
+ intr_ctrl_en_rising = gpio_reg_intr_ctrl_en_rising::type_id::create("intr_ctrl_en_rising");
+ intr_ctrl_en_rising.configure(.blk_parent(this));
+ intr_ctrl_en_rising.build();
+ default_map.add_reg(.rg(intr_ctrl_en_rising),
+ .offset(32'h28),
+ .rights("RW"));
+ intr_ctrl_en_falling = gpio_reg_intr_ctrl_en_falling::type_id::create("intr_ctrl_en_falling");
+ intr_ctrl_en_falling.configure(.blk_parent(this));
+ intr_ctrl_en_falling.build();
+ default_map.add_reg(.rg(intr_ctrl_en_falling),
+ .offset(32'h2c),
+ .rights("RW"));
+ intr_ctrl_en_lvlhigh = gpio_reg_intr_ctrl_en_lvlhigh::type_id::create("intr_ctrl_en_lvlhigh");
+ intr_ctrl_en_lvlhigh.configure(.blk_parent(this));
+ intr_ctrl_en_lvlhigh.build();
+ default_map.add_reg(.rg(intr_ctrl_en_lvlhigh),
+ .offset(32'h30),
+ .rights("RW"));
+ intr_ctrl_en_lvllow = gpio_reg_intr_ctrl_en_lvllow::type_id::create("intr_ctrl_en_lvllow");
+ intr_ctrl_en_lvllow.configure(.blk_parent(this));
+ intr_ctrl_en_lvllow.build();
+ default_map.add_reg(.rg(intr_ctrl_en_lvllow),
+ .offset(32'h34),
+ .rights("RW"));
+ ctrl_en_input_filter = gpio_reg_ctrl_en_input_filter::type_id::create("ctrl_en_input_filter");
+ ctrl_en_input_filter.configure(.blk_parent(this));
+ ctrl_en_input_filter.build();
+ default_map.add_reg(.rg(ctrl_en_input_filter),
+ .offset(32'h38),
+ .rights("RW"));
+ endfunction : build
+
+endclass : gpio_reg_block
+
// Block: hmac
// Class: hmac_reg_intr_state
class hmac_reg_intr_state extends dv_base_reg;
@@ -1265,2245 +4933,6 @@
endclass : hmac_reg_block
-// Block: gpio
-// Class: gpio_reg_intr_state
-class gpio_reg_intr_state extends dv_base_reg;
- // fields
- rand dv_base_reg_field gpio;
-
- `uvm_object_utils(gpio_reg_intr_state)
-
- function new(string name = "gpio_reg_intr_state",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- gpio = dv_base_reg_field::type_id::create("gpio");
- gpio.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_state
-
-// Class: gpio_reg_intr_enable
-class gpio_reg_intr_enable extends dv_base_reg;
- // fields
- rand dv_base_reg_field gpio;
-
- `uvm_object_utils(gpio_reg_intr_enable)
-
- function new(string name = "gpio_reg_intr_enable",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- gpio = dv_base_reg_field::type_id::create("gpio");
- gpio.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_enable
-
-// Class: gpio_reg_intr_test
-class gpio_reg_intr_test extends dv_base_reg;
- // fields
- rand dv_base_reg_field gpio;
-
- `uvm_object_utils(gpio_reg_intr_test)
-
- function new(string name = "gpio_reg_intr_test",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- gpio = dv_base_reg_field::type_id::create("gpio");
- gpio.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_test
-
-// Class: gpio_reg_data_in
-class gpio_reg_data_in extends dv_base_reg;
- // fields
- rand dv_base_reg_field data_in;
-
- `uvm_object_utils(gpio_reg_data_in)
-
- function new(string name = "gpio_reg_data_in",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- data_in = dv_base_reg_field::type_id::create("data_in");
- data_in.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_data_in
-
-// Class: gpio_reg_direct_out
-class gpio_reg_direct_out extends dv_base_reg;
- // fields
- rand dv_base_reg_field direct_out;
-
- `uvm_object_utils(gpio_reg_direct_out)
-
- function new(string name = "gpio_reg_direct_out",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- direct_out = dv_base_reg_field::type_id::create("direct_out");
- direct_out.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_direct_out
-
-// Class: gpio_reg_masked_out_lower
-class gpio_reg_masked_out_lower extends dv_base_reg;
- // fields
- rand dv_base_reg_field data;
- rand dv_base_reg_field mask;
-
- `uvm_object_utils(gpio_reg_masked_out_lower)
-
- function new(string name = "gpio_reg_masked_out_lower",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- data = dv_base_reg_field::type_id::create("data");
- data.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- mask = dv_base_reg_field::type_id::create("mask");
- mask.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("WO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_masked_out_lower
-
-// Class: gpio_reg_masked_out_upper
-class gpio_reg_masked_out_upper extends dv_base_reg;
- // fields
- rand dv_base_reg_field data;
- rand dv_base_reg_field mask;
-
- `uvm_object_utils(gpio_reg_masked_out_upper)
-
- function new(string name = "gpio_reg_masked_out_upper",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- data = dv_base_reg_field::type_id::create("data");
- data.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- mask = dv_base_reg_field::type_id::create("mask");
- mask.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("WO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_masked_out_upper
-
-// Class: gpio_reg_direct_oe
-class gpio_reg_direct_oe extends dv_base_reg;
- // fields
- rand dv_base_reg_field direct_oe;
-
- `uvm_object_utils(gpio_reg_direct_oe)
-
- function new(string name = "gpio_reg_direct_oe",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- direct_oe = dv_base_reg_field::type_id::create("direct_oe");
- direct_oe.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_direct_oe
-
-// Class: gpio_reg_masked_oe_lower
-class gpio_reg_masked_oe_lower extends dv_base_reg;
- // fields
- rand dv_base_reg_field data;
- rand dv_base_reg_field mask;
-
- `uvm_object_utils(gpio_reg_masked_oe_lower)
-
- function new(string name = "gpio_reg_masked_oe_lower",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- data = dv_base_reg_field::type_id::create("data");
- data.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- mask = dv_base_reg_field::type_id::create("mask");
- mask.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_masked_oe_lower
-
-// Class: gpio_reg_masked_oe_upper
-class gpio_reg_masked_oe_upper extends dv_base_reg;
- // fields
- rand dv_base_reg_field data;
- rand dv_base_reg_field mask;
-
- `uvm_object_utils(gpio_reg_masked_oe_upper)
-
- function new(string name = "gpio_reg_masked_oe_upper",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- data = dv_base_reg_field::type_id::create("data");
- data.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- mask = dv_base_reg_field::type_id::create("mask");
- mask.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_masked_oe_upper
-
-// Class: gpio_reg_intr_ctrl_en_rising
-class gpio_reg_intr_ctrl_en_rising extends dv_base_reg;
- // fields
- rand dv_base_reg_field intr_ctrl_en_rising;
-
- `uvm_object_utils(gpio_reg_intr_ctrl_en_rising)
-
- function new(string name = "gpio_reg_intr_ctrl_en_rising",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- intr_ctrl_en_rising = dv_base_reg_field::type_id::create("intr_ctrl_en_rising");
- intr_ctrl_en_rising.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_rising
-
-// Class: gpio_reg_intr_ctrl_en_falling
-class gpio_reg_intr_ctrl_en_falling extends dv_base_reg;
- // fields
- rand dv_base_reg_field intr_ctrl_en_falling;
-
- `uvm_object_utils(gpio_reg_intr_ctrl_en_falling)
-
- function new(string name = "gpio_reg_intr_ctrl_en_falling",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- intr_ctrl_en_falling = dv_base_reg_field::type_id::create("intr_ctrl_en_falling");
- intr_ctrl_en_falling.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_falling
-
-// Class: gpio_reg_intr_ctrl_en_lvlhigh
-class gpio_reg_intr_ctrl_en_lvlhigh extends dv_base_reg;
- // fields
- rand dv_base_reg_field intr_ctrl_en_lvlhigh;
-
- `uvm_object_utils(gpio_reg_intr_ctrl_en_lvlhigh)
-
- function new(string name = "gpio_reg_intr_ctrl_en_lvlhigh",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- intr_ctrl_en_lvlhigh = dv_base_reg_field::type_id::create("intr_ctrl_en_lvlhigh");
- intr_ctrl_en_lvlhigh.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_lvlhigh
-
-// Class: gpio_reg_intr_ctrl_en_lvllow
-class gpio_reg_intr_ctrl_en_lvllow extends dv_base_reg;
- // fields
- rand dv_base_reg_field intr_ctrl_en_lvllow;
-
- `uvm_object_utils(gpio_reg_intr_ctrl_en_lvllow)
-
- function new(string name = "gpio_reg_intr_ctrl_en_lvllow",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- intr_ctrl_en_lvllow = dv_base_reg_field::type_id::create("intr_ctrl_en_lvllow");
- intr_ctrl_en_lvllow.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_intr_ctrl_en_lvllow
-
-// Class: gpio_reg_ctrl_en_input_filter
-class gpio_reg_ctrl_en_input_filter extends dv_base_reg;
- // fields
- rand dv_base_reg_field ctrl_en_input_filter;
-
- `uvm_object_utils(gpio_reg_ctrl_en_input_filter)
-
- function new(string name = "gpio_reg_ctrl_en_input_filter",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- ctrl_en_input_filter = dv_base_reg_field::type_id::create("ctrl_en_input_filter");
- ctrl_en_input_filter.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : gpio_reg_ctrl_en_input_filter
-
-// Class: gpio_reg_block
-class gpio_reg_block extends dv_base_reg_block;
- // registers
- rand gpio_reg_intr_state intr_state;
- rand gpio_reg_intr_enable intr_enable;
- rand gpio_reg_intr_test intr_test;
- rand gpio_reg_data_in data_in;
- rand gpio_reg_direct_out direct_out;
- rand gpio_reg_masked_out_lower masked_out_lower;
- rand gpio_reg_masked_out_upper masked_out_upper;
- rand gpio_reg_direct_oe direct_oe;
- rand gpio_reg_masked_oe_lower masked_oe_lower;
- rand gpio_reg_masked_oe_upper masked_oe_upper;
- rand gpio_reg_intr_ctrl_en_rising intr_ctrl_en_rising;
- rand gpio_reg_intr_ctrl_en_falling intr_ctrl_en_falling;
- rand gpio_reg_intr_ctrl_en_lvlhigh intr_ctrl_en_lvlhigh;
- rand gpio_reg_intr_ctrl_en_lvllow intr_ctrl_en_lvllow;
- rand gpio_reg_ctrl_en_input_filter ctrl_en_input_filter;
-
- `uvm_object_utils(gpio_reg_block)
-
- function new(string name = "gpio_reg_block",
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, has_coverage);
- endfunction : new
-
- virtual function void build(uvm_reg_addr_t base_addr);
- // create default map
- this.default_map = create_map(.name("default_map"),
- .base_addr(base_addr),
- .n_bytes(4),
- .endian(UVM_LITTLE_ENDIAN));
-
- // create registers
- intr_state = gpio_reg_intr_state::type_id::create("intr_state");
- intr_state.configure(.blk_parent(this));
- intr_state.build();
- default_map.add_reg(.rg(intr_state),
- .offset(32'h0),
- .rights("RW"));
- intr_enable = gpio_reg_intr_enable::type_id::create("intr_enable");
- intr_enable.configure(.blk_parent(this));
- intr_enable.build();
- default_map.add_reg(.rg(intr_enable),
- .offset(32'h4),
- .rights("RW"));
- intr_test = gpio_reg_intr_test::type_id::create("intr_test");
- intr_test.configure(.blk_parent(this));
- intr_test.build();
- default_map.add_reg(.rg(intr_test),
- .offset(32'h8),
- .rights("WO"));
- data_in = gpio_reg_data_in::type_id::create("data_in");
- data_in.configure(.blk_parent(this));
- data_in.build();
- default_map.add_reg(.rg(data_in),
- .offset(32'hc),
- .rights("RO"));
- direct_out = gpio_reg_direct_out::type_id::create("direct_out");
- direct_out.configure(.blk_parent(this));
- direct_out.build();
- default_map.add_reg(.rg(direct_out),
- .offset(32'h10),
- .rights("RW"));
- masked_out_lower = gpio_reg_masked_out_lower::type_id::create("masked_out_lower");
- masked_out_lower.configure(.blk_parent(this));
- masked_out_lower.build();
- default_map.add_reg(.rg(masked_out_lower),
- .offset(32'h14),
- .rights("RW"));
- masked_out_upper = gpio_reg_masked_out_upper::type_id::create("masked_out_upper");
- masked_out_upper.configure(.blk_parent(this));
- masked_out_upper.build();
- default_map.add_reg(.rg(masked_out_upper),
- .offset(32'h18),
- .rights("RW"));
- direct_oe = gpio_reg_direct_oe::type_id::create("direct_oe");
- direct_oe.configure(.blk_parent(this));
- direct_oe.build();
- default_map.add_reg(.rg(direct_oe),
- .offset(32'h1c),
- .rights("RW"));
- masked_oe_lower = gpio_reg_masked_oe_lower::type_id::create("masked_oe_lower");
- masked_oe_lower.configure(.blk_parent(this));
- masked_oe_lower.build();
- default_map.add_reg(.rg(masked_oe_lower),
- .offset(32'h20),
- .rights("RW"));
- masked_oe_upper = gpio_reg_masked_oe_upper::type_id::create("masked_oe_upper");
- masked_oe_upper.configure(.blk_parent(this));
- masked_oe_upper.build();
- default_map.add_reg(.rg(masked_oe_upper),
- .offset(32'h24),
- .rights("RW"));
- intr_ctrl_en_rising = gpio_reg_intr_ctrl_en_rising::type_id::create("intr_ctrl_en_rising");
- intr_ctrl_en_rising.configure(.blk_parent(this));
- intr_ctrl_en_rising.build();
- default_map.add_reg(.rg(intr_ctrl_en_rising),
- .offset(32'h28),
- .rights("RW"));
- intr_ctrl_en_falling = gpio_reg_intr_ctrl_en_falling::type_id::create("intr_ctrl_en_falling");
- intr_ctrl_en_falling.configure(.blk_parent(this));
- intr_ctrl_en_falling.build();
- default_map.add_reg(.rg(intr_ctrl_en_falling),
- .offset(32'h2c),
- .rights("RW"));
- intr_ctrl_en_lvlhigh = gpio_reg_intr_ctrl_en_lvlhigh::type_id::create("intr_ctrl_en_lvlhigh");
- intr_ctrl_en_lvlhigh.configure(.blk_parent(this));
- intr_ctrl_en_lvlhigh.build();
- default_map.add_reg(.rg(intr_ctrl_en_lvlhigh),
- .offset(32'h30),
- .rights("RW"));
- intr_ctrl_en_lvllow = gpio_reg_intr_ctrl_en_lvllow::type_id::create("intr_ctrl_en_lvllow");
- intr_ctrl_en_lvllow.configure(.blk_parent(this));
- intr_ctrl_en_lvllow.build();
- default_map.add_reg(.rg(intr_ctrl_en_lvllow),
- .offset(32'h34),
- .rights("RW"));
- ctrl_en_input_filter = gpio_reg_ctrl_en_input_filter::type_id::create("ctrl_en_input_filter");
- ctrl_en_input_filter.configure(.blk_parent(this));
- ctrl_en_input_filter.build();
- default_map.add_reg(.rg(ctrl_en_input_filter),
- .offset(32'h38),
- .rights("RW"));
- endfunction : build
-
-endclass : gpio_reg_block
-
-// Block: flash_ctrl
-// Class: flash_ctrl_reg_intr_state
-class flash_ctrl_reg_intr_state extends dv_base_reg;
- // fields
- rand dv_base_reg_field prog_empty;
- rand dv_base_reg_field prog_lvl;
- rand dv_base_reg_field rd_full;
- rand dv_base_reg_field rd_lvl;
- rand dv_base_reg_field op_done;
- rand dv_base_reg_field op_error;
-
- `uvm_object_utils(flash_ctrl_reg_intr_state)
-
- function new(string name = "flash_ctrl_reg_intr_state",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- prog_empty = dv_base_reg_field::type_id::create("prog_empty");
- prog_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_lvl = dv_base_reg_field::type_id::create("prog_lvl");
- prog_lvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_full = dv_base_reg_field::type_id::create("rd_full");
- rd_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_lvl = dv_base_reg_field::type_id::create("rd_lvl");
- rd_lvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op_done = dv_base_reg_field::type_id::create("op_done");
- op_done.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op_error = dv_base_reg_field::type_id::create("op_error");
- op_error.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_intr_state
-
-// Class: flash_ctrl_reg_intr_enable
-class flash_ctrl_reg_intr_enable extends dv_base_reg;
- // fields
- rand dv_base_reg_field prog_empty;
- rand dv_base_reg_field prog_lvl;
- rand dv_base_reg_field rd_full;
- rand dv_base_reg_field rd_lvl;
- rand dv_base_reg_field op_done;
- rand dv_base_reg_field op_error;
-
- `uvm_object_utils(flash_ctrl_reg_intr_enable)
-
- function new(string name = "flash_ctrl_reg_intr_enable",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- prog_empty = dv_base_reg_field::type_id::create("prog_empty");
- prog_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_lvl = dv_base_reg_field::type_id::create("prog_lvl");
- prog_lvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_full = dv_base_reg_field::type_id::create("rd_full");
- rd_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_lvl = dv_base_reg_field::type_id::create("rd_lvl");
- rd_lvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op_done = dv_base_reg_field::type_id::create("op_done");
- op_done.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op_error = dv_base_reg_field::type_id::create("op_error");
- op_error.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_intr_enable
-
-// Class: flash_ctrl_reg_intr_test
-class flash_ctrl_reg_intr_test extends dv_base_reg;
- // fields
- rand dv_base_reg_field prog_empty;
- rand dv_base_reg_field prog_lvl;
- rand dv_base_reg_field rd_full;
- rand dv_base_reg_field rd_lvl;
- rand dv_base_reg_field op_done;
- rand dv_base_reg_field op_error;
-
- `uvm_object_utils(flash_ctrl_reg_intr_test)
-
- function new(string name = "flash_ctrl_reg_intr_test",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- prog_empty = dv_base_reg_field::type_id::create("prog_empty");
- prog_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_lvl = dv_base_reg_field::type_id::create("prog_lvl");
- prog_lvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_full = dv_base_reg_field::type_id::create("rd_full");
- rd_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_lvl = dv_base_reg_field::type_id::create("rd_lvl");
- rd_lvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op_done = dv_base_reg_field::type_id::create("op_done");
- op_done.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op_error = dv_base_reg_field::type_id::create("op_error");
- op_error.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_intr_test
-
-// Class: flash_ctrl_reg_control
-class flash_ctrl_reg_control extends dv_base_reg;
- // fields
- rand dv_base_reg_field start;
- rand dv_base_reg_field op;
- rand dv_base_reg_field erase_sel;
- rand dv_base_reg_field fifo_rst;
- rand dv_base_reg_field num;
-
- `uvm_object_utils(flash_ctrl_reg_control)
-
- function new(string name = "flash_ctrl_reg_control",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- start = dv_base_reg_field::type_id::create("start");
- start.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- op = dv_base_reg_field::type_id::create("op");
- op.configure(
- .parent(this),
- .size(2),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_sel = dv_base_reg_field::type_id::create("erase_sel");
- erase_sel.configure(
- .parent(this),
- .size(1),
- .lsb_pos(6),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- fifo_rst = dv_base_reg_field::type_id::create("fifo_rst");
- fifo_rst.configure(
- .parent(this),
- .size(1),
- .lsb_pos(7),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- num = dv_base_reg_field::type_id::create("num");
- num.configure(
- .parent(this),
- .size(12),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_control
-
-// Class: flash_ctrl_reg_addr
-class flash_ctrl_reg_addr extends dv_base_reg;
- // fields
- rand dv_base_reg_field start;
-
- `uvm_object_utils(flash_ctrl_reg_addr)
-
- function new(string name = "flash_ctrl_reg_addr",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- start = dv_base_reg_field::type_id::create("start");
- start.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_addr
-
-// Class: flash_ctrl_reg_mp_region_cfg0
-class flash_ctrl_reg_mp_region_cfg0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en0;
- rand dv_base_reg_field rd_en0;
- rand dv_base_reg_field prog_en0;
- rand dv_base_reg_field erase_en0;
- rand dv_base_reg_field base0;
- rand dv_base_reg_field size0;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg0)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en0 = dv_base_reg_field::type_id::create("en0");
- en0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en0 = dv_base_reg_field::type_id::create("rd_en0");
- rd_en0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en0 = dv_base_reg_field::type_id::create("prog_en0");
- prog_en0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en0 = dv_base_reg_field::type_id::create("erase_en0");
- erase_en0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base0 = dv_base_reg_field::type_id::create("base0");
- base0.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size0 = dv_base_reg_field::type_id::create("size0");
- size0.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg0
-
-// Class: flash_ctrl_reg_mp_region_cfg1
-class flash_ctrl_reg_mp_region_cfg1 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en1;
- rand dv_base_reg_field rd_en1;
- rand dv_base_reg_field prog_en1;
- rand dv_base_reg_field erase_en1;
- rand dv_base_reg_field base1;
- rand dv_base_reg_field size1;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg1)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg1",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en1 = dv_base_reg_field::type_id::create("en1");
- en1.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en1 = dv_base_reg_field::type_id::create("rd_en1");
- rd_en1.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en1 = dv_base_reg_field::type_id::create("prog_en1");
- prog_en1.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en1 = dv_base_reg_field::type_id::create("erase_en1");
- erase_en1.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base1 = dv_base_reg_field::type_id::create("base1");
- base1.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size1 = dv_base_reg_field::type_id::create("size1");
- size1.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg1
-
-// Class: flash_ctrl_reg_mp_region_cfg2
-class flash_ctrl_reg_mp_region_cfg2 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en2;
- rand dv_base_reg_field rd_en2;
- rand dv_base_reg_field prog_en2;
- rand dv_base_reg_field erase_en2;
- rand dv_base_reg_field base2;
- rand dv_base_reg_field size2;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg2)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg2",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en2 = dv_base_reg_field::type_id::create("en2");
- en2.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en2 = dv_base_reg_field::type_id::create("rd_en2");
- rd_en2.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en2 = dv_base_reg_field::type_id::create("prog_en2");
- prog_en2.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en2 = dv_base_reg_field::type_id::create("erase_en2");
- erase_en2.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base2 = dv_base_reg_field::type_id::create("base2");
- base2.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size2 = dv_base_reg_field::type_id::create("size2");
- size2.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg2
-
-// Class: flash_ctrl_reg_mp_region_cfg3
-class flash_ctrl_reg_mp_region_cfg3 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en3;
- rand dv_base_reg_field rd_en3;
- rand dv_base_reg_field prog_en3;
- rand dv_base_reg_field erase_en3;
- rand dv_base_reg_field base3;
- rand dv_base_reg_field size3;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg3)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg3",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en3 = dv_base_reg_field::type_id::create("en3");
- en3.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en3 = dv_base_reg_field::type_id::create("rd_en3");
- rd_en3.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en3 = dv_base_reg_field::type_id::create("prog_en3");
- prog_en3.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en3 = dv_base_reg_field::type_id::create("erase_en3");
- erase_en3.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base3 = dv_base_reg_field::type_id::create("base3");
- base3.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size3 = dv_base_reg_field::type_id::create("size3");
- size3.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg3
-
-// Class: flash_ctrl_reg_mp_region_cfg4
-class flash_ctrl_reg_mp_region_cfg4 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en4;
- rand dv_base_reg_field rd_en4;
- rand dv_base_reg_field prog_en4;
- rand dv_base_reg_field erase_en4;
- rand dv_base_reg_field base4;
- rand dv_base_reg_field size4;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg4)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg4",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en4 = dv_base_reg_field::type_id::create("en4");
- en4.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en4 = dv_base_reg_field::type_id::create("rd_en4");
- rd_en4.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en4 = dv_base_reg_field::type_id::create("prog_en4");
- prog_en4.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en4 = dv_base_reg_field::type_id::create("erase_en4");
- erase_en4.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base4 = dv_base_reg_field::type_id::create("base4");
- base4.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size4 = dv_base_reg_field::type_id::create("size4");
- size4.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg4
-
-// Class: flash_ctrl_reg_mp_region_cfg5
-class flash_ctrl_reg_mp_region_cfg5 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en5;
- rand dv_base_reg_field rd_en5;
- rand dv_base_reg_field prog_en5;
- rand dv_base_reg_field erase_en5;
- rand dv_base_reg_field base5;
- rand dv_base_reg_field size5;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg5)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg5",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en5 = dv_base_reg_field::type_id::create("en5");
- en5.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en5 = dv_base_reg_field::type_id::create("rd_en5");
- rd_en5.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en5 = dv_base_reg_field::type_id::create("prog_en5");
- prog_en5.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en5 = dv_base_reg_field::type_id::create("erase_en5");
- erase_en5.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base5 = dv_base_reg_field::type_id::create("base5");
- base5.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size5 = dv_base_reg_field::type_id::create("size5");
- size5.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg5
-
-// Class: flash_ctrl_reg_mp_region_cfg6
-class flash_ctrl_reg_mp_region_cfg6 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en6;
- rand dv_base_reg_field rd_en6;
- rand dv_base_reg_field prog_en6;
- rand dv_base_reg_field erase_en6;
- rand dv_base_reg_field base6;
- rand dv_base_reg_field size6;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg6)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg6",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en6 = dv_base_reg_field::type_id::create("en6");
- en6.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en6 = dv_base_reg_field::type_id::create("rd_en6");
- rd_en6.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en6 = dv_base_reg_field::type_id::create("prog_en6");
- prog_en6.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en6 = dv_base_reg_field::type_id::create("erase_en6");
- erase_en6.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base6 = dv_base_reg_field::type_id::create("base6");
- base6.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size6 = dv_base_reg_field::type_id::create("size6");
- size6.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg6
-
-// Class: flash_ctrl_reg_mp_region_cfg7
-class flash_ctrl_reg_mp_region_cfg7 extends dv_base_reg;
- // fields
- rand dv_base_reg_field en7;
- rand dv_base_reg_field rd_en7;
- rand dv_base_reg_field prog_en7;
- rand dv_base_reg_field erase_en7;
- rand dv_base_reg_field base7;
- rand dv_base_reg_field size7;
-
- `uvm_object_utils(flash_ctrl_reg_mp_region_cfg7)
-
- function new(string name = "flash_ctrl_reg_mp_region_cfg7",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- en7 = dv_base_reg_field::type_id::create("en7");
- en7.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_en7 = dv_base_reg_field::type_id::create("rd_en7");
- rd_en7.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en7 = dv_base_reg_field::type_id::create("prog_en7");
- prog_en7.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en7 = dv_base_reg_field::type_id::create("erase_en7");
- erase_en7.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- base7 = dv_base_reg_field::type_id::create("base7");
- base7.configure(
- .parent(this),
- .size(9),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- size7 = dv_base_reg_field::type_id::create("size7");
- size7.configure(
- .parent(this),
- .size(9),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_region_cfg7
-
-// Class: flash_ctrl_reg_default_region
-class flash_ctrl_reg_default_region extends dv_base_reg;
- // fields
- rand dv_base_reg_field rd_en;
- rand dv_base_reg_field prog_en;
- rand dv_base_reg_field erase_en;
-
- `uvm_object_utils(flash_ctrl_reg_default_region)
-
- function new(string name = "flash_ctrl_reg_default_region",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rd_en = dv_base_reg_field::type_id::create("rd_en");
- rd_en.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_en = dv_base_reg_field::type_id::create("prog_en");
- prog_en.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en = dv_base_reg_field::type_id::create("erase_en");
- erase_en.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_default_region
-
-// Class: flash_ctrl_reg_mp_bank_cfg
-class flash_ctrl_reg_mp_bank_cfg extends dv_base_reg;
- // fields
- rand dv_base_reg_field erase_en0;
- rand dv_base_reg_field erase_en1;
-
- `uvm_object_utils(flash_ctrl_reg_mp_bank_cfg)
-
- function new(string name = "flash_ctrl_reg_mp_bank_cfg",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- erase_en0 = dv_base_reg_field::type_id::create("erase_en0");
- erase_en0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- erase_en1 = dv_base_reg_field::type_id::create("erase_en1");
- erase_en1.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_mp_bank_cfg
-
-// Class: flash_ctrl_reg_op_status
-class flash_ctrl_reg_op_status extends dv_base_reg;
- // fields
- rand dv_base_reg_field done;
- rand dv_base_reg_field err;
-
- `uvm_object_utils(flash_ctrl_reg_op_status)
-
- function new(string name = "flash_ctrl_reg_op_status",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- done = dv_base_reg_field::type_id::create("done");
- done.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- err = dv_base_reg_field::type_id::create("err");
- err.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_op_status
-
-// Class: flash_ctrl_reg_status
-class flash_ctrl_reg_status extends dv_base_reg;
- // fields
- rand dv_base_reg_field rd_full;
- rand dv_base_reg_field rd_empty;
- rand dv_base_reg_field prog_full;
- rand dv_base_reg_field prog_empty;
- rand dv_base_reg_field init_wip;
- rand dv_base_reg_field error_page;
- rand dv_base_reg_field error_bank;
-
- `uvm_object_utils(flash_ctrl_reg_status)
-
- function new(string name = "flash_ctrl_reg_status",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rd_full = dv_base_reg_field::type_id::create("rd_full");
- rd_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd_empty = dv_base_reg_field::type_id::create("rd_empty");
- rd_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_full = dv_base_reg_field::type_id::create("prog_full");
- prog_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- prog_empty = dv_base_reg_field::type_id::create("prog_empty");
- prog_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- init_wip = dv_base_reg_field::type_id::create("init_wip");
- init_wip.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- error_page = dv_base_reg_field::type_id::create("error_page");
- error_page.configure(
- .parent(this),
- .size(9),
- .lsb_pos(8),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- error_bank = dv_base_reg_field::type_id::create("error_bank");
- error_bank.configure(
- .parent(this),
- .size(1),
- .lsb_pos(17),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_status
-
-// Class: flash_ctrl_reg_scratch
-class flash_ctrl_reg_scratch extends dv_base_reg;
- // fields
- rand dv_base_reg_field data;
-
- `uvm_object_utils(flash_ctrl_reg_scratch)
-
- function new(string name = "flash_ctrl_reg_scratch",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- data = dv_base_reg_field::type_id::create("data");
- data.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_scratch
-
-// Class: flash_ctrl_reg_fifo_lvl
-class flash_ctrl_reg_fifo_lvl extends dv_base_reg;
- // fields
- rand dv_base_reg_field prog;
- rand dv_base_reg_field rd;
-
- `uvm_object_utils(flash_ctrl_reg_fifo_lvl)
-
- function new(string name = "flash_ctrl_reg_fifo_lvl",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- prog = dv_base_reg_field::type_id::create("prog");
- prog.configure(
- .parent(this),
- .size(5),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(15),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rd = dv_base_reg_field::type_id::create("rd");
- rd.configure(
- .parent(this),
- .size(5),
- .lsb_pos(8),
- .access("RW"),
- .volatile(0),
- .reset(15),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : flash_ctrl_reg_fifo_lvl
-
-// Class: flash_ctrl_mem_prog_fifo
-class flash_ctrl_mem_prog_fifo extends dv_base_mem;
-
- `uvm_object_utils(flash_ctrl_mem_prog_fifo)
-
- function new(string name = "flash_ctrl_mem_prog_fifo",
- longint unsigned size = 1,
- int unsigned n_bits = 32,
- string access = "RW"/* TODO:"WO"*/,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, size, n_bits, access, has_coverage);
- endfunction : new
-
-endclass : flash_ctrl_mem_prog_fifo
-
-// Class: flash_ctrl_mem_rd_fifo
-class flash_ctrl_mem_rd_fifo extends dv_base_mem;
-
- `uvm_object_utils(flash_ctrl_mem_rd_fifo)
-
- function new(string name = "flash_ctrl_mem_rd_fifo",
- longint unsigned size = 1,
- int unsigned n_bits = 32,
- string access = "RW"/* TODO:"RO"*/,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, size, n_bits, access, has_coverage);
- endfunction : new
-
-endclass : flash_ctrl_mem_rd_fifo
-
-// Class: flash_ctrl_reg_block
-class flash_ctrl_reg_block extends dv_base_reg_block;
- // registers
- rand flash_ctrl_reg_intr_state intr_state;
- rand flash_ctrl_reg_intr_enable intr_enable;
- rand flash_ctrl_reg_intr_test intr_test;
- rand flash_ctrl_reg_control control;
- rand flash_ctrl_reg_addr addr;
- rand flash_ctrl_reg_mp_region_cfg0 mp_region_cfg0;
- rand flash_ctrl_reg_mp_region_cfg1 mp_region_cfg1;
- rand flash_ctrl_reg_mp_region_cfg2 mp_region_cfg2;
- rand flash_ctrl_reg_mp_region_cfg3 mp_region_cfg3;
- rand flash_ctrl_reg_mp_region_cfg4 mp_region_cfg4;
- rand flash_ctrl_reg_mp_region_cfg5 mp_region_cfg5;
- rand flash_ctrl_reg_mp_region_cfg6 mp_region_cfg6;
- rand flash_ctrl_reg_mp_region_cfg7 mp_region_cfg7;
- rand flash_ctrl_reg_default_region default_region;
- rand flash_ctrl_reg_mp_bank_cfg mp_bank_cfg;
- rand flash_ctrl_reg_op_status op_status;
- rand flash_ctrl_reg_status status;
- rand flash_ctrl_reg_scratch scratch;
- rand flash_ctrl_reg_fifo_lvl fifo_lvl;
- // memories
- rand flash_ctrl_mem_prog_fifo prog_fifo;
- rand flash_ctrl_mem_rd_fifo rd_fifo;
-
- `uvm_object_utils(flash_ctrl_reg_block)
-
- function new(string name = "flash_ctrl_reg_block",
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, has_coverage);
- endfunction : new
-
- virtual function void build(uvm_reg_addr_t base_addr);
- // create default map
- this.default_map = create_map(.name("default_map"),
- .base_addr(base_addr),
- .n_bytes(4),
- .endian(UVM_LITTLE_ENDIAN));
-
- // create registers
- intr_state = flash_ctrl_reg_intr_state::type_id::create("intr_state");
- intr_state.configure(.blk_parent(this));
- intr_state.build();
- default_map.add_reg(.rg(intr_state),
- .offset(32'h0),
- .rights("RW"));
- intr_enable = flash_ctrl_reg_intr_enable::type_id::create("intr_enable");
- intr_enable.configure(.blk_parent(this));
- intr_enable.build();
- default_map.add_reg(.rg(intr_enable),
- .offset(32'h4),
- .rights("RW"));
- intr_test = flash_ctrl_reg_intr_test::type_id::create("intr_test");
- intr_test.configure(.blk_parent(this));
- intr_test.build();
- default_map.add_reg(.rg(intr_test),
- .offset(32'h8),
- .rights("WO"));
- control = flash_ctrl_reg_control::type_id::create("control");
- control.configure(.blk_parent(this));
- control.build();
- default_map.add_reg(.rg(control),
- .offset(32'hc),
- .rights("RW"));
- addr = flash_ctrl_reg_addr::type_id::create("addr");
- addr.configure(.blk_parent(this));
- addr.build();
- default_map.add_reg(.rg(addr),
- .offset(32'h10),
- .rights("RW"));
- mp_region_cfg0 = flash_ctrl_reg_mp_region_cfg0::type_id::create("mp_region_cfg0");
- mp_region_cfg0.configure(.blk_parent(this));
- mp_region_cfg0.build();
- default_map.add_reg(.rg(mp_region_cfg0),
- .offset(32'h14),
- .rights("RW"));
- mp_region_cfg1 = flash_ctrl_reg_mp_region_cfg1::type_id::create("mp_region_cfg1");
- mp_region_cfg1.configure(.blk_parent(this));
- mp_region_cfg1.build();
- default_map.add_reg(.rg(mp_region_cfg1),
- .offset(32'h18),
- .rights("RW"));
- mp_region_cfg2 = flash_ctrl_reg_mp_region_cfg2::type_id::create("mp_region_cfg2");
- mp_region_cfg2.configure(.blk_parent(this));
- mp_region_cfg2.build();
- default_map.add_reg(.rg(mp_region_cfg2),
- .offset(32'h1c),
- .rights("RW"));
- mp_region_cfg3 = flash_ctrl_reg_mp_region_cfg3::type_id::create("mp_region_cfg3");
- mp_region_cfg3.configure(.blk_parent(this));
- mp_region_cfg3.build();
- default_map.add_reg(.rg(mp_region_cfg3),
- .offset(32'h20),
- .rights("RW"));
- mp_region_cfg4 = flash_ctrl_reg_mp_region_cfg4::type_id::create("mp_region_cfg4");
- mp_region_cfg4.configure(.blk_parent(this));
- mp_region_cfg4.build();
- default_map.add_reg(.rg(mp_region_cfg4),
- .offset(32'h24),
- .rights("RW"));
- mp_region_cfg5 = flash_ctrl_reg_mp_region_cfg5::type_id::create("mp_region_cfg5");
- mp_region_cfg5.configure(.blk_parent(this));
- mp_region_cfg5.build();
- default_map.add_reg(.rg(mp_region_cfg5),
- .offset(32'h28),
- .rights("RW"));
- mp_region_cfg6 = flash_ctrl_reg_mp_region_cfg6::type_id::create("mp_region_cfg6");
- mp_region_cfg6.configure(.blk_parent(this));
- mp_region_cfg6.build();
- default_map.add_reg(.rg(mp_region_cfg6),
- .offset(32'h2c),
- .rights("RW"));
- mp_region_cfg7 = flash_ctrl_reg_mp_region_cfg7::type_id::create("mp_region_cfg7");
- mp_region_cfg7.configure(.blk_parent(this));
- mp_region_cfg7.build();
- default_map.add_reg(.rg(mp_region_cfg7),
- .offset(32'h30),
- .rights("RW"));
- default_region = flash_ctrl_reg_default_region::type_id::create("default_region");
- default_region.configure(.blk_parent(this));
- default_region.build();
- default_map.add_reg(.rg(default_region),
- .offset(32'h34),
- .rights("RW"));
- mp_bank_cfg = flash_ctrl_reg_mp_bank_cfg::type_id::create("mp_bank_cfg");
- mp_bank_cfg.configure(.blk_parent(this));
- mp_bank_cfg.build();
- default_map.add_reg(.rg(mp_bank_cfg),
- .offset(32'h38),
- .rights("RW"));
- op_status = flash_ctrl_reg_op_status::type_id::create("op_status");
- op_status.configure(.blk_parent(this));
- op_status.build();
- default_map.add_reg(.rg(op_status),
- .offset(32'h3c),
- .rights("RW"));
- status = flash_ctrl_reg_status::type_id::create("status");
- status.configure(.blk_parent(this));
- status.build();
- default_map.add_reg(.rg(status),
- .offset(32'h40),
- .rights("RO"));
- scratch = flash_ctrl_reg_scratch::type_id::create("scratch");
- scratch.configure(.blk_parent(this));
- scratch.build();
- default_map.add_reg(.rg(scratch),
- .offset(32'h44),
- .rights("RW"));
- fifo_lvl = flash_ctrl_reg_fifo_lvl::type_id::create("fifo_lvl");
- fifo_lvl.configure(.blk_parent(this));
- fifo_lvl.build();
- default_map.add_reg(.rg(fifo_lvl),
- .offset(32'h48),
- .rights("RW"));
-
- // create memories
- prog_fifo = flash_ctrl_mem_prog_fifo::type_id::create("prog_fifo");
- prog_fifo.configure(.parent(this));
- default_map.add_mem(.mem(prog_fifo),
- .offset(32'h4c),
- .rights("WO"));
- rd_fifo = flash_ctrl_mem_rd_fifo::type_id::create("rd_fifo");
- rd_fifo.configure(.parent(this));
- default_map.add_mem(.mem(rd_fifo),
- .offset(32'h50),
- .rights("RO"));
- endfunction : build
-
-endclass : flash_ctrl_reg_block
-
// Block: uart
// Class: uart_reg_intr_state
class uart_reg_intr_state extends dv_base_reg;
@@ -4452,1263 +5881,6 @@
endclass : uart_reg_block
-// Block: spi_device
-// Class: spi_device_reg_intr_state
-class spi_device_reg_intr_state extends dv_base_reg;
- // fields
- rand dv_base_reg_field rxf;
- rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txlvl;
- rand dv_base_reg_field rxerr;
- rand dv_base_reg_field rxoverflow;
- rand dv_base_reg_field txunderflow;
-
- `uvm_object_utils(spi_device_reg_intr_state)
-
- function new(string name = "spi_device_reg_intr_state",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rxf = dv_base_reg_field::type_id::create("rxf");
- rxf.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxlvl = dv_base_reg_field::type_id::create("rxlvl");
- rxlvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txlvl = dv_base_reg_field::type_id::create("txlvl");
- txlvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxerr = dv_base_reg_field::type_id::create("rxerr");
- rxerr.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxoverflow = dv_base_reg_field::type_id::create("rxoverflow");
- rxoverflow.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txunderflow = dv_base_reg_field::type_id::create("txunderflow");
- txunderflow.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_intr_state
-
-// Class: spi_device_reg_intr_enable
-class spi_device_reg_intr_enable extends dv_base_reg;
- // fields
- rand dv_base_reg_field rxf;
- rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txlvl;
- rand dv_base_reg_field rxerr;
- rand dv_base_reg_field rxoverflow;
- rand dv_base_reg_field txunderflow;
-
- `uvm_object_utils(spi_device_reg_intr_enable)
-
- function new(string name = "spi_device_reg_intr_enable",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rxf = dv_base_reg_field::type_id::create("rxf");
- rxf.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxlvl = dv_base_reg_field::type_id::create("rxlvl");
- rxlvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txlvl = dv_base_reg_field::type_id::create("txlvl");
- txlvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxerr = dv_base_reg_field::type_id::create("rxerr");
- rxerr.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxoverflow = dv_base_reg_field::type_id::create("rxoverflow");
- rxoverflow.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txunderflow = dv_base_reg_field::type_id::create("txunderflow");
- txunderflow.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_intr_enable
-
-// Class: spi_device_reg_intr_test
-class spi_device_reg_intr_test extends dv_base_reg;
- // fields
- rand dv_base_reg_field rxf;
- rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txlvl;
- rand dv_base_reg_field rxerr;
- rand dv_base_reg_field rxoverflow;
- rand dv_base_reg_field txunderflow;
-
- `uvm_object_utils(spi_device_reg_intr_test)
-
- function new(string name = "spi_device_reg_intr_test",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rxf = dv_base_reg_field::type_id::create("rxf");
- rxf.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxlvl = dv_base_reg_field::type_id::create("rxlvl");
- rxlvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txlvl = dv_base_reg_field::type_id::create("txlvl");
- txlvl.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxerr = dv_base_reg_field::type_id::create("rxerr");
- rxerr.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxoverflow = dv_base_reg_field::type_id::create("rxoverflow");
- rxoverflow.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txunderflow = dv_base_reg_field::type_id::create("txunderflow");
- txunderflow.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_intr_test
-
-// Class: spi_device_reg_control
-class spi_device_reg_control extends dv_base_reg;
- // fields
- rand dv_base_reg_field abort;
- rand dv_base_reg_field mode;
- rand dv_base_reg_field rst_txfifo;
- rand dv_base_reg_field rst_rxfifo;
-
- `uvm_object_utils(spi_device_reg_control)
-
- function new(string name = "spi_device_reg_control",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- abort = dv_base_reg_field::type_id::create("abort");
- abort.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- mode = dv_base_reg_field::type_id::create("mode");
- mode.configure(
- .parent(this),
- .size(2),
- .lsb_pos(4),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rst_txfifo = dv_base_reg_field::type_id::create("rst_txfifo");
- rst_txfifo.configure(
- .parent(this),
- .size(1),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rst_rxfifo = dv_base_reg_field::type_id::create("rst_rxfifo");
- rst_rxfifo.configure(
- .parent(this),
- .size(1),
- .lsb_pos(17),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_control
-
-// Class: spi_device_reg_cfg
-class spi_device_reg_cfg extends dv_base_reg;
- // fields
- rand dv_base_reg_field cpol;
- rand dv_base_reg_field cpha;
- rand dv_base_reg_field tx_order;
- rand dv_base_reg_field rx_order;
- rand dv_base_reg_field timer_v;
-
- `uvm_object_utils(spi_device_reg_cfg)
-
- function new(string name = "spi_device_reg_cfg",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- cpol = dv_base_reg_field::type_id::create("cpol");
- cpol.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- cpha = dv_base_reg_field::type_id::create("cpha");
- cpha.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- tx_order = dv_base_reg_field::type_id::create("tx_order");
- tx_order.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rx_order = dv_base_reg_field::type_id::create("rx_order");
- rx_order.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- timer_v = dv_base_reg_field::type_id::create("timer_v");
- timer_v.configure(
- .parent(this),
- .size(8),
- .lsb_pos(8),
- .access("RW"),
- .volatile(0),
- .reset(127),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_cfg
-
-// Class: spi_device_reg_fifo_level
-class spi_device_reg_fifo_level extends dv_base_reg;
- // fields
- rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txlvl;
-
- `uvm_object_utils(spi_device_reg_fifo_level)
-
- function new(string name = "spi_device_reg_fifo_level",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rxlvl = dv_base_reg_field::type_id::create("rxlvl");
- rxlvl.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(128),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txlvl = dv_base_reg_field::type_id::create("txlvl");
- txlvl.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_fifo_level
-
-// Class: spi_device_reg_async_fifo_level
-class spi_device_reg_async_fifo_level extends dv_base_reg;
- // fields
- rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txlvl;
-
- `uvm_object_utils(spi_device_reg_async_fifo_level)
-
- function new(string name = "spi_device_reg_async_fifo_level",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rxlvl = dv_base_reg_field::type_id::create("rxlvl");
- rxlvl.configure(
- .parent(this),
- .size(8),
- .lsb_pos(0),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txlvl = dv_base_reg_field::type_id::create("txlvl");
- txlvl.configure(
- .parent(this),
- .size(8),
- .lsb_pos(16),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_async_fifo_level
-
-// Class: spi_device_reg_status
-class spi_device_reg_status extends dv_base_reg;
- // fields
- rand dv_base_reg_field rxf_full;
- rand dv_base_reg_field rxf_empty;
- rand dv_base_reg_field txf_full;
- rand dv_base_reg_field txf_empty;
- rand dv_base_reg_field abort_done;
- rand dv_base_reg_field csb;
-
- `uvm_object_utils(spi_device_reg_status)
-
- function new(string name = "spi_device_reg_status",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rxf_full = dv_base_reg_field::type_id::create("rxf_full");
- rxf_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- rxf_empty = dv_base_reg_field::type_id::create("rxf_empty");
- rxf_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(1),
- .access("RO"),
- .volatile(1),
- .reset(1),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txf_full = dv_base_reg_field::type_id::create("txf_full");
- txf_full.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txf_empty = dv_base_reg_field::type_id::create("txf_empty");
- txf_empty.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RO"),
- .volatile(1),
- .reset(1),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- abort_done = dv_base_reg_field::type_id::create("abort_done");
- abort_done.configure(
- .parent(this),
- .size(1),
- .lsb_pos(4),
- .access("RO"),
- .volatile(1),
- .reset(1),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- csb = dv_base_reg_field::type_id::create("csb");
- csb.configure(
- .parent(this),
- .size(1),
- .lsb_pos(5),
- .access("RO"),
- .volatile(1),
- .reset(1),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_status
-
-// Class: spi_device_reg_rxf_ptr
-class spi_device_reg_rxf_ptr extends dv_base_reg;
- // fields
- rand dv_base_reg_field rptr;
- rand dv_base_reg_field wptr;
-
- `uvm_object_utils(spi_device_reg_rxf_ptr)
-
- function new(string name = "spi_device_reg_rxf_ptr",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rptr = dv_base_reg_field::type_id::create("rptr");
- rptr.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- wptr = dv_base_reg_field::type_id::create("wptr");
- wptr.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_rxf_ptr
-
-// Class: spi_device_reg_txf_ptr
-class spi_device_reg_txf_ptr extends dv_base_reg;
- // fields
- rand dv_base_reg_field rptr;
- rand dv_base_reg_field wptr;
-
- `uvm_object_utils(spi_device_reg_txf_ptr)
-
- function new(string name = "spi_device_reg_txf_ptr",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- rptr = dv_base_reg_field::type_id::create("rptr");
- rptr.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RO"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- wptr = dv_base_reg_field::type_id::create("wptr");
- wptr.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_txf_ptr
-
-// Class: spi_device_reg_rxf_addr
-class spi_device_reg_rxf_addr extends dv_base_reg;
- // fields
- rand dv_base_reg_field base;
- rand dv_base_reg_field limit;
-
- `uvm_object_utils(spi_device_reg_rxf_addr)
-
- function new(string name = "spi_device_reg_rxf_addr",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- base = dv_base_reg_field::type_id::create("base");
- base.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- limit = dv_base_reg_field::type_id::create("limit");
- limit.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(508),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_rxf_addr
-
-// Class: spi_device_reg_txf_addr
-class spi_device_reg_txf_addr extends dv_base_reg;
- // fields
- rand dv_base_reg_field base;
- rand dv_base_reg_field limit;
-
- `uvm_object_utils(spi_device_reg_txf_addr)
-
- function new(string name = "spi_device_reg_txf_addr",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- base = dv_base_reg_field::type_id::create("base");
- base.configure(
- .parent(this),
- .size(16),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(512),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- limit = dv_base_reg_field::type_id::create("limit");
- limit.configure(
- .parent(this),
- .size(16),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(1020),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : spi_device_reg_txf_addr
-
-// Class: spi_device_mem_buffer
-class spi_device_mem_buffer extends dv_base_mem;
-
- `uvm_object_utils(spi_device_mem_buffer)
-
- function new(string name = "spi_device_mem_buffer",
- longint unsigned size = 512,
- int unsigned n_bits = 32,
- string access = "RW"/* TODO:"RW"*/,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, size, n_bits, access, has_coverage);
- endfunction : new
-
-endclass : spi_device_mem_buffer
-
-// Class: spi_device_reg_block
-class spi_device_reg_block extends dv_base_reg_block;
- // registers
- rand spi_device_reg_intr_state intr_state;
- rand spi_device_reg_intr_enable intr_enable;
- rand spi_device_reg_intr_test intr_test;
- rand spi_device_reg_control control;
- rand spi_device_reg_cfg cfg;
- rand spi_device_reg_fifo_level fifo_level;
- rand spi_device_reg_async_fifo_level async_fifo_level;
- rand spi_device_reg_status status;
- rand spi_device_reg_rxf_ptr rxf_ptr;
- rand spi_device_reg_txf_ptr txf_ptr;
- rand spi_device_reg_rxf_addr rxf_addr;
- rand spi_device_reg_txf_addr txf_addr;
- // memories
- rand spi_device_mem_buffer buffer;
-
- `uvm_object_utils(spi_device_reg_block)
-
- function new(string name = "spi_device_reg_block",
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, has_coverage);
- endfunction : new
-
- virtual function void build(uvm_reg_addr_t base_addr);
- // create default map
- this.default_map = create_map(.name("default_map"),
- .base_addr(base_addr),
- .n_bytes(4),
- .endian(UVM_LITTLE_ENDIAN));
-
- // create registers
- intr_state = spi_device_reg_intr_state::type_id::create("intr_state");
- intr_state.configure(.blk_parent(this));
- intr_state.build();
- default_map.add_reg(.rg(intr_state),
- .offset(32'h0),
- .rights("RW"));
- intr_enable = spi_device_reg_intr_enable::type_id::create("intr_enable");
- intr_enable.configure(.blk_parent(this));
- intr_enable.build();
- default_map.add_reg(.rg(intr_enable),
- .offset(32'h4),
- .rights("RW"));
- intr_test = spi_device_reg_intr_test::type_id::create("intr_test");
- intr_test.configure(.blk_parent(this));
- intr_test.build();
- default_map.add_reg(.rg(intr_test),
- .offset(32'h8),
- .rights("WO"));
- control = spi_device_reg_control::type_id::create("control");
- control.configure(.blk_parent(this));
- control.build();
- default_map.add_reg(.rg(control),
- .offset(32'hc),
- .rights("RW"));
- cfg = spi_device_reg_cfg::type_id::create("cfg");
- cfg.configure(.blk_parent(this));
- cfg.build();
- default_map.add_reg(.rg(cfg),
- .offset(32'h10),
- .rights("RW"));
- fifo_level = spi_device_reg_fifo_level::type_id::create("fifo_level");
- fifo_level.configure(.blk_parent(this));
- fifo_level.build();
- default_map.add_reg(.rg(fifo_level),
- .offset(32'h14),
- .rights("RW"));
- async_fifo_level = spi_device_reg_async_fifo_level::type_id::create("async_fifo_level");
- async_fifo_level.configure(.blk_parent(this));
- async_fifo_level.build();
- default_map.add_reg(.rg(async_fifo_level),
- .offset(32'h18),
- .rights("RO"));
- status = spi_device_reg_status::type_id::create("status");
- status.configure(.blk_parent(this));
- status.build();
- default_map.add_reg(.rg(status),
- .offset(32'h1c),
- .rights("RO"));
- rxf_ptr = spi_device_reg_rxf_ptr::type_id::create("rxf_ptr");
- rxf_ptr.configure(.blk_parent(this));
- rxf_ptr.build();
- default_map.add_reg(.rg(rxf_ptr),
- .offset(32'h20),
- .rights("RW"));
- txf_ptr = spi_device_reg_txf_ptr::type_id::create("txf_ptr");
- txf_ptr.configure(.blk_parent(this));
- txf_ptr.build();
- default_map.add_reg(.rg(txf_ptr),
- .offset(32'h24),
- .rights("RW"));
- rxf_addr = spi_device_reg_rxf_addr::type_id::create("rxf_addr");
- rxf_addr.configure(.blk_parent(this));
- rxf_addr.build();
- default_map.add_reg(.rg(rxf_addr),
- .offset(32'h28),
- .rights("RW"));
- txf_addr = spi_device_reg_txf_addr::type_id::create("txf_addr");
- txf_addr.configure(.blk_parent(this));
- txf_addr.build();
- default_map.add_reg(.rg(txf_addr),
- .offset(32'h2c),
- .rights("RW"));
-
- // create memories
- buffer = spi_device_mem_buffer::type_id::create("buffer");
- buffer.configure(.parent(this));
- default_map.add_mem(.mem(buffer),
- .offset(32'h800),
- .rights("RW"));
- endfunction : build
-
-endclass : spi_device_reg_block
-
-// Block: rv_timer
-// Class: rv_timer_reg_ctrl
-class rv_timer_reg_ctrl extends dv_base_reg;
- // fields
- rand dv_base_reg_field active0;
-
- `uvm_object_utils(rv_timer_reg_ctrl)
-
- function new(string name = "rv_timer_reg_ctrl",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- active0 = dv_base_reg_field::type_id::create("active0");
- active0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_ctrl
-
-// Class: rv_timer_reg_cfg0
-class rv_timer_reg_cfg0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field prescale;
- rand dv_base_reg_field step;
-
- `uvm_object_utils(rv_timer_reg_cfg0)
-
- function new(string name = "rv_timer_reg_cfg0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- prescale = dv_base_reg_field::type_id::create("prescale");
- prescale.configure(
- .parent(this),
- .size(12),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- step = dv_base_reg_field::type_id::create("step");
- step.configure(
- .parent(this),
- .size(8),
- .lsb_pos(16),
- .access("RW"),
- .volatile(0),
- .reset(1),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_cfg0
-
-// Class: rv_timer_reg_timer_v_lower0
-class rv_timer_reg_timer_v_lower0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field v;
-
- `uvm_object_utils(rv_timer_reg_timer_v_lower0)
-
- function new(string name = "rv_timer_reg_timer_v_lower0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- v = dv_base_reg_field::type_id::create("v");
- v.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_timer_v_lower0
-
-// Class: rv_timer_reg_timer_v_upper0
-class rv_timer_reg_timer_v_upper0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field v;
-
- `uvm_object_utils(rv_timer_reg_timer_v_upper0)
-
- function new(string name = "rv_timer_reg_timer_v_upper0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- v = dv_base_reg_field::type_id::create("v");
- v.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_timer_v_upper0
-
-// Class: rv_timer_reg_compare_lower0_0
-class rv_timer_reg_compare_lower0_0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field v;
-
- `uvm_object_utils(rv_timer_reg_compare_lower0_0)
-
- function new(string name = "rv_timer_reg_compare_lower0_0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- v = dv_base_reg_field::type_id::create("v");
- v.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(4294967295),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_compare_lower0_0
-
-// Class: rv_timer_reg_compare_upper0_0
-class rv_timer_reg_compare_upper0_0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field v;
-
- `uvm_object_utils(rv_timer_reg_compare_upper0_0)
-
- function new(string name = "rv_timer_reg_compare_upper0_0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- v = dv_base_reg_field::type_id::create("v");
- v.configure(
- .parent(this),
- .size(32),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(4294967295),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_compare_upper0_0
-
-// Class: rv_timer_reg_intr_enable0
-class rv_timer_reg_intr_enable0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field ie0;
-
- `uvm_object_utils(rv_timer_reg_intr_enable0)
-
- function new(string name = "rv_timer_reg_intr_enable0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- ie0 = dv_base_reg_field::type_id::create("ie0");
- ie0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_intr_enable0
-
-// Class: rv_timer_reg_intr_state0
-class rv_timer_reg_intr_state0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field is0;
-
- `uvm_object_utils(rv_timer_reg_intr_state0)
-
- function new(string name = "rv_timer_reg_intr_state0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- is0 = dv_base_reg_field::type_id::create("is0");
- is0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_intr_state0
-
-// Class: rv_timer_reg_intr_test0
-class rv_timer_reg_intr_test0 extends dv_base_reg;
- // fields
- rand dv_base_reg_field t0;
-
- `uvm_object_utils(rv_timer_reg_intr_test0)
-
- function new(string name = "rv_timer_reg_intr_test0",
- int unsigned n_bits = 32,
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, n_bits, has_coverage);
- endfunction : new
-
- virtual function void build();
- // create fields
- t0 = dv_base_reg_field::type_id::create("t0");
- t0.configure(
- .parent(this),
- .size(1),
- .lsb_pos(0),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- endfunction : build
-
-endclass : rv_timer_reg_intr_test0
-
-// Class: rv_timer_reg_block
-class rv_timer_reg_block extends dv_base_reg_block;
- // registers
- rand rv_timer_reg_ctrl ctrl;
- rand rv_timer_reg_cfg0 cfg0;
- rand rv_timer_reg_timer_v_lower0 timer_v_lower0;
- rand rv_timer_reg_timer_v_upper0 timer_v_upper0;
- rand rv_timer_reg_compare_lower0_0 compare_lower0_0;
- rand rv_timer_reg_compare_upper0_0 compare_upper0_0;
- rand rv_timer_reg_intr_enable0 intr_enable0;
- rand rv_timer_reg_intr_state0 intr_state0;
- rand rv_timer_reg_intr_test0 intr_test0;
-
- `uvm_object_utils(rv_timer_reg_block)
-
- function new(string name = "rv_timer_reg_block",
- int has_coverage = UVM_NO_COVERAGE);
- super.new(name, has_coverage);
- endfunction : new
-
- virtual function void build(uvm_reg_addr_t base_addr);
- // create default map
- this.default_map = create_map(.name("default_map"),
- .base_addr(base_addr),
- .n_bytes(4),
- .endian(UVM_LITTLE_ENDIAN));
-
- // create registers
- ctrl = rv_timer_reg_ctrl::type_id::create("ctrl");
- ctrl.configure(.blk_parent(this));
- ctrl.build();
- default_map.add_reg(.rg(ctrl),
- .offset(32'h0),
- .rights("RW"));
- cfg0 = rv_timer_reg_cfg0::type_id::create("cfg0");
- cfg0.configure(.blk_parent(this));
- cfg0.build();
- default_map.add_reg(.rg(cfg0),
- .offset(32'h100),
- .rights("RW"));
- timer_v_lower0 = rv_timer_reg_timer_v_lower0::type_id::create("timer_v_lower0");
- timer_v_lower0.configure(.blk_parent(this));
- timer_v_lower0.build();
- default_map.add_reg(.rg(timer_v_lower0),
- .offset(32'h104),
- .rights("RW"));
- timer_v_upper0 = rv_timer_reg_timer_v_upper0::type_id::create("timer_v_upper0");
- timer_v_upper0.configure(.blk_parent(this));
- timer_v_upper0.build();
- default_map.add_reg(.rg(timer_v_upper0),
- .offset(32'h108),
- .rights("RW"));
- compare_lower0_0 = rv_timer_reg_compare_lower0_0::type_id::create("compare_lower0_0");
- compare_lower0_0.configure(.blk_parent(this));
- compare_lower0_0.build();
- default_map.add_reg(.rg(compare_lower0_0),
- .offset(32'h10c),
- .rights("RW"));
- compare_upper0_0 = rv_timer_reg_compare_upper0_0::type_id::create("compare_upper0_0");
- compare_upper0_0.configure(.blk_parent(this));
- compare_upper0_0.build();
- default_map.add_reg(.rg(compare_upper0_0),
- .offset(32'h110),
- .rights("RW"));
- intr_enable0 = rv_timer_reg_intr_enable0::type_id::create("intr_enable0");
- intr_enable0.configure(.blk_parent(this));
- intr_enable0.build();
- default_map.add_reg(.rg(intr_enable0),
- .offset(32'h114),
- .rights("RW"));
- intr_state0 = rv_timer_reg_intr_state0::type_id::create("intr_state0");
- intr_state0.configure(.blk_parent(this));
- intr_state0.build();
- default_map.add_reg(.rg(intr_state0),
- .offset(32'h118),
- .rights("RW"));
- intr_test0 = rv_timer_reg_intr_test0::type_id::create("intr_test0");
- intr_test0.configure(.blk_parent(this));
- intr_test0.build();
- default_map.add_reg(.rg(intr_test0),
- .offset(32'h11c),
- .rights("WO"));
- endfunction : build
-
-endclass : rv_timer_reg_block
-
// Block: rv_plic
// Class: rv_plic_reg_ip0
class rv_plic_reg_ip0 extends dv_base_reg;
@@ -9985,12 +10157,12 @@
// Class: chip_reg_block
class chip_reg_block extends dv_base_reg_block;
// sub blocks
- rand hmac_reg_block hmac;
- rand gpio_reg_block gpio;
- rand flash_ctrl_reg_block flash_ctrl;
- rand uart_reg_block uart;
rand spi_device_reg_block spi_device;
+ rand flash_ctrl_reg_block flash_ctrl;
rand rv_timer_reg_block rv_timer;
+ rand gpio_reg_block gpio;
+ rand hmac_reg_block hmac;
+ rand uart_reg_block uart;
rand rv_plic_reg_block rv_plic;
// memories
rand chip_mem_rom rom;
@@ -10012,36 +10184,36 @@
.endian(UVM_LITTLE_ENDIAN));
// create sub blocks and add their maps
- hmac = hmac_reg_block::type_id::create("hmac");
- hmac.configure(.parent(this));
- hmac.build(.base_addr(base_addr + 32'h40120000));
- default_map.add_submap(.child_map(hmac.default_map),
- .offset(base_addr + 32'h40120000));
- gpio = gpio_reg_block::type_id::create("gpio");
- gpio.configure(.parent(this));
- gpio.build(.base_addr(base_addr + 32'h40010000));
- default_map.add_submap(.child_map(gpio.default_map),
- .offset(base_addr + 32'h40010000));
- flash_ctrl = flash_ctrl_reg_block::type_id::create("flash_ctrl");
- flash_ctrl.configure(.parent(this));
- flash_ctrl.build(.base_addr(base_addr + 32'h40030000));
- default_map.add_submap(.child_map(flash_ctrl.default_map),
- .offset(base_addr + 32'h40030000));
- uart = uart_reg_block::type_id::create("uart");
- uart.configure(.parent(this));
- uart.build(.base_addr(base_addr + 32'h40000000));
- default_map.add_submap(.child_map(uart.default_map),
- .offset(base_addr + 32'h40000000));
spi_device = spi_device_reg_block::type_id::create("spi_device");
spi_device.configure(.parent(this));
spi_device.build(.base_addr(base_addr + 32'h40020000));
default_map.add_submap(.child_map(spi_device.default_map),
.offset(base_addr + 32'h40020000));
+ flash_ctrl = flash_ctrl_reg_block::type_id::create("flash_ctrl");
+ flash_ctrl.configure(.parent(this));
+ flash_ctrl.build(.base_addr(base_addr + 32'h40030000));
+ default_map.add_submap(.child_map(flash_ctrl.default_map),
+ .offset(base_addr + 32'h40030000));
rv_timer = rv_timer_reg_block::type_id::create("rv_timer");
rv_timer.configure(.parent(this));
rv_timer.build(.base_addr(base_addr + 32'h40080000));
default_map.add_submap(.child_map(rv_timer.default_map),
.offset(base_addr + 32'h40080000));
+ gpio = gpio_reg_block::type_id::create("gpio");
+ gpio.configure(.parent(this));
+ gpio.build(.base_addr(base_addr + 32'h40010000));
+ default_map.add_submap(.child_map(gpio.default_map),
+ .offset(base_addr + 32'h40010000));
+ hmac = hmac_reg_block::type_id::create("hmac");
+ hmac.configure(.parent(this));
+ hmac.build(.base_addr(base_addr + 32'h40120000));
+ default_map.add_submap(.child_map(hmac.default_map),
+ .offset(base_addr + 32'h40120000));
+ uart = uart_reg_block::type_id::create("uart");
+ uart.configure(.parent(this));
+ uart.build(.base_addr(base_addr + 32'h40000000));
+ default_map.add_submap(.child_map(uart.default_map),
+ .offset(base_addr + 32'h40000000));
rv_plic = rv_plic_reg_block::type_id::create("rv_plic");
rv_plic.configure(.parent(this));
rv_plic.build(.base_addr(base_addr + 32'h40090000));
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 6f256c5..08e70a2 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -431,6 +431,13 @@
" base instance."]
}
multireg_optional = reg_optional
+multireg_optional.update({
+ 'regwen_incr': [
+ 's', "If true, regwen term increments along with current multireg " +
+ "count "
+ ],
+})
+
multireg_added = {'genregs': ['l',
"generated list of registers with required "\
"and added keys"]
@@ -891,6 +898,15 @@
mreg, mrname)
error += derr
+ # multireg specific default validation
+ regwen_incr = False
+ if 'regwen_incr' not in mreg or 'regwen' not in mreg:
+ mreg['regwen_incr'] = 'false'
+ else:
+ regwen_incr, derr = check_bool(mreg['regwen_incr'],
+ mrname + " multireg increment")
+ error += derr
+
# if there was an error before this then can't trust anything!
if error > 0:
log.info(mrname + "@" + hex(offset) + " " + str(error) +
@@ -927,7 +943,14 @@
genreg['hwext'] = mreg['hwext']
genreg['hwqe'] = mreg['hwqe']
genreg['hwre'] = mreg['hwre']
- genreg['regwen'] = mreg['regwen']
+ genreg['swaccess'] = mreg['swaccess']
+ genreg['hwaccess'] = mreg['hwaccess']
+
+ if regwen_incr:
+ genreg['regwen'] = mreg['regwen'] + str(rnum)
+ else:
+ genreg['regwen'] = mreg['regwen']
+
resval = 0
resmask = 0
bits_used = 0
@@ -969,20 +992,22 @@
closereg = True
if closereg:
- genreg['genresval'] = resval
- genreg['genresmask'] = resmask
- genreg['genbitsused'] = bits_used
- genreg['genbasebits'] = bused
- genreg['genoffset'] = offset + (rnum * addrsep)
- genreg['gendvrights'] = parse_dvrights(default_sw)
- genfields.sort(key=get_bits)
genreg['fields'] = genfields
+ genreg['genbasebits'] = bused
+ error += validate_register(genreg, offset + (rnum * addrsep),
+ width, top)
+ if error:
+ return (error, 0)
rnum += 1
bpos = 0
rlist.append(genreg)
- top['genrnames'].append(genreg['name'].lower())
+ # there is only one entry, so the index is unnecessary. Pop and re-assign names
+ # associated with the index
if len(rlist) == 1:
+ # TODO really should make the following a function that reverses the last node inserted
+ # may have more properties than just genrnames in the future
rlist[0]['name'] = mrname
+ rlist[0]['regwen'] = mreg['regwen']
top['genrnames'].pop()
mreg['genregs'] = rlist
top['genrnames'].append(mrname.lower())
@@ -1151,31 +1176,55 @@
return error, nextoff
+""" Check that terms specified for regwen exist
+Regwen can be individual registers or fields within a register. The function
+below checks for both and additional regwen properties.
+"""
def check_wen_regs(regs):
error = 0
- for x in regs['genwennames']:
- if not x.lower() in regs['genrnames']:
- error += 1
- log.error(x + " used as regwen but is not defined")
- else:
- for reg in regs['registers']:
- if ('name' in reg):
- if (reg['name'] == x):
- break
+ idx = 0
- if reg['genbitsused'] != 1:
- error += 1
- log.error(x + " used as regwen fails requirement to only " +
- "define bit 0")
- elif reg['genresval'] != 1:
- error += 1
- log.error(x + " used as regwen fails requirement to default " +
- "to 1")
- elif reg['fields'][0]['genswaccess'] != SwAccess.W1C:
- error += 1
- log.error(x + " used as regwen fails requirement to be " +
- "rw1c")
+ # Construct Tuple
+ # 0 - name
+ # 1 - reset value
+ # 2 - sw access
+ tuple_name = 0
+ tuple_rstval = 1
+ tuple_swaccess = 2
+
+ reg_list = [(reg['name'].lower(), reg['genresval'], reg['swaccess'])
+ for reg in regs['registers'] if 'name' in reg]
+ mreg_list = [
+ reg['multireg'] for reg in regs['registers'] if 'multireg' in reg
+ ]
+ field_list = [((reg['name'] + "_" + field['name']).lower(),
+ field['genresval'], field['swaccess']) for mreg in mreg_list
+ for reg in mreg['genregs'] for field in reg['fields']]
+
+ # Need to check in register names and field list in case of multireg
+ reg_list.extend(field_list)
+
+ # check for reset value
+ # both w1c and w0c are acceptable
+ for x in regs['genwennames']:
+ target = x.lower()
+ log.info("check_wen_regs::Searching for %s" % target)
+ try:
+ idx = [r[tuple_name] for r in reg_list].index(target)
+ except ValueError:
+ log.error("Could not find register name matching %s" % target)
+
+ if not reg_list[idx][tuple_rstval]:
+ error += 1
+ log.error(x + " used as regwen fails requirement to default " +
+ "to 1")
+
+ if not reg_list[idx][tuple_swaccess] in ["rw0c", "rw1c"]:
+ error += 1
+ log.error(x +
+ " used as regwen fails requirement to be W1C or W0C ")
+
return error
