[sw] Add DIF listings to i2c and rv_timer
Signed-off-by: Sam Elliott <selliott@lowrisc.org>
diff --git a/hw/ip/i2c/doc/_index.md b/hw/ip/i2c/doc/_index.md
index d5b1f07..dccf56f 100644
--- a/hw/ip/i2c/doc/_index.md
+++ b/hw/ip/i2c/doc/_index.md
@@ -372,7 +372,10 @@
| TIMING1.T_R | 0 | 134 | 402 | Atypicallly high line capacitance |
| SCL Period | 1000 | N/A | 395 | Forced longer than minimum by long T_R |
+## Device Interface Functions (DIFs)
+
+{{< dif_listing "sw/device/lib/dif/dif_i2c.h" >}}
+
## Register Table
{{<registers "hw/ip/i2c/data/i2c.hjson" >}}
-
diff --git a/hw/ip/rv_timer/doc/_index.md b/hw/ip/rv_timer/doc/_index.md
index 0b7c91d..01a113c 100644
--- a/hw/ip/rv_timer/doc/_index.md
+++ b/hw/ip/rv_timer/doc/_index.md
@@ -240,6 +240,10 @@
The RV_TIMER module also follows RISC-V Previliged spec that requires the interrupt to be cleared by updating `mtimecmp` memory-mapped CSRs.
In this case both {{<regref "COMPARE_LOWER0_0">}} and {{<regref "COMPARE_UPPER0_0">}} can clear the interrupt source.
+## Device Interface Functions (DIFs)
+
+{{< dif_listing "sw/device/lib/dif/dif_rv_timer.h" >}}
+
## Register Table
{{< registers "hw/ip/rv_timer/data/rv_timer.hjson" >}}
